: SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF TELECOMMUNICATION COURSE PLAN

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1 SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF TELECOMMUNICATION COURSE PLAN Course Code Course Title Semester Course Time Location : TE1103 : Digital Design and Modelling using VHDL. : VII : July -Nov2017 : SRM UNIVERSITY Faculty Details Sec. Name Office Mail id A Mr.S.Vijay Ananth TP13S4 vijayananth.s@ktr.srmuniv.ac.in TEXT BOOKS 1. Brown and Vranesic, Fundamentals of Digital Logic with VHDL Design, ISBN , McGraw Hill, 3rdEdition Navabi, Vhdl Modular Design, ISBN , McGraw Hill REFERENCES 1. Ercegovac. Lang & Moreno; John Wiley, Introduction to Digital Systems, ISBN , Digitized KC Chang, Digital Design and Modelling with VHDL and Synthesis An Integrated Approach, IEEE Computer Society Press, ISBN , Prerequisite : Nil Objectives: To study the basic concepts of Data Communication Networks and their performance. The course is designed around the TCP/IP model. Assessment Details Cycle Test I : 15 Marks Cycle Test II : 25 Marks Surprise Test I : 5 Marks Assignment : 5 Marks

2 Outcomes Students who have successfully completed this course Course outcome 1. To understand the working nature of different VHDL tools and design 2. To understand the various classes and types 3. To understand the various design modeling and programming on different domains. Program outcome a) Graduates will demonstrate knowledge of VHDL b) Graduates will demonstrate the ability to identify, formulate and solve engineering problems. c) Graduates will demonstrate the ability to design and test and analyze various programming concepts of different. Detailed Session Plan UNIT I INTRODUCTION Introduction to computer-aided design tools for digital systems - Hardware description Languages-example - Introduction to VHDL and data types - VHDL classes and types - VHDL Operations and overloading - Logical operators - Types of delays entity - Architecture declaration. Session No. 1 Topics to be covered Time Ref Introduction to computer-aided design tools for digital systems Teaching Method 50 1 BB Testing Method 2 Hardware description Languages-example 50 1 BB 3 Introduction to VHDL and data types 50 1 BB 4 VHDL classes and types 50 1 BB 5 VHDL data types 50 1 PP Questionare 6 VHDL Operations and overloading 50 1 BB 7 8. Logical operators Types of delays entity 50 1 BB Self test questions 50 1 BB Architecture declaration Self PP test questions UNIT II VHDL STATEMENTS Assignment statements sequential statements and process, conditional statements, case statement array and loops, resolution functions, Packages and libraries, concurrent statements, subprograms; Application of Functions and Procedures, Structural Modelling, component declaration, and generics. 10 Assignment statements 50 1 BB 11 sequential statements and process 50 1,2 BB 12 conditional statements 50 1 PP

3 13 case statement array and loops 50 1 BB 14 resolution functions 50 1,2 PP 15 Packages and libraries 50 1,2 BB 16 concurrent statements, 50 1,2 PP subprograms 17 Application of Functions and 50 1,2 BB Procedures 18 Structural Modelling, component declaration 19 declaration generics UNIT III MODELLING Behavioral Modelling process statement multiple process data flow modeling and structural modeling 20 Behavioral Modelling 50 1,2 BB 21 Sample programs 50 1,2 BB 22 Process statement 50 1,2 BB 23 Sample programs 50 1,2 PP 24 Multiple process 50 1,2 BB 25 Sample programs 26 Data flow modeling sample programs 27 Structural modeling sample programs UNIT IV COMBINATIONAL & SEQUENTIAL CIRCUIT DESIGN VHDL Models and simulation of combinational circuits such as Multiplexers, Demultiplexers, encoders, decoders, code converters, comparators, implementation of Boolean functions etc. VHDL models and simulation of sequential circuits shift registers, counters, etc 28 VHDL Models and simulation of combinational circuits 29 Multiplexers - Demultiplexers 50 1 BB 30 Encoders - decoders 31 Code converters, Comparators 50 1 BB 32 Implementation of Boolean 50 1,2 BB functions 33 VHDL models 50 1,2 BB 34 Simulation of sequential circuits 50 1,2 BB 35 Shift registers, Counters 50 1,2 BB 36 Sample Programs

4 UNIT V DESIGN OF MICROCOMPUTER & PROGRAMMING DEVICE Basic components of a computer, specifications, architecture of a simple microcomputer system, Implementation of a simple microcomputer system using VHDL programmable logic devices: ROM, PLA s, PAL s, GAL, PEEL, CPLDs and FPGA. Design implementation using CPLDs AND FPGAs 37 Basic components of a computer 50 1 PP 38 architecture of a simple 50 1 BB 39 microcomputer ROM system 50 1 BB 40 PLA s, PAL s, FPGA 50 1 PP Self test questions 41 GAL, PEEL, CPLDs 50 1 BB 42 Design implementation using CPLDs & FPGAs 50 1 PP Self test questions

5 41 NIME 50 1 BB 42 FTP 50 1 PP 43 CMIP 50 1 BB 44 SNMP 50 1 BB Self test questions 45 HTTP 50 2 BB

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Day Hour Timing pm pm am am SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF COMPUTING DEPARTMENT OF SOFTWARE ENGINEERING COURSE PLAN Course Code : SE1002 Course Title : COMPUTER ORGANIZATION AND ARCHITECTURE Semester