Take Home Final Examination (From noon, May 5, 2004 to noon, May 12, 2004)

Size: px

Start display at page:

Download "Take Home Final Examination (From noon, May 5, 2004 to noon, May 12, 2004)"

Gabriella McCormick
5 years ago
Views:

1 Last (family) name: First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 734 VLSI Array Structure for Digital Signal Processing Take Home Final Examination (From noon, May 5, 2004 to noon, May 12, 2004) I, (print your name) declare that I complete this exam without consulting any person other than the instructor and the teaching assistant of this course. I understand committing academic plagiarism will result in a failure grade of this course and will be pursued according to UW academic code of conduct to the fullest extent. Signed by:, Date: IMPORTANT! Instruction for submission of the final examination paper The final exam should be submitted by noon, Wednesday, May 12, 2004 to Room 3332 Engineering Hall. The teaching assistant will collect the final examination from 11:00 AM to 12:00 Noon. If you need to turn in your exam paper earlier, please send contact her. You MUST submit the first TWO PAGES as the cover pages of your final exam paper. STAPLE the exam and number each page. The answer should be printed neatly or typewritten. Messy answer sheet may cause the instructor to miss your answer and result in losing additional points. IMPORTANT! Question Answering Period On MONDAY, May 10, 10:00-noon, Prof. Hu will be at 3625 EH answering questions related to this final examination. After that, he can be contacted only by . Page 1 of 7

2 Problem Max. pts Points Total 100 Page 2 of 7

3 1. (30 points) Digital IIR Filter Implementation Consider the following IIR digital filter. a 1, a 2, b 0, b 1, and b 2 are filter coefficients, A1 A4, M1 M5 are labels for the adders and multipliers. x(n) A1 A2 M1 a 1 a 2 b 0 u(n) M3 D b 1 u(n 1) M4 D b 2 A3 A4 y(n) M2 u(n 2) M5 (a) (2 points) Assume that each multiplication takes T M time units, and each addition takes T A time units. Find the iteration bound of this IIR filter structure in terms of T M and T A. (b) (2 points) Draw the signal flow graph of this corresponding block diagram. (c) (2 points) Draw a data flow graph of the block diagram. Label each node with A1, M1, etc. (d) (2 points) Identify all the critical paths you can find. Specify the path in terms of labels for adders and multipliers. Also, compute the critical path delay T cr. (e) (2 points) Assume that T M = 2 t.u., and T A = 1 t.u. Determine the minimum sampling duration of this block diagram. (f) (3 points) Use retiming, unfolding, or other method to modify the block diagram so that the sampling duration is T while the increase of the number of registers is minimized. (g) (5 points) Apply unfolding to this IIR structure once, and plot the transformed DFG. Label the adders and multipliers as Aik and Mik where k = 0, 1 indicates different iterations. For example, A1 will becomes A10 and A11. Give the table such as shown in the unfolding class note specifying which edge will be mapped from where to where and how many delays will be associated with it. (h) (2 points) Give the transfer function of this IIR filter (i) (5 points) Assume that T M = 2 t.u., and T A = 1 t.u. If a 1 = 0.8, a 2 = 0.15, b 0 = 2, b 1 = 0.8, and b 2 = 0. Apply look-ahead transformation so that the loop bound can be reduced to T 2 t.u. Give the IIR equations of the transformed filter structure, and compute the new loop bound T,new. (j) (5 points) Continue part (i), implement the transformed IIR filter so that it can process one input data sample for every 2 t.u. Discuss your design decisions, draw the corresponding DFG and the final block diagram of the implementation. Also, show that this implementation can run on a clock cycle time of 2 t.u. Page 3 of 7

4 2. (10 points) Retiming, unfolding Assume that the node computing time at each node is 1 t.u D (a) (5 points) Use the cutest-retiming to convert above DFG into a fully pipelined implementation that has at least 1 delay on every data link. (b) (5 points) Use the retiming procedure described in section in the text book to perform the retiming task. 3. (10 points) Implementation of DSP algorithms on MMX and PDSPs (a) (5 points) An important arithmetic operation that has been implemented in multimedia extension instructions is saturated arithmetic. Let us consider an MMX instruction: Packed add with saturation for word (PADDSW): PADDSW M2, M4 That is to say, adding the four words in M2 register to those of the M4 register using saturation arithmetic and store the results back to the M2 register. Here each word contains 16 bits, and is in two s complement representation. Hence in hexadecimal representation, the maximum is 7FFF and the minimum is You are to handsimulate this instruction by specifying the content of M2 register after the execution of this instruction. Answer: MM F FFFF MM4 FFFF F MM2 (b) (5 points) One naïve, yet feasible method to implement saturation arithmetic is to first evaluate the addition result, and then make corrections. (Note that two s complement subtraction can be realized by taking the two s complement of the minuend and then perform addition.) Let us consider a four-bit 2 s complement adder example. Modify a generic 4-bit ripple carry adder/subtractor to implement the signed saturation arithmetic. 4. (10 points) Algorithm transformation Consider a IIR filter K 7 yn ( ) = ak ( ) yn ( k) b( jun ) ( j) k= 1 j= 0 where n = 0, 1, 2,. Also, assume that u(n) = 0, and y(n) = 0 for n < 0. For the special case J = 0, and b(0) = 1, perform the following task. (a) (3 points) write a high level language (HLL) program listing that implement above algorithm. (b) (3 points) Convert this HLL program listing into the single assignment format. J Page 4 of 7

5 (c) (4 points) For K = 3, J = 0, and 0 n 5, plot a localized DG corresponding to this algorithm. Assume that at each node, a single MAC operation will be performed. If the DG you obtained is not a localized DG, you need to consider modify the algorithm to make it localized. 5. (10 points) Mapping nested do-loop algorithms to processor arrays Given an algorithm in the single-assignment format and with localized data propagation as follows: for k = 1 to N for i = k to N for j = k to N if i = k then b(i,j,k) = c(i,j,k-1) else b(i,j,k) = b(i-1, j, k) if j = k then a(i,j,k) = c(i,j,k-1)/b(i,j,k) else a(i,j,k) = a(i,j-1,k) c(i,j,k) = c(i,j,k-1)-a(i,j,k)b(i,j,k) end end end Suppose that the input nodes in the DG are [i j 1] T, the output nodes are [i k k] T, and [k j k] T for the appropriate range of i, j, and k. (a) (3 points) Let N = 4, plot the slices of the 3D DG for k =1, 2, 3, and 4. Use the origin of coordinate as depicted below: j (b) (2 points) Identify the (inter-iteration) data dependence matrix D. (c) (5 points) Perform node mapping, arc mapping, and I/O mapping assuming that d T = s T = [1 1 1]. 6. (5 points) Huffman decoding Let us consider the following Huffman table i Symbol Codeword a (000) 0 b (001) 10 c (010) 1100 d (011) 1101 e (100) 1110 f (101) 1111 Develop a finite state machine that can decode the symbols at a rate of one input bit per clock cycle. For convenience, denote the input as w, the output symbol will be encoded with three Boolean variables x, y, z. The code assignment is specified in the parenthesis in the table. Use binary code 111 to indicate that there is NO symbol output at the present clock cycle. Give your answer as a state table corresponding to a Mealy model sequential machine. Page 5 of 7

6 7. (10 points) This part is independent of parts (a)-(c). Assuming that 16 bits will be sufficient to implement the DCT algorithm. Below is a code segment that implements two-point DCT operation y0 1/ 2 1/ 2 x0 y = 1 1/ 2 1/ 2 x 1 void fsadct2_mmx (short in[2], short out[2]) { static int64 xstatic1 = 0xA57E5A825A825A82; // -f0 f0 f0 f0 static int64 rounding = 0x ; asm { mov eax, in // in is address of x1, x0 mov ecx, out // out is address of y1, y0 movd mm0, [eax] // [mm0] = [xx xx x1 x0] pshufw mm1, mm0, b // [mm1] = [x1 x0 x1 x0] pmaddwd mm1, xstatic1 // [mm1] = [x0f0-x1f0 x0f0x1f0] paddd mm1, rounding // do proper rounding psrad mm1, 15 packssdw mm1, mm7 // [mm1] = [xx xx y1 y0] movd [ecx], mm1 } } (a) (5 points) Trace this program starting from the line movd mm0, [eax], and specify the content of the destination register in the hexa-decimal format in the clock cycle after each assembly instruction is executed. Assume that x1=017a h, x0 = 00AC h, and that all MMX registers are initially cleared. You may use the Intel document no , IA-32 Intel Architecture Software Developer's Manual, Vol. 2 Instruction Set Reference (available at MMX references on class web page) to help out with MMX instructions. Refer to the instruction packssdw, note that figure 3-5 in that manual is incorrect. Read the operations in the following page. Answer: Instruction executed Movd mm0, [eax] Pushfw mm1, mm0, b [mm1] = Content of Register [mm0] = A 00AC h Pmaddwd mm1, xstatic1 [mm1] = h Paddd mm1, rounding [mm1] = h Psrad mm1, 15 [mm1] = h Packssdw mm1, mm7 [mm1] = h Movd [ecx], mm1 Results stored into memory h Page 6 of 7

7 (b) (5 points) Explain the purpose of these two lines in the program, and verify that they are correct for what they are meant for perform: paddd mm1, rounding psrad mm1, (15 points) Implementation of digital frequency synthesizer Below is a diagram of a phase accumulation digital frequency synthesizer (DFS). clk δ K-bit Register φ(nt) Sin(x) ROM 2 K b y(nt): To DAC The basic idea is as follows. Let us consider n-th discrete time instance nt where T is the clock period of the external clock that triggers the register. The phase at this time instance is (( n 1) T) = ( nt) = 0 ( n 1) φ φ δ φ δ where φ(0) = φ 0, δ = dφ is the known phase increment and is a positive integer. The output (to digital to analog converter DAC) is obtained as: ( π φ( ) ) π ( δ φ0 ) ( ) ynt ( ) = sin 2 nt / K = sin 2 n / K where K = 2 k is the number of different outputs from the register REG. For convenience, assume K is an integer multiple of δ. (a) (5 points) Using parameters δ, T, and K, derive a formula to express the fundamental frequency f 0 (in hertz) of the analog output after the DAC. (b) (5 points) There are three sources of hardware propagation delay may occur in the DFS circuit shown above: The adder delay, the setup time plus propagation delay of the register REG, and the read delay of the ROM. Assume that the delay through the adder is 2ns, the setup time and the propagation delay of the register is 1ns, and the read delay of the ROM is 5ns. What is the highest fundamental frequency f 0 this DFS can generate? (c) (5 points) Suppose our objective is to design a DFS that can generate sinusoidal frequency up to 50 Mhz with at least 5 data points per period (cycle). Given the same type of hardware as above, namely, adder delay 2 ns, register setup time plus propagation delay of 2ns, and ROM read latency 5ns. Design a DFS that achieve the design objective. Give a block diagram of your design and specify parameters T, K, δ, and compute the highest frequency of the sinusoidal signal this DFS can synthesize. Page 7 of 7

Midterm Exam Thursday, October 24, :00--2:15PM (75 minutes)

Midterm Exam Thursday, October 24, :00--2:15PM (75 minutes) Last (family) name: Answer Key First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 551 Digital System Design and Synthesis Midterm