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1 1 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
2 Bixby: the Scalability and Coherence Directory ASIC in Oracle's Highly Scalable Enterprise Systems Thomas Wicki and Jürgen Schulz Senior Principal Hardware Engineers, Microelectronics Hot Chips 25 August 25-27, 2013
3 The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle s products remains at the sole discretion of Oracle. 3 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
4 Outline Motivation and Design Objectives M5 System and Beyond System RAS Features Implementation Details Debug and DFT Features Summary 4 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
5 - T Motivation SL SL M5 and M6 s direct interconnects scale up to 8 processors using Coherence Links (CL) (Glueless system) To enable systems to scale beyond 8 processors: Scalability Links (SL) were added to M5 and M6 SL SL M6 M6 M6 CL M6 M6 M6 SL SL Bixby ASICs are needed (Glued system) M6 SL M6 SL 5 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
6 Bixby Design Objectives Scalable up to 96 processors Communication switch between 8-processor SMPs Large System Scaling Bixby Coherence Directory & Processing Directory for L3 caches of all processors Multi-generation support Enabling mixed processor systems Enterprise System Focus Enterprise-Class RAS feature set High bandwidth, low latency 6 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
7 Challenges and Trade-Offs Directory Size Directory Width Challenge Large directory size requirement Massive number of L3 cache ways x number of processors per look-up Solution Scale up number of Bixbys with system size Pipeline look-ups Switch Size 24 x 24 crossbar efficiency Overprovision switching bandwidth Shared Resources Some resources shared by multiple hardware domains Associate errors with single domain and clean up shared resources after error 7 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
8 Outline Motivation and Design Objectives M5 System and Beyond System RAS Features Implementation Details Debug and DFT Features Summary 8 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
9 Oracle s M5-32 System 32 M5 SPARC processors 12 Bixbys 4 physical (hardware) domains 3.1TB/s payload coherence bandwidth 1.5TB/s payload scalability bandwidth Bixbys 9 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
10 M5-32 System Coherence Interconnect Coherence Links (CL) 12 lanes per direction Scalability Links (SL) 4 lanes per direction 12Gbps per lane 7 CLs + 6 SLs per processor 16 SLs per Bixby 10 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
11 Scalability Link Bandwidth 11 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
12 Outline Motivation and Design Objectives M5 System and Beyond System RAS Features Implementation Details Debug and DFT Features Summary 12 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
13 Physical (Hardware) Domain Support S S S S S S S S Domain A S S S S S S S S Domain B BX BX BX BX S S S S S S S S Domain A S S S S S S S S Domain C Up to 12 physical domains Dynamically configurable by Service Processor Packet filtering and Physical Address fencing Errors resolved to physical domain Per-domain Cease Operation support 13 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
14 5-of-6 Redundancy Mode Normal configuration: BX BX BX BX BX BX BX BX BX BX BX BX Failover configuration: BX BX BX BX BX BX BX BX BX BX BX BX Still Boots! System can boot with any 5 out of each group of 6 Bixbys Increases availability since system can be used until service is performed 14 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
15 Hot Maintenance Support S S S S S S S S Domain A S S S S S S S S Domain A In a running system, failing Bixby or SMP can be: BIST BX BX BX BX IBIST Replaced Tested Re-integrated S S S S S S S S Domain B BIST S S S S S S S S New SMP 15 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
16 Link Protection CRC check and auto retry Replay, if CRC error detected Guaranteed lane failure detection Built in PRBS testing during link training Auto link re-initialization Re-training link, if Replay unsuccessful No Service Processor intervention required Auto single lane failover (per direction) Based on PRBS testing No Service Processor intervention required SL Chip A LFU LFU Chip B 16 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
17 Outline Motivation and Design Objectives M5 System and Beyond System RAS Features Implementation Details Debug and DFT Features Summary 17 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
18 Implementation Details 96 Tx + 96 Rx 16Gb/s Long-Reach AC coupled SerDes Package: 45mm x 45mm 1677-pin FPBGA (~500 signal IO) Process: 28nm 10 layer metal 0.85V ASIC ~160 Mbits SRAM (~20MB Tags) ~70M Gates (nand2 equivalent) 18 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
19 Functional Blocks Forward Packet SerDes Links (24 x4) Link Framing Units (LFU) LQU Input Queues (IQU) ASU Crossbar In (AXI) Forwarding Crossbar (FXU) Address Serialization Units ASU ASU ASU ASU ASU ASU ASU ASU ASU Crossbar Out (AXO) LQU Output Queues (OQU) Link Framing Units (LFU) SerDes Links (24 x4) 19 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
20 Functional Blocks SerDes Links (24 x4) Directory Lookup Link Framing Units (LFU) LQU Input Queues (IQU) ASU Crossbar In (AXI) Forwarding Crossbar (FXU) Address Serialization Units ASU ASU ASU ASU ASU ASU ASU ASU ASU Crossbar Out (AXO) LQU Output Queues (OQU) Link Framing Units (LFU) SerDes Links (24 x4) 20 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
21 Floorplan CRC/Retry CRC/Retry CRC/Retry CRC/Retry ECC for Datapath Parity for Control CRC/Retry CRC/Retry CRC/Retry CRC/Retry SEC-DED on all major datapaths Parity on control signals Custom top level wires on top two routing layers Critical nets implemented by Buffer on route Faster ps/mm PVT invariant clock distribution 21 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
22 Link Queuing Unit (LQU) Forwarding Crossbar (FXU) Link Framing Units (LFU) LQU Input Queues (IQU) ASU Crossbar In (AXI) Address Serialization Units ASU ASU ASU ASU ASU ASU ASU ASU ASU Crossbar Out (AXO) LQU Output Queues (OQU) Link Framing Units (LFU) Each manages an x4 Scalability Link Provides queuing support for multiple Virtual Channels Each LQU is part of a single physical domain SEC-DED on Link FIFOs (RAM based) 22 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
23 % Efficiency Cross Bar Units (XBU) A separate data path forwards traffic and is sized to account for any Head-of-Line blocking inefficiencies FXU: 24in x 24out (2-cycle packet) AXI: 24in x 8out AXO: 16in x 24out Switch fabrics implemented as custom layout hard macros Bixby fully sustains mixed request and data traffic at full line rate FXU is single domain, AXI/AXO are multi-domain logic Flow through SEC-DED, parity on routing control Forwarding Crossbar (FXU) Link Framing Units (LFU) LQU Input Queues (IQU) Switch Efficiencies FXU AXI AXO ASU Crossbar In (AXI) Address Serialization Units ASU ASU ASU ASU ASU ASU ASU ASU ASU Crossbar Out (AXO) LQU Output Queues (OQU) Link Framing Units (LFU) Output Input 23 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
24 Address Serialization Unit (ASU) Partitioned into eight parallel units Each directory unit can compare and process up to 22,656 bits per cycle (total 181,248 bits per chip per cycle) 0.5 request lookups per cycle (total 4 per chip) Flow-through correction on incoming packets and tag directory contents Retry on directory tag staging flops Supports up to 12 hardware domains with error steering Per domain Built-In Self Initialization (BISI) Tag RAM scrubber Forwarding Crossbar (FXU) Link Framing Units (LFU) LQU Input Queues (IQU) ASU Crossbar In (AXI) Address Serialization Units ASU ASU ASU ASU ASU ASU ASU ASU ASU Crossbar Out (AXO) LQU Output Queues (OQU) Link Framing Units (LFU) 24 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
25 Outline Motivation and Design Objectives M5 System and Beyond System RAS Features Implementation Details Debug and DFT Features Summary 25 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
26 Debug and DFT Features Monitoring link at full signaling speed is challenging Two internal rings to allow capturing packet flow in ingress or egress direction Internal triggering logic and RAM to store packet flow External DDR interface to allow capturing packet flow on Logic Analyzer In-system test features: MemBIST InterconnectBIST ASU tag RAM can be read, written or read-modify-write 26 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
27 Outline Motivation and Design Objectives M5 System and Beyond System RAS Features Implementation Details Debug and DFT Features Summary 27 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
28 Bixby Design Objectives Accomplished Scales to 96 processors Provides communication switching between 8-processor SMPs Large System Scaling Bixby Coherence Directory & Processing Directory for L3 caches of all processors Multi-generation support Enabling mixed processor systems Enterprise System Focus Enterprise-Class RAS feature set High bandwidth, low latency invisible 28 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
29 Bixby Scalability ASIC Hosts L3 cache directory Processes coherence requests Includes comprehensive Enterprise-Class RAS Provides extensive debug and DFT features Pushes ASIC boundaries: technology, complexity, die size, SerDes count, power, Flexible scaling up to 12x Glueless systems Glued systems 29 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
30 30 Copyright 2013 Oracle and/or its affiliates. All rights reserved. Q&A
31 References White Paper: SPARC M5-32 Server Architecture Data Sheets: SPARC M5-32 Server SPARC M5 Processor processor-ds pdf 31 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
32 Glossary BISI Built-In Self Initialization BIST Built-In Self Test BX Bixby ASIC CL Coherence Link CRC Cyclic Redundancy Check IBIST Interconnect Built-In Self Test MemBIST Memory Built-In Self Test PRBS Pseudo-Random Binary Sequence PVT Process Voltage Temperature RAS Reliability Availability Serviceability SEC-DED Single-bit Error Correction - Double-bit Error Detection SL Scalability Link SMP Shared Memory Processor SPARC - Scalable Processor ARChitecture 32 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
33 33 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
34 34 Copyright 2013 Oracle and/or its affiliates. All rights reserved.
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