EE552 Extra Credit Project

Transcription

1 EE552 Extra Credit Project Publications on Hazard-Free Implementations Submitted by: Rabia Essani

2 List of the Papers included in this report: Algorithms for synthesis of hazard-free asynchronous circuits (1991) L. Lavagno Dept. of EECS University of California, Berkeley K. Keutzer. Proc. ACM/IEEE Design Automation Conference. URL: Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes.(1992) Steven M. Nowick David L. Dill Department of Computer Science Department of Computer Science Columbia University Stanford University New York, NY Stanford, CA URL: Synthesis of verifiably hazard-free asynchronous control circuits (1990) L. Lavagno Dept. of EECS University of California, Berkeley K. Keutzer AT&T Bell Laboratories Murray Hill, NJ A. Sangiovanni-Vincentelli Dept. of EECS University of California, Berkeley November 9, 1990 URL: Symbolic Hazard-Free Minimization and Encoding of Asynchronous Finite State Machines(1995) _ Robert M. Fuhrer Bill Lin Steven M. Nowick Dept. of Computer Science IMEC Laboratory Dept. of Computer Science Columbia University Kapeldreef 75 Columbia University New York, NY B-3001 Leuve, Belgium New York, NY URL:

3 Fast Heuristic and Exact Algorithms for Two-Level Hazard-Free Logic Minimization(1998) Michael Theobald and Steven M. Nowick IEEE Transactions on Computer-Aided Design URL: Hazard-Free Implementation of the Self-Timed Cell Set in a Xilinx FPGA(1994) Kapilan Maheswaran Venkatesh Akella maheswar@ece.ucdavis.edu akella@ece.ucdavis.edu Computer Engineering Research Laboratory Department of Electrical & Computer Engineering University of California Davis, CA URL: Direct Synthesis of Timed Asynchronous Circuits Sung Tae Jung and Chris J. Myers Electrical Engineering Department University of Utah Salt Lake City, UT URL: dffiles/06a_4.pdf Synthesis of Asynchronous Circuits for Stuck-at and Robust Path Delay Fault Testability(1995) Steven M. Nowick Niraj K. Jha Fu-Chiung Cheng Dept of Computer Science Dept of Electrical Engg. Dept of Computer Science Columbia University Princeton University Columbia University New York, NY Princeton, NJ New York, NY Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gc Finite State Machines Hans Jacobson Chris Myers Ganesh Gopalakrishnan Dept. of Computer Science Dept. of Electrical Engg. Dept. of Computer Science University of Utah University of Utah University of Utah hans@cs.utah.edu myers@ee.utah.edu ganesh@cs.utah.edu URL:

4 Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-Free Implementations) Kenneth Y. Yun, Member, IEEE David L. Dill, Member, IEEE URL: Additional papers related to hazard-free implementation and other topics of logic circuits can be found at the following locations: The Asynchronous Bibliography BIBT E X database file async.bib Ad Peeters April 20, 2001 URL: /iccad00/htmfiles/sun_sgi/frames/iccadai.htm

5 Objective In this report I am trying to compile all the publications on hazard free implementation. I am going to provide the abstract and conclusion of each paper as well as the URL at which the complete paper can be found. Apart from the abstract I have also included a basic overview of the whole paper so that it is easier for the reader to take advantage of finding the appropriate paper for him/her. At the end of the report I have also included a URL where most of the older publications can be found. Algorithms for synthesis of hazard-free asynchronous circuits (1991) L. Lavagno Dept. of EECS University of California, Berkeley K. Keutzer. Proc. ACM/IEEE Design Automation Conference. URL: Abstract: A technique for the synthesis o asynchronous sequential circuits from a Signal Transition Graph (STG) specification is described. We give algorithms for synthesis and hazard removal, able to produce hazard free circuits with bounded wire delay model, requiring the STG to be live, safe and to have the unique state coding properly. A proof that, STG persistency is not necessary for hazard-free implementation is given. Overview Asynchronous design is important in several applications of digital design. Real world interfaces and low power systems, where lazy evaluation style designs may extend the average life of a battery, are two examples. In addition, clock skew problems limit the performance and the flexibility of large-scale synchronous systems. On the other hand asynchronous design is harder and more constrained than synchronous design, due to the hazard problem: asynchronous circuits are by definition sensitive to all signal changes, whether they are intentional (i.e. part of specification) or not (then they are called hazards).an example of such unintentional changes, is the oscillation of a signal that is supposed to have a single transition. Historically two main models of operation for an asynchronous circuit have been used: The Huffman model. The Muller model.

6 Recently, [Chu87] introduced a specification formalism for asynchronous circuits called Signal Transition Graph (STG), that is based on Petri nets to explicitly model concurrency. It overcomes the specification size problem, but the synthesis procedure given by [Chu87] does not guarantee hazard-free operation, unless a possibly unrealistic delay model is used. In a previous paper ([LKSV91]) we have shown that hazard-free asynchronous logic design from STG specification can be done, using the bounded wire-delay model, with an appropriate synthesis technique, and we show the results of its application to some circuit examples, while the interested reader is referred to [LKSV90] for the proofs. Conclusion and Future work: The principal target of this paper was to give practical algorithms for hazard free syntheses of asynchronous circuits from live STG s with the USC property. The algorithms rely on knowing bounds on the delays in the circuit, and use the wire delay model. No fundamental mode assumption is required (unlike [Ung69]). One noticeable consequence of this work is that STG persistence can no longer be considered a necessary or sufficient condition for hazard-free implementation. This is a desirable result, since enforcing persistence reduces the concurrency at the STG level. So we can claim that if the speed measure is the global throughput of the circuit, and if the throughput is bound by the amount of parallelism in the implementation, ours is the fastest solution that can be obtained from the given STG Specification. Notice also that liveness and USC are only sufficient condition for an STG to have a hazard free implementation, since our procedure is based on the assumption that only the values of signals specified by the STG can be used as state variables to encode the SG. So in order to give necessary and sufficient conditions for hazard free implementation, we will have to remove the restriction on the state assignment technique, and state those conditions in terms of properties of both the STG specification and the state assignment procedure. Moreover, since the hazard freeness property relies on delay bounds, we must be able to perform delay tests on the circuit [Smi85] in order to ensure that these bounds are met by the manufactured circuits. This requires to be able to synthesize a circuit that retains the hazard properties of the two level implementation examined in this paper but is delay fault testable. This topic will be discussed in a forthcoming paper.

7 Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes.(1992) Steven M. Nowick David L. Dill Department of Computer Science Department of Computer Science Columbia University Stanford University New York, NY Stanford, CA URL: Abstract This paper describes a new method for exact hazard-free logic minimization of Boolean functions. Given an incompletely-specified Boolean function, the method produces a minimum-cost sum-ofproducts implementation which is hazard-free for a given set of multiple-input changes, if such a solution exists. The method is a constrained version of the Quine-McCluskey algorithm. It has been automated and applied to a number of examples. Results are compared with results of a comparable non-hazard-free method (espresso-exact). Overhead due to hazard-elimination is shown to be negligible. Overview There has been renewed interest in asynchronous design because of the potential benefits of improved system performance, modular design, and avoidance of clock skew. However, a major obstacle to correct asynchronous design is the problem of hazards, or undesired glitches in a circuit. The elimination of all hazards from asynchronous designs is an important and difficult problem. Many existing design methods do not guarantee freedom from all hazards; other methods are limited by harsh restrictions on input behavior (single-input changes only) or implementation style (the use of large, slow inertial delays) to insure correct operation. The focus in this paper is on particular class of hazards: hazards in combinational logic. The design of hazard-free combinational logic is critical to the correctness of most asynchronous designs. Out goal is the synthesis of combinational logic, which avoids all combinational hazards for a given set of multiple-input changes. The contribution of this paper is a solution to an open problem in logic synthesis: Given

8 an incompletely-specified Boolean function and a set of multiple-input changes, produce an exact minimized two-level implementation which is hazard-free for every specified multiple-input change, if such a solution exists. The method has been automated and applied to a number of examples. Results are compared with results of a comparable nonhazard-free method. Overhead due to hazard elimination is shown to be negligible. Our method is a constrained version of the Quine-McCluskey algorithm. Conclusions This paper considers the two-level hazard-free minimization problem for several reasons: the general problem has not previously been solved; minimal two-level solutions are important for optimal PLA implementations; and solutions serve as good starting point for hazard-free logic transformations. In particular, multi-level transformations, which introduce no hazards into a combinational network, are discussed in [35]. This set of transformations has been significantly extended by Kung [14]. Finally, technologymapping algorithms, which introduce no hazards, are described by Siegel el at. [34]. We have described the problem of implementing hazard-free two-level logic as a constrained covering problem on Karnaugh maps. We presented an automated algorithm for solving the two-level hazard-free logic minimization problem and showed its effectiveness on a set of examples. An important feature of the algorithms is that they involve only localized changes to existing algorithms. As a result, we can use existing sophistical algorithms for prime implicant generation (Step 1) and for table reduction and solution (Step 3). Our algorithms have implications for testability, since they may introduce redundant and non-prime implicants. In this case, the resulting circuits may have non-testable faults. However, recent methods have been proposed which insure complete testability of hazard-free logic, for both stuck-at and robust path delay faults, in the presence of redundant [13,30] and non-prime [30] implicants. Therefore, testability need not be adversely affected when hazards are removed. With the automation of these exact algorithms, the basic automated synthesis system of [28] is complete. The algorithms have been incorporated into two other synthesis systems as well [38,26] and can be used in a number of other sequential synthesis methods. The

9 algorithms have also been applied to several substantial asynchronous designs, including a second-level cache controller [27] and state machines for an infrared communications chip [1]. Synthesis of verifiably hazard-free asynchronous control circuits (1990) L. Lavagno Dept. of EECS University of California, Berkeley K. Keutzer AT&T Bell Laboratories Murray Hill, NJ A. Sangiovanni-Vincentelli Dept. of EECS University of California, Berkeley November 9, 1990 URL: Abstract A synthesis technique for asynchronous sequential control circuits from a high level specification, the Signal Transition Graph (STG) is described. The synthesis technique is guaranteed to generate hazard-free circuits with the unbounded gatedelay model and the bounded wire-delay model, if the STG is live, safe and has the unique state coding property. A proof that STG persistency is not necessary for hazard-free implementation is given. 1 Introduction Asynchronous sequential circuit design has always been a controversial topic. In the early years of electronic circuit design, when the size of the circuits was such that a human designer could keep track of the complex timing issues. Overview Asynchronous sequential circuit design has always been a controversial topic. In the early years of electronic circuit design, when the size of the circuits was such that a human designer could keep track of the complex timing issues involved, it was a popular design style (see [Ung69] for a thorough review). Then synchronous logic dominated the VLSI

10 era, when the ease of design of clocked circuits overwhelmed the advantages of the asynchronous style. Asynchronous design, still, has always been around, at least in the restricted domain of interfaces to the external world, asynchronous by definition. However it was usually limited to finding a good and reliable way to synchronize signals with the internal clock. Recently there has been a revival of interest in asynchronous self-timed circuits ([Sei81]) due to their desirable properties: 1. The clock-skew problem, getting worse and worse in synchronous sub-micron designs, disappears completely. 2. System-level latency is no longer dictated by the worst-case delay, but by the average delay. For example, a self-timed adder can signal when the result on its outputs is valid and stable, rather than always wait for the worst delay of the carry chain. These properties are counterbalanced by a more constrained design procedure and, often, by an increase in area, power consumption and worst-case delay. In this paper we will give a procedure transforming a formal, technology-independent specification, called Signal Transition Graph (introduced by [Chu87]), into a circuit implementation made out of basic gates such as nands, nors and S-R flip-flops. We want to prove that the output of our procedure does not have hazards. In order to do so, we must define what delay model we are going to use for our circuit implementation. _ The unbounded gate-delay model ([Ung69]) assumes that wires interconnecting gates have zero delay, and that all paths inside each gate (including flip-flops) have exactly the same delay. It also assumes that no bounds are known on the delay of each gate. _ The unbounded wire-delay model assumes that each connection between a gate output and another gate input can have an unbounded delay. _ The bounded wire-delay model assumes that each connection between a gate output and another gate input can have a delay. In this model the amount of delay from each input to each output of a complex gate is a function of the load on the gate output. The function depends both on the input that we consider and on the actual circuit used to implement the gate. This delay is called nominal delay. Because of statistical fluctuations in the manufacturing process and of modeling errors, for example the delay on the wires themselves, a lower and an upper bound on the nominal delay are considered when verifying the circuit with timing analysis. This delay model was introduced by [Huf54] (together with the assumption, that we shall not make, that input changes are applied only when the circuit is known to be stable).

11 Conclusions and future work The principal target of this paper was to show that each live STG s with the USC property has a hazard-free asynchronous implementation, using both the unbounded gatedelay and the bounded wire-delay models. In order to prove this, we gave a synthesis procedure, and we examined what were the hazard properties of the result of each step, taking care that we did not introduce new causes of hazards, and we removed old ones at each step. One important consequence of this work is that persistence can no longer be considered a necessary condition for hazard-free implementation. This is a desirable result, since enforcing persistence reduces the concurrency at the STG level. So we can claim that if the speed measure is the global throughput of the circuit, and if the throughput is bound by the amount of parallelism in the implementation, ours is the fastest solution that can be obtained from the given STG specification. Notice that liveness and USC are only sufficient conditions for an STG to have a hazard-free implementation, since our procedure is based on the assumption that only the values of signals specified by the STG can be used as state variables to encode the SG. So in order to give necessary and sufficient conditions for hazard-free implementation, we will have to remove the restriction on the state assignment technique, and state those conditions in terms of properties of both the STG specification and the state assignment procedure. Symbolic Hazard-Free Minimization and Encoding of Asynchronous Finite State Machines(1995) _ Robert M. Fuhrer Bill Lin Steven M. Nowick Dept. of Computer Science IMEC Laboratory Dept. of Computer Science Columbia University Kapeldreef 75 Columbia University New York, NY B-3001 Leuve, Belgium New York, NY URL: Abstract This paper presents an automated method for the synthesis of multiple-input-synchronous synthesis logic must be implemented without hazards, change (MIC) asynchronous state machines. Asynchronous state machine design is subtle since, unlike synchronous synthesis, logic must be implemented without hazards and state codes must be chosen carefully to avoid critical races. We formulate and solve an optimal hazard free and critical race-free encoding problem for a class of MIC asynchronous state machines called burst-mode. Analogous to a paradigm success-fully used for the optimal encoding

12 of synchronous machines, the problem is formulated as an input-encoding problem. Implementations are targeted to sum-of-product realizations. We believe this is the first general method for the optimal encoding of hazard-free MIC asynchronous state machines under a generalized fundamental mode of operation. Results indicate that improved solutions are produced, ranging up to 17% improvement. Overview There has been a renewed interest in asynchronous design, because of their potential for high-performance, modularity and avoidance of clock skew. This paper focuses on one class of asynchronous designs: asynchronous state machines. Several methods have recently been introduced for the synthesis of asynchronous state machines [9, 17, 8]. These methods have been automated and produce low-latency machines, which are guaranteed hazard-free at the gate-level. The design tools have benefited from a number of hazard-free optimization algorithms: exact two-level logic minimization [10], multi-level logic optimization [15, 3, 4], and technology mapping [13]. However, none of these methods includes algorithms for optimal state assignment. The contribution of this paper is a general method for the optimal state assignment of asynchronous state machines. Optimal state assignment of synchronous machines has been an active area of research. De Micheli [7] formulated and solved an input-encoding problem, which approximates an optimal state assignment for PLA-based state machines. Other formulations as an output encoding or input/output encoding problem have also been developed [6, 16, 12, 1]. A key contribution of our method is that it produces exactly minimal hazard-free (twolevel) output logic, over all possible critical race-free assignments. This result is significant since the latency of an asynchronous machine is determined by its output logic: there are no clock or latches. For next-state logic, our approach leads only to an approximate solution. However, in practice, high quality solutions are produced for nextstate logic as well, ranging up to 17% overall improvement. We believe this is the first general method for the optimal state assignment of hazard-free MIC asynchronous state machines.

13 Fast Heuristic and Exact Algorithms for Two-Level Hazard-Free Logic Minimization(1998) Michael Theobald and Steven M. Nowick IEEE Transactions on Computer-Aided Design URL: Abstract None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and automated circuit partitioning techniques. This paper introduces two new 2-level hazard-free logic minimizers: Espresso-HF, a heuristic method, which is loosely based on Espresso-II, and Impymin, an exact method based on implicit data structures. Both minimizers can solve all currently available examples, which range up to 32 inputs and 33 outputs. These include examples that have never been solved before. For the more difficult examples that can be solved by other minimizers, our methods are several orders of magnitude faster. As by-products of these algorithms, we also present two additional results. First, we propose a fast new method to check if a hazard-free covering problem can feasibly be solved. Second, we introduce a novel reformulation of the 2-level hazard-free logic minimization problem, by capturing hazard-freedom constraints within a synchronous function through the addition of new variables. Overview Asynchronous design has been the focus of much recent research activity. In fact, asynchronous designs have been applied to several large-scale control and data path circuits and processors. A number of methods have been developed for the design of hazard-free controllers. These methods have been applied to several large and realistic design examples, including a low-powre infrared communications chip, a second-level cache-controller, a SCSI controller, a differential equation solver and an instruction length decoder. An important aspect of these methods is the development of optimized CAD tools. In synchronous design, CAD packages have been critical to the advancement of modern

14 digital design. In asynchronous design, much progress has been made, including tools for exact hazard-free two-level logic minimization, optimal state assignment and synthesisfor-testability. However, these tools have been limited in handling large-scale designs. In particular, hazard-free 2-level logic minimization is an important step in all the abovementioned CAD tools. However, while the currently used Quine-McCluseky-like exact hazard-free minimization algorithm, HFMIN, has been effective on small and mediumsized examples, it has been unable to produce solutions for several large design problems. This limitation has been a major reason for researchers to invent and apply manual as well as automated techniques for partitioning circuits before hazard-free logic minimization can be performed. This paper introduces two new and very efficient 2-level hazard-free logic minimizers for multi-output minimization: ESPRESSO-HF and IMPYMIN. Both ESPRESSO-HF and IMPYMIN can solve all currently available examples, which range up to 32 inputs and 33 outputs. These include examples that have been previously solved. For examples that can be solved by the currently fastest minimizer HFMIN our two minimizers are typically several orders of magnitude faster. In particular, IMPYMIN can find a minimum-size cover for all benchmark examples in less than 813 seconds, and ESPRESSO-HF can find very good covers at most 3% larger that a minimum-size cover in less than 105 seconds. ESPRESSO_HF and IMPYMIN are somewhat orthogonal. On the one hand ESPRESSO_HF is typically faster than IMPYMIN. On the other hand, IMPYMIN computes a cover of minimum size, wheras ESPRESSO_HF is not guaranteed to find a minimum cover but typically does find a cover of very good quality. Conclusions We have presented two new minimization methods for multi-output 2-level hazard-free logic minimization: Espresso-HF, a heuristic method based on Espresso-II, and Impymin, an exact method based on implicit data structures. Both tools can solve all examples that we have available. These include several large examples that could not be minimized by previous methods. In particular both tools can solve examples that cannot be solved by the currently fastest minimizer Hfmin. On the more difficult examples that can be solved by Hfmin, Espresso-HF and Impymin are typically orders of magnitude faster.

15 Although Espresso-HF is a heuristic minimizer, it almost always obtains an exactly minimum-size cover. Espresso-HF also employs a new fast method to check for the existence of a hazard-free solution, which does not need to generate all prime implicants. Hazard-Free Implementation of the Self-Timed Cell Set in a Xilinx FPGA(1994) Kapilan Maheswaran Venkatesh Akella maheswar@ece.ucdavis.edu akella@ece.ucdavis.edu Computer Engineering Research Laboratory Department of Electrical & Computer Engineering University of California Davis, CA URL: Abstract When designing asynchronous systems, the problems of hazards becomes an important issue. This paper deals with the hazard-free implementation of asynchronous logic in a look-up table based FPGA. First, the definitions of hazards and techniques to deal with them in gate-level asynchronous circuits are surveyed. Then the look-up table (LUT) model and its associated timing properties are presented. Finally, a list of line delay constraints for a hazard-free implementation of the self-timed modules is presented and the conditions under which the cell set is hazard-free is explained. Our technique is illustrated in the implementation of the basic asynchronous macromodules outlined in Sutherland[16], Ebergen[8] and Brunvand[6]) using the Xilinx 4000 Series FPGA. Overview As technology improves, the systems that can be built become larger, faster, and more complex. Speed of synchronous systems is limited by clock skew and the worst case signal path. In an asynchronous system, the various subsystems can operate concurrently and the performance is restricted only by data and control dependencies. Hence, asynchronous systems tend to exhibit average case performance. In addition, asynchronous systems can result in minimizing power dissipation because only components contributing to the current computational task are activated. Thus, asynchronous systems promise to be a viable alternative for the high performance

16 computing systems of the future. However, at the present, there is a lack of commercially viable design methodologies and cell libraries to support this style of design. Field Programmable Gate Arrays (FPGAs) offer rapid prototyping and experimentation of digital circuits with minimum engineering costs. Today, they are limited to only synchronous circuits. FPGAs will be ideal for investigating novel asynchronous architectures provided suitable circuit structures can be built in a hazard-free manner. FPGA-based designs are prone to hazards because of two reasons: (1) They do not ensure predictable routing delays and (2) one cannot restrict the input changes at various circuit inputs. This is not a major issue in the design of synchronous systems but poses to be the main obstacle in the hazard-free implementation of asynchronous logic. In this paper, we propose a scheme to build hazard-free asynchronous circuits in a commercial FPGA such as the Xilinx 4000 series part. First, we review the definitions of various possible hazards in asynchronous circuits and then examine why the existing techniques cannot be used directly to realize hazard-free circuits in a look-up table based FPGA. This brings us to the characterization of the timing behavior of a look-up table. Then we present a set of timing constraints under which a look-up table based implementation of a macro module is hazard-free. Finally, we present the list of delay constraints that have to be satisfied by each asynchronous macro module for a hazard-free realization. Conclusion and Future Work Implementing asynchronous circuits in a given technology demands a careful characterization of the hazard behavior in the technology. This paper examines the issues of mapping asynchronous cell libraries into Xilinx FPGA. A Xilinx FPGA is made up of look-up tables which are different in terms of timing characteristics from simple gates like AND, OR, NAND, etc. Hence, we first provide a survey of existing work on the hazard analysis, which is applicable to simple gate-level implementations. Then we characterize the behavior of a LUT using the Xilinx 4000 family FPGA as an example and present delay constraints that have to be satisfied to achieve a hazard-free implementation of an asynchronous cell library for control circuits. Of course, the proposed scheme is valid only if the circuit elements are used according to their environmental constraints. In addition, the scheme does not eliminate function hazards. Implementation of self-timed data path in a FPGA is being investigated currently.

17 Direct Synthesis of Timed Asynchronous Circuits Sung Tae Jung and Chris J. Myers Electrical Engineering Department University of Utah Salt Lake City, UT URL: d99/pdffiles/06a_4.pdf Abstract This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a deterministic graph specification with timing constraints. A timing analysis extracts the timed concurrency and timed causality relations between any two signal transitions. Then, a hazard-free implementation of the specification is synthesized by analyzing precedence graphs, which are constructed by using the timed concurrency, and timed causality relations. The major result of this work is that the method does not suffer from the state explosion problem, achieves significant reductions in synthesis time, and generates synthesized circuits that have nearly the same area as compared to previous timed circuit methods. In particular, this paper shows that a timed circuit not containing circuit hazards under given timing constraints can be found by using the relations between signal transitions of the specification. Moreover, the relations can be efficiently found using a heuristic timing analysis algorithm. By allowing significantly larger designs to be synthesized, this work is a step towards the development of high-level synthesis tools for system level asynchronous circuits. Overview Speed-independent asynchronous circuits are very robust since they are guaranteed to work independent of the delays associated with their gates, and many synthesis methods for speed-independent circuits have been proposed [1, 2, 3, 4]. However, circuits have been proposed [1, 2, 3, 4]. However, timing constraints are available. Methods have been proposed to use timing constraints to synthesize timed circuits. Such circuits work correctly under the given timing constraints [5, 6] and tend to be more efficient in area and speed than speed-independent circuits [6]. The synthesis techniques in [1, 2, 3, 4, 5, 6] have the state explosion problem because they are based on a state graph. To overcome the state explosion problem, direct methods

18 have been proposed for speed-independent circuits [7, 8, 9, 10]. The method in [7] approximates a set of states as a cube by using a concurrency relation between transitions of the specification. It then finds an initial approximation of the implementation using these cubes. If this approximation does not satisfy correctness criteria, then iterative refinement is performed using state machine decompositions. This method is restricted to state machine decomposable specifications. The method in [8] uses an approach similar to [7] but it allows for a wider class of specifications by finding an initial approximation and refining it using STG-unfolding segments. The method in [9] constructs a characteristic graph for the given signal transition graph and generates a hazard-free implementation by finding a strongly connected sub graph. The method in [10] constructs a precedence graph for each transition of output signals and generates a hazard-free implementation by finding paths in the graph. Whereas a characteristic graph encapsulates all feasible solutions of the original STG, a precedence graph encapsulates all feasible solutions for a single transition of an output signal. Even though several direct methods have been suggested for the synthesis of speedindependent circuits, no method has been suggested for the synthesis of timed circuits. The main goal of this work is to develop a method, which generates timed asynchronous circuits for the specifications that cannot be synthesized by the previous techniques due to the large size of the state space. The solution to this problem is found by the use of timing analysis to obtain the necessary timing information directly from the specification. Timing analysis is used to determine the timed concurrency relation and timed causality relation between any two-signal transitions in a circuit specification. After timing analysis, the algorithm synthesizes efficient timed circuits by constructing a precedence graph and finding all the paths in the graph in a method similar to that in [10]. This paper compares the new method to the previous methods using many benchmark examples and two parameterizable examples: SCSI and FIFO. Whereas previous methods can only synthesize 8 SCSI controllers and 5 FIFO stages, the new method can synthesize 180 SCSI controllers and 100 FIFO stages. By allowing significantly larger designs to be synthesized, this work is a step towards the development of high-level synthesis tools for system level asynchronous circuits. Conclusions This paper presents a direct synthesis method for timed circuits. It shows that a timed circuit not containing circuit hazards under given timing constraints can be found by

19 using the timing relations between signal transitions of the specification. Moreover, these relationships can be efficiently found using a heuristic timing analysis algorithm. The results indicate that by using the direct synthesis approach, we can overcome the state explosion problem. Currently, the synthesis algorithm can handle only deterministic specifications. Future work includes the extension of the algorithm to specifications with free-choice behavior. Also, we plan to extend the target circuit model and synthesis algorithm to apply gate sharing between interval networks. Synthesis of Asynchronous Circuits for Stuck-at and Robust Path Delay Fault Testability(1995) Steven M. Nowick Niraj K. Jha Fu-Chiung Cheng Dept of Computer Science Dept of Electrical Engg. Dept of Computer Science Columbia University Princeton University Columbia University New York, NY Princeton, NJ New York, NY Abstract In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free and completely testable. Making an asynchronous two-level circuit hazard-free usually requires the introduction of either redundant or non-prime cubes, or both. This adversely affects its testability. However, using extra inputs, which is seldom necessary, and a synthesis for testability method, we convert the two-level circuit into a multi-level circuit which is completely testable. To avoid the addition of extra inputs as much as possible, we introduce new exact minimization algorithms for hazard-free twolevel logic where we first minimize the number of redundant cubes and then minimize the number of non-prime cubes. We target the stuck-at and robust paths delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former. Conclusions In this paper, we presented an efficient and complete method for synthesizing hazard-free implementations of asynchronous circuits, which are also completely testable under the stuck-at and robust path delay fault models. Although, theoretically, to make the method complete, we may need to introduce extra control inputs in some rare cases, for none of the practical circuits that we encountered did we need an extra input. The area and delay overheads for obtaining the testable solutions were also shown to be minimal.

20 Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gc Finite State Machines Hans Jacobson Chris Myers Ganesh Gopalakrishnan Dept. of Computer Science Dept. of Electrical Engg. Dept. of Computer Science University of Utah University of Utah University of Utah URL: Abstract This paper presents a new approach to two-level hazard-free logic minimization in the context of extended burst-mode finite state machine synthesis targeting generalized C- elements (gc). No currently available minimizers for literal-exact two-level hazard-free logic minimization of extended burst-mode gc controllers can handle large circuits without synthesis times ranging up over thousands of seconds. Even existing heuristic approaches take too much time when iterative exploration over a large de-sign space is required and do not yield minimum results. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms, an approach that has not been considered for minimization of extended burstmode finite state machines previously. Our algorithm achieves very fast logic minimization by introducing compacted state graphs and cover tables and an efficient single-cube cover algorithm for single-output minimization. Our exact logic minimizer finds minimal number of literal solutions to all currently available benchmarks, in less than one second on a 333 MHz microprocessor more than three orders of magnitude faster than existing literal exact methods, and over an order of magnitude faster than existing heuristic methods for the largest benchmarks. This includes a benchmark that has never been possible to solve exactly in number of literals before. Overview Burst-mode and extended burst-mode asynchronous finite state machine controllers have been successfully used in designing several efficient real-life asynchronous circuits [1, 2, 3, 4, 5]. For such large designs, much iteration through the synthesis process are needed to reach a good circuit implementation. For example, different protocols and state assignments could lead to substantial improvements in circuit area and delay. Since existing exact synthesis methods are slow, and may not even complete for large circuits,

21 designers are often forced to use heuristic methods, or partitioning [6], to interactively explore the design space in a reasonable amount of time often yielding sub-optimal circuits. The bottleneck of extended burst-mode finite state machine synthesis is typically in the hazard-free logic minimization step. This paper will address a new method that allows fast algorithms based on state graph exploration to produce solutions that are hazard-free under the extended burst-mode hazard model. This new method allows very fast logic minimization that is exact in number of literal, even for controllers that previously have been impossible to solve exactly in number of literal due to their large size. Hazard-free logic minimization of two-level sum-of-products burst-mode circuits has been pursued by Nowick et al. Literal exact, cube exact, and heuristic solutions have been explored in the tools HFMIN [7], IMPYMIN [8], and Espresso-HF [8]. While the two later algorithms have managed to reduce logic minimization time, algorithms for higher quality literal-exact solutions still takes thousands of seconds for large controllers, effectively setting a limit on exploration of the design space. Algorithms based on state graph exploration have traditionally been used for synthesis of speed-independent [9, 10] and timed [11] circuits. Some researchers [9, 10] have proposed to use speed-independent methods for logic minimization of burst-mode gc controllers by first translating them into Petri-net specifications. The generated solutions are hazard-free under the constrained gc decomposition rules imposed by the relaxed burst-mode hazard model presented in [12]. However, these methods are not hazard-free for extended burst-mode controllers. Structural logic minimization methods to combat the problem of state explosion in state graph traversal have been explored [13, 14, 15]. These methods perform logic minimization while traversing the input Petri-net specification avoiding generation of potentially large state graphs. These methods, however, experience a substantial increase in Petri-net size for non-monotonic level signals (frequently used in extended burst-mode specifications), and are not hazard-free for extended burst-mode controllers. Recent efforts have been made to produce optimal output solutions over all state reductions and encoding [16], thus avoiding manual design exploration of different state assignments. While these methods are intriguing, the sheer algorithm complexity currently limits the size of controllers that can be automatically explored. In more recent designs, such as Yun s differential equation solver [4] and the burst-mode portions of Intel s RAPPID [17], it has been found that substantial performance

22 improvements can be achieved through the use of generalized C-element (gc) circuit implementations over two-level standard gate implementations. In [18], state minimization and state assignment methods are developed for extended burst-mode controllers based on excitation region covers allowing for gc circuit implementations. These synthesis methods have been implemented in the 3D-tool [19]. 3D leverage the HFMIN tool to perform hazard-free logic minimization and [20] to perform technology mapping. The hazard-free logic minimization method presented in this paper performs the same function as the HFMIN tool in the 3D synthesis flow. Conclusions A very fast algorithm for per-output literal-exact logic minimization of extended burstmode gc finite state machines is presented. The method is based on state graph exploration and the efficient single-cube cover algorithm which is extended to handle the extended burst-mode hazard model and generate per-output minimized covers. Introducing the concept of compacted state graphs and compacted binate cover tables has significantly reduced synthesis time for very large controllers. New extensions to the original single-cube algorithm allowing extremely fast generation of per-output literalexact solutions have also been developed. With the achievement of sub-second exact logic minimization of even the largest burst-mode benchmarks to date on a 333 MHz microprocessor, the method presented in this paper has opened up the possibility of truly interactive and iterative design space exploration of exact solutions for large controllers. Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-Free Implementations) Kenneth Y. Yun, Member, IEEE David L. Dill, Member, IEEE URL: Abstract We introduce a new design style called extended burst-mode. The extended burst-mode design style covers a wide spectrum of sequential circuits ranging from delay-insensitive to synchronous. We can synthesize multiple-input change asynchronous finite state machines, and many circuits that fall in the gray area (hard to classify as synchronous or asynchronous) which are difficult or impossible to synthesize automatically using

23 existing methods. Our implementation of extended burst-mode machines uses standard CMOS logic, generates low-latency outputs, and guarantees freedom from hazards at the gate level. In Part I, we formally define the extended burst-mode specification, provide an overview of the synthesis method, and describe the hazard-free synthesis requirements for two different next-state logic synthesis methods: two-level sums-of-products implementation and generalized C-elements implementation. We also present an extension to existing theories for hazard-free combinational synthesis to handle nonmonotonic input changes. Overview Today s system components typically employ the synchronous paradigm primarily because of the availability of the rich set of design tools and algorithms and, perhaps, because of the designers perception of ease of design and the lack of alternatives. Even so, the interfaces among the system components do not strictly adhere to the synchronous paradigm because of the cost benefit of mixing modules operating at different. There is little doubt that today s heterogeneous system concept at the board level will carry over to tomorrow s systems-on-a-chip, because miniaturization does not make global synchronization any simpler. This paper addresses the problem of how to synthesize asynchronous controllers operating in a heterogeneous environment, i.e., in a system composed of components using different synchronization mechanisms. In this paper, we are mainly concerned with designing correct and efficient asynchronous controllers. There are three factors that affect the quality of the final design and the scope of its applications: specification method, target implementation, and synthesis method. The design style is a general term, which refers to a combination of all of these. Our goal is to develop a design style that attains a good combination of expressiveness and implementability, which are conflicting goals. We will briefly survey existing design styles and zero in on a design style called extended burst-mode, which has a reasonable combination of expressiveness and implementability. Conclusions We formally defined the extended burst-mode specification, presented an overview of the 3D synthesis, and discussed hazard elimination strategies. Because the most difficult problem in asynchronous circuit synthesis is avoiding hazards, we reviewed precise

24 characterization of various kinds of hazards and described how each is avoided in the 3D machine implementation. We showed that the 3D machine synthesis problem reduces down to one of synthesizing hazard-free next-state logic and presented two approaches for next-state logic synthesis: two level AND-OR implementation and generalized C- element implementation. We also presented an extension to existing theories for hazardfree combinational synthesis to handle non- monotonic inputs. We showed that these methods require different constraints to guarantee that implementations are hazard- free. In Part II of the paper, we will show how the selection of the next-state logic synthesis method affects the state assignment. We will present an extensive set of experimental results and compare our results to competing methods whenever possible. The following are the URLs where a lot of publications on logic circuits can be found /htmfiles/sun_sgi/frames/iccadai.htm

25 "I alone prepared and wrote this project. I received no help from anyone one else. This material is not copied or paraphrased from any other source except where specifically indicated. I grant my permission for this project to be placed on the course homepage during future semesters. I understand that I could receive an F for the course retroactively, even after graduation, if this work is later found to be plagiarized." Rabia Essani