Advanced Digital Logic Design EECS 303

Transcription

1 Advanced igital Logic esign EECS 33 Teacher: Robert ick Office: L477 Tech Phone:

2 Outline Robert ick Advanced igital Logic esign

3 Introduction to testing After fabrication, some circuits don t work correctly etermining which circuits contain faults requires testing Testing some types of circuits is easy, testing others is difficult One can use automation to help solve this problem 3 Robert ick Advanced igital Logic esign

4 Introduction to testing etermining the best way to test large circuits requires automation Building large circuits that are easy to test also requires automation Testing it spans all design, from system to physical level Today, I ll introduce some classical ideas at the logic level 4 Robert ick Advanced igital Logic esign

5 Section outline. 5 Robert ick Advanced igital Logic esign

6 , y, is the fraction of fault-free products Test fault coverage, c, is the fraction of faults that the set of applied tests detects Low-yield is expensive because fabrication capacity is wasted efect level, d, is the fraction of parts containing undetected faults d = y c A high defect level is extremely expensive because it means circuits make their way into products, or worse, to consumers, before faults are discovered 6 Robert ick Advanced igital Logic esign

7 efect level Example acceptable defect level:.2 Either yield must be very high or fault coverage must be very high d c (%) y Robert ick Advanced igital Logic esign

8 Section outline. 8 Robert ick Advanced igital Logic esign

9 Faults and failures A fault is a physical defect in a circuit A failure is the deviation of a circuit from its specified behavior Faults can cause failures but they don t always cause failures 9 Robert ick Advanced igital Logic esign

10 Functional testing No assumptions about types of fault No assumptions about structure or properties of Circuit Under Test (CUT) The CUT is a black box that is checked to determine whether it responds to all (or most) input (sequences) as specified However, ignoring structural information makes testing unnecessarily slow Robert ick Advanced igital Logic esign

11 Structural testing Use information about the specific CUT Types of faults that are likely to occur Structure of circuit Robert ick Advanced igital Logic esign

12 V V a b z a b z V SS 2 Robert ick Advanced igital Logic esign

13 V V a b z a b z V SS bridging fault 2 Robert ick Advanced igital Logic esign

14 V V a b z a b z V SS 2 Robert ick Advanced igital Logic esign

15 V V stuck open fault a b z a b z V SS 2 Robert ick Advanced igital Logic esign

16 V V a b z a b z V SS 2 Robert ick Advanced igital Logic esign

17 V V stuck at fault a b z a b z V SS 2 Robert ick Advanced igital Logic esign

18 V V a b z a b z V SS 2 Robert ick Advanced igital Logic esign

19 Singe stuck-at faults One of the simplest and most common fault models S-a-: Stuck-at S-a-: Stuck-at Relies on digital reinforcement.8 V is V one logic stage later S-a-.8 s-a- For two-level logic, exhaustive test set for single stuck-at faults will detect all multiple stuck-at faults, too oesn t hold for multi-level logic 3 Robert ick Advanced igital Logic esign

20 Single stuck-at faults Consider a NAN3 gate z Inputs fault a b c z A B C free 4 Robert ick Advanced igital Logic esign

21 Single stuck-at faults Consider a NAN3 gate z Inputs fault a b c z A B C free Too expensive to use 2 n inputs (2 3 = 8 in this case) 4 Robert ick Advanced igital Logic esign

22 Single stuck-at faults Consider a NAN3 gate z Inputs fault a b c z A B C free Unate covering again 4 Robert ick Advanced igital Logic esign

23 Fault coverage A test of all possible inputs for a NANn gate will require 2 n tests Applying all possible tests (or sequences of tests) for complex circuits isn t practical However, for all NANn gates, all single stuck-at faults (and implicitly multiple stuck-at faults) can be tested using only n + tests 5 Robert ick Advanced igital Logic esign

24 Fault equivalence The function of the circuit is identical in the presence of either fault E.g., any input of a NAN gate being s-a- or the output being s-a- output of In general, identifying equivalent faults, or fault collapsing is difficult However, can use knowledge about gates, and connectivities, to find most equivalent faults 6 Robert ick Advanced igital Logic esign

25 Fault equivalence Consider a NAN3 gate z Inputs fault a b c z A B C free 7 Robert ick Advanced igital Logic esign

26 Fault equivalence Consider a NAN3 gate z Inputs fault a b c z A B C free Equivalent faults 7 Robert ick Advanced igital Logic esign

27 Other fault models 2 /3 CMOS faults are not stuck-at faults Luckily, stuck-at fault tests often detect them More advanced faults models Allow higher theoretical coverage Are more complicated In this lecture, we only have time to cover stuck-at-faults 8 Robert ick Advanced igital Logic esign

28 Section outline. 9 Robert ick Advanced igital Logic esign

29 Test generation Can use algorithms to automatically generate a test for a specific fault Problem: Identify some test, t, such that the output of the circuit will deviate from its specified value if a particular fault, f, is present Excitation: Need to propagate a value to stuck-at fault that is contrary to the fault value Sensitization: Need to propagate the faulty value to an output of the circuit 2 Robert ick Advanced igital Logic esign

30 Excitation and sensitization s a 2 Robert ick Advanced igital Logic esign

31 Excitation and sensitization s a excitation 2 Robert ick Advanced igital Logic esign

32 Excitation and sensitization s a sensitization 2 Robert ick Advanced igital Logic esign

33 Excitation and sensitization s a sensitization 2 Robert ick Advanced igital Logic esign

34 Excitation and sensitization s a sensitization 2 Robert ick Advanced igital Logic esign

35 Backtracking s a not sensitized 22 Robert ick Advanced igital Logic esign

36 Backtracking s a 22 Robert ick Advanced igital Logic esign

37 Backtracking s a sensitized 22 Robert ick Advanced igital Logic esign

38 Backtracking s a sensitized 22 Robert ick Advanced igital Logic esign

39 Automatic Test Pattern Generation (ATPG) Can automatically determine test for a particular fault Boolean difference Generally considered too slow for use on large circuits Easy to understand Excitation/sensitization based methods (-algorithm) 23 Robert ick Advanced igital Logic esign

40 Boolean difference i i 2 i 3 z 24 Robert ick Advanced igital Logic esign

41 Boolean difference i i 2 s a i 3 z In the presence of the fault, function is i 3 24 Robert ick Advanced igital Logic esign

42 Boolean difference i i 2 i 3 δ XOR faulty and specified functions 24 Robert ick Advanced igital Logic esign

43 Boolean difference If the resulting function is, the fault can not be identified If the resulting function is, the fault can be identified Use a test that satisfies (sets to ) the function 25 Robert ick Advanced igital Logic esign

44 Boolean difference 26 Robert ick Advanced igital Logic esign

45 Boolean difference 26 Robert ick Advanced igital Logic esign

46 Boolean difference 26 Robert ick Advanced igital Logic esign

47 Boolean difference 26 Robert ick Advanced igital Logic esign

48 -algorithm We have seen that, in order to test for a particular fault, we must Excite the fault Sensitize a path from the fault to the output The -algorithm is an automated method of finding a test that excites a fault and sensitizes a path to the circuit output J.P. Roth, IBM, Robert ick Advanced igital Logic esign

49 Roth s extension to Boolean algebra α/β / = / = / = / = α is the fault-free value β is the value in the presence of the fault X /X = X 28 Robert ick Advanced igital Logic esign

50 (N)AN -cubes of failure detection -cube of failure gate input z a b a b z AN s-a- X s-a- X X s-a- X NAN s-a- X s-a- X X s-a- X 29 Robert ick Advanced igital Logic esign

51 (N)OR -cubes of failure detection -cube of failure gate input z a b a b z OR s-a- X s-a- X X s-a- X NOR s-a- X s-a- X X s-a- X 3 Robert ick Advanced igital Logic esign

52 (N)AN -cubes of propagation input AN NAN a b z z 3 Robert ick Advanced igital Logic esign

53 (N)OR -cubes of propagation input OR NOR a b z z 32 Robert ick Advanced igital Logic esign

54 -algorithm Initially, all the lines in the circuit are X (on t Care) Left blank in example 2 A gate with an input of or and an output of X belongs to the frontier 3 An element whose assigned inputs do not imply the output is unjustified 4 We want to drive the frontier to a circuit output (sensitize) and justify the gate inputs (excite) 33 Robert ick Advanced igital Logic esign

55 -algorithm overview choose -cube of failure to excite fault sensitize path to output justify gates conflicts? no done yes Backtrack 34 Robert ick Advanced igital Logic esign

56 -algorithm Select a -cube of failure to excite the fault while frontier has not yet reached an output do Perform the implications of the most recent assignment if the frontier is empty then Backtrack end if Choose a signal, s, s.t. s can t reached from the fault Assign s to a value in order to propagate the fault forward end while for each unjustified line, l do if l can be justified then Justify l else Backtrack end if end for A test has been found

57 -algorithm notes There are a few details not explained in the pseudocode Signals should be selected in order to drive the frontier forward Backtracking is the action of backing up and taking the closest previously unexplored branch in the decision tree 36 Robert ick Advanced igital Logic esign

58 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

59 -algorithm example i i 2 i 3 z i 4 i 5 s a 37 Robert ick Advanced igital Logic esign

60 -algorithm example i i 2 i 3 z i 4 i 5 / = 37 Robert ick Advanced igital Logic esign

61 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

62 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

63 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

64 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

65 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

66 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

67 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

68 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

69 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

70 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

71 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

72 -algorithm example i i 2 i 3 Conflict! z i 4 i 5 37 Robert ick Advanced igital Logic esign

73 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

74 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

75 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

76 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

77 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

78 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

79 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

80 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

81 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

82 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

83 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

84 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

85 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

86 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

87 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

88 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

89 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

90 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

91 -algorithm example i i 2 i 3 z i 4 i 5 37 Robert ick Advanced igital Logic esign

92 NOR -cubes of failure detection -cube of failure gate input z a b a b z NOR s-a- s-a- s-a- s-a- 38 Robert ick Advanced igital Logic esign

93 NOR -cubes of failure detection -cube of failure gate input z a b a b z NOR s-a- s-a- s-a- s-a- 38 Robert ick Advanced igital Logic esign

94 AN -cubes of propagation input AN a b z 39 Robert ick Advanced igital Logic esign

95 AN -cubes of propagation input AN a b z 39 Robert ick Advanced igital Logic esign

96 NOR -cubes of propagation input NOR a b z 4 Robert ick Advanced igital Logic esign

97 NOR -cubes of propagation input NOR a b z 4 Robert ick Advanced igital Logic esign

98 NOR -cubes of failure detection -cube of failure gate input z a b a b z NOR s-a- s-a- s-a- s-a- 4 Robert ick Advanced igital Logic esign

99 NOR -cubes of failure detection -cube of failure gate input z a b a b z NOR s-a- s-a- s-a- s-a- 4 Robert ick Advanced igital Logic esign

100 -algorithm summary If a test for a fault exists, guaranteed to generate it Full backtracking However, much faster than Boolean difference 42 Robert ick Advanced igital Logic esign

101 Caveats This lecture has only introduced some topics in testing If you intend to do research in this area, take a few courses on testing Single stuck-at fault model is becoming obsolete 43 Robert ick Advanced igital Logic esign

102 Caveats -algorithm is actually more complicated Avoiding backtracking is important for performance Implications Heuristics to make best decisions first Should understand derivation of -cubes for arbitrary fault models 44 Robert ick Advanced igital Logic esign

103 -algorithm reference Stanley Hurst. VLSI Testing: igital and Mixed Analogue/igital Techniques. Institution of Electrical Engineers, U.K., 998 This is one of the better references in the library Beware: The -algorithm examples contain small errors 45 Robert ick Advanced igital Logic esign

104 CA survey reference Melvin A. Breuer, Majid Sarrafzadeh, and Fabio Somenzi. Fundamental CA algorithms. IEEE Trans. Computer-Aided esign of Integrated Circuits and Systems, 8(2): , ecember 2 Recommended by a student Introduces a number of important logic-level and physical-level CA algorithms A useful supplement to the material in Hachtel and Somenzi s, and Sherwani s books Introduces the -algorithm 46 Robert ick Advanced igital Logic esign

105 Outline -algorithm review Redundancy elimination esign/synthesis for testability Robert ick Advanced igital Logic esign

106 Section outline -algorithm review Redundancy elimination esign/synthesis for testability 2. -algorithm review Redundancy elimination esign/synthesis for testability 48 Robert ick Advanced igital Logic esign

107 -algorithm review -algorithm review Redundancy elimination esign/synthesis for testability Given a fault, the -algorithm will generate a test for that fault Selects a -cube of failure to excite the fault Propagates a value to the circuit outputs be selection -cubes of propagation for gates Justifies gate inputs Uses full backtracking on -cubes of failure and gate justification 49 Robert ick Advanced igital Logic esign

108 Fault simulator -algorithm review Redundancy elimination esign/synthesis for testability Fault simulation is the process of determining which faults a test detects Test generation is complicated and time-consuming Fault simulation is quick 5 Robert ick Advanced igital Logic esign

109 Test sequence generation -algorithm review Redundancy elimination esign/synthesis for testability The -algorithm gives us a way to generate a test for a given fault However, we need a sequence of tests for all (or most) faults etermine all stuck-at faults for the circuit Eliminate equivalent faults while untested faults remain do Pick a fault and use an ATPG to generate a test Append the test to a list Use a fault simulator to determine all faults the test detects Eliminate detected faults end while 5 Robert ick Advanced igital Logic esign

110 Test sequence generation -algorithm review Redundancy elimination esign/synthesis for testability However, this approach can still be too expensive Recall Fault simulation is fast ATPG is slow Take advantage of fault simulator 52 Robert ick Advanced igital Logic esign

111 Test sequence generation -algorithm review Redundancy elimination esign/synthesis for testability while fault coverage is less than 9% do Generate a random pattern extremely fast Use a fault simulator to determine if new faults are detected if so then Append pattern to a list Eliminate detected faults end if end while while fault coverage is less than 99.5% do Pick a fault and use an ATPG to generate a test Append the test to a list Use a fault simulator to determine all faults the test detects Eliminate detected faults end while 53 Robert ick Advanced igital Logic esign

112 Section outline -algorithm review Redundancy elimination esign/synthesis for testability 2. -algorithm review Redundancy elimination esign/synthesis for testability 54 Robert ick Advanced igital Logic esign

113 Redundancies -algorithm review Redundancy elimination esign/synthesis for testability Sometimes a s-at- fault can t be detected Implication: Given any set of inputs to the circuit, that node can be set to and the output will match the specifications Converse for s-a- faults Even if a portion of the circuit is not able the switch, the same function is realized The presence of an undetectable fault implies redundancy 55 Robert ick Advanced igital Logic esign

114 Redundancies -algorithm review Redundancy elimination esign/synthesis for testability Sometimes a s-at- fault can t be detected Implication: Given any set of inputs to the circuit, that node can be set to and the output will match the specifications Converse for s-a- faults Even if a portion of the circuit is not able the switch, the same function is realized The presence of an undetectable fault implies redundancy How can the -algorithm can be used to simplify logic? 55 Robert ick Advanced igital Logic esign

115 Redundancies -algorithm review Redundancy elimination esign/synthesis for testability Logic terminating in the location of the stuck-at fault can be removed from the circuit and the same function will be realized Conventional wisdom suggests removal Simplify logic Make circuit more fully testable 56 Robert ick Advanced igital Logic esign

116 Redundancy example -algorithm review Redundancy elimination esign/synthesis for testability a b z 57 Robert ick Advanced igital Logic esign

117 Redundancy example -algorithm review Redundancy elimination esign/synthesis for testability a b s-a- z 57 Robert ick Advanced igital Logic esign

118 Redundancy example -algorithm review Redundancy elimination esign/synthesis for testability a b s-a- z Excite: a b 57 Robert ick Advanced igital Logic esign

119 Redundancy example -algorithm review Redundancy elimination esign/synthesis for testability a b s-a- z Excite: a b Sensitize: a = b = 57 Robert ick Advanced igital Logic esign

120 Redundancy example -algorithm review Redundancy elimination esign/synthesis for testability a b s-a- z Excite: a b Sensitize: a = b = Can t excite and propegate faulty value to z! 57 Robert ick Advanced igital Logic esign

121 Redundancy example -algorithm review Redundancy elimination esign/synthesis for testability a b s-a- z Excite: a b Sensitize: a = b = Can t excite and propegate faulty value to z! Replace s-a- logic with 57 Robert ick Advanced igital Logic esign

122 Redundancy example -algorithm review Redundancy elimination esign/synthesis for testability a b s-a- z Excite: a b Sensitize: a = b = Can t excite and propegate faulty value to z! Replace s-a- logic with Eliminate unused logic 57 Robert ick Advanced igital Logic esign

123 Redundancy example -algorithm review Redundancy elimination esign/synthesis for testability a b z Excite: a b Sensitize: a = b = Can t excite and propegate faulty value to z! Replace s-a- logic with Eliminate unused logic Simplify logic 57 Robert ick Advanced igital Logic esign

124 ATPG for logic simplification -algorithm review Redundancy elimination esign/synthesis for testability Can use ATPG algorithm to simplify logic Find a fault that is untestable due to redundancy 2 Remove the redundant logic 3 Repeat 58 Robert ick Advanced igital Logic esign

125 Redundancy removal not always safe -algorithm review Redundancy elimination esign/synthesis for testability Logical equivalence may not imply true equivalence What happens if redundancy is intentional? To reduce power consumption To ensure signal stability for use in asynchronous circuits Removal can Increase power Introduce races 59 Robert ick Advanced igital Logic esign

126 Section outline -algorithm review Redundancy elimination esign/synthesis for testability 2. -algorithm review Redundancy elimination esign/synthesis for testability 6 Robert ick Advanced igital Logic esign

127 -algorithm review Redundancy elimination esign/synthesis for testability Can convert to a version of combinational testing Iterative array expansion Simulation-based 6 Robert ick Advanced igital Logic esign

128 Iterative array expansion -algorithm review Redundancy elimination esign/synthesis for testability Make a copy of the combinational logic for each time step However, now the problem converts ATPG for multiple faults Iterative array expansion increases the size of the combinational problem More importantly, changes the required fault model Requires ATPG for multiple faults 62 Robert ick Advanced igital Logic esign

129 Iterative array expansion -algorithm review Redundancy elimination esign/synthesis for testability i i 2 i 3 z i 4 Q c C Q 63 Robert ick Advanced igital Logic esign

130 Iterative array expansion -algorithm review Redundancy elimination esign/synthesis for testability i i 2 i 3 z i 4 s a Q c C Q 63 Robert ick Advanced igital Logic esign

131 Iterative array expansion -algorithm review Redundancy elimination esign/synthesis for testability i i 2 i 3 z i i 2 i 3 z i 4 i 4 s a Q c C Q 63 Robert ick Advanced igital Logic esign

132 Iterative array expansion -algorithm review Redundancy elimination esign/synthesis for testability i i 2 i 3 z i i 2 i 3 z i 4 i 4 c C Q Q i i 2 i 3 i 4 s a z s a 63 Robert ick Advanced igital Logic esign

133 Iterative array expansion -algorithm review Redundancy elimination esign/synthesis for testability i i 2 i 3 z i i 2 i 3 z i 4 i 4 c C Q Q i i 2 i 3 i 4 s a z s a 63 Robert ick Advanced igital Logic esign

134 -algorithm review Redundancy elimination esign/synthesis for testability Modified -algorithm for iterative array Propagate -frontier forward Generate new time frames as necessary Propagate gate justification backward Generate new time frames as necessary However, this algorithm is not certain to find a test if one exists Roth s algebra not suited to sequential circuits 64 Robert ick Advanced igital Logic esign

135 Muth s 9-valued logic -algorithm review Redundancy elimination esign/synthesis for testability -algorithm can t adequately model the possible states in sequential circuits Repeated effect of fault can t be modeled Roth s values /, / ( ), / (), /, X/X Muth s values /, /, /X, /, /, /X, X/, X/, X/X 65 Robert ick Advanced igital Logic esign

136 Simulation-based sequential testing -algorithm review Redundancy elimination esign/synthesis for testability Generate a vector etermine whether that vector brought the circuit state nearer to or farther from fault excitation and sensitization If the state moved near to detection, append the pattern to a list Many of the probabilistic optimization algorithms in the third lecture can be applied for simulation-based testing 66 Robert ick Advanced igital Logic esign

137 Simulation-based sequential testing -algorithm review Redundancy elimination esign/synthesis for testability a b c 67 Robert ick Advanced igital Logic esign

138 Simulation-based sequential testing -algorithm review Redundancy elimination esign/synthesis for testability a b c s a 67 Robert ick Advanced igital Logic esign

139 Simulation-based sequential testing -algorithm review Redundancy elimination esign/synthesis for testability a b c s a What if a, b, and c are state variables? 67 Robert ick Advanced igital Logic esign

140 Simulation-based sequential testing -algorithm review Redundancy elimination esign/synthesis for testability a b c s a What if a, b, and c are state variables? 67 Robert ick Advanced igital Logic esign

141 Simulation-based sequential testing -algorithm review Redundancy elimination esign/synthesis for testability a b c? s a What if a, b, and c are state variables? 67 Robert ick Advanced igital Logic esign

142 Simulation-based sequential testing -algorithm review Redundancy elimination esign/synthesis for testability a b c s a What if a, b, and c are state variables? 67 Robert ick Advanced igital Logic esign

143 Sequential test generation problems -algorithm review Redundancy elimination esign/synthesis for testability Sequential test generation intractable for large circuits Some continue to work on improving test generation Others modify circuit structure to make test generation easier Robert ick Advanced igital Logic esign

144 Section outline -algorithm review Redundancy elimination esign/synthesis for testability 2. -algorithm review Redundancy elimination esign/synthesis for testability 69 Robert ick Advanced igital Logic esign

145 Scan-based design for test (FT) -algorithm review Redundancy elimination esign/synthesis for testability If testability is considered during design or synthesis, can be made easy Instead of forcing ATPG to deal with synchronous testing, insert a scan chain Chain together (all) flip-flops and scan through an input if and only if a testing input is activated 7 Robert ick Advanced igital Logic esign

146 Scan flip-flop -algorithm review Redundancy elimination esign/synthesis for testability Q Q C 7 Robert ick Advanced igital Logic esign

147 Scan flip-flop -algorithm review Redundancy elimination esign/synthesis for testability T S 7 Robert ick Advanced igital Logic esign

148 Scan flip-flop -algorithm review Redundancy elimination esign/synthesis for testability T S C Q Q 7 Robert ick Advanced igital Logic esign

149 Scan flip-flop -algorithm review Redundancy elimination esign/synthesis for testability T from previous flip flop C Q to next flip flop 7 Robert ick Advanced igital Logic esign

150 Scan flip-flop -algorithm review Redundancy elimination esign/synthesis for testability T testing logic overhead from previous flip flop C Q to next flip flop 7 Robert ick Advanced igital Logic esign

151 Scan flip-flop -algorithm review Redundancy elimination esign/synthesis for testability T testing logic overhead from previous flip flop testing routing overhead C Q to next flip flop testing routing overhead 7 Robert ick Advanced igital Logic esign

152 Full scan -algorithm review Redundancy elimination esign/synthesis for testability Greatly simplifies testing Converts sequential testing to combinational testing Testing can be slow if I/O pins limited Significantly increases chip area and price More complicated flip-flops More complicated routing I/O requirements, especially if speed required 72 Robert ick Advanced igital Logic esign

153 Scan chain -algorithm review Redundancy elimination esign/synthesis for testability combinational logic serial scan input test mode clock S T C Q S T C Q S T C Q S T C Q serial scan output 73 Robert ick Advanced igital Logic esign

154 Level-sensitive scan design (LSS) -algorithm review Redundancy elimination esign/synthesis for testability Less delay than scan-path during normal operation Used commercially, especially within IBM Pre-processing step replaces all latches with LSS latches Other companies have related testing approaches Scan path NEC Scan/set Sperry Univac Random access scan Fujitsu 74 Robert ick Advanced igital Logic esign

155 LSS -algorithm review Redundancy elimination esign/synthesis for testability L L L 2 L 2 C normal C test T C test2 75 Robert ick Advanced igital Logic esign

156 LSS -algorithm review Redundancy elimination esign/synthesis for testability level sensitive flip-flop L L L 2 L 2 C normal C test T C test2 75 Robert ick Advanced igital Logic esign

157 LSS -algorithm review Redundancy elimination esign/synthesis for testability level sensitive flip-flop L L L 2 L 2 C normal C test T C test2 level sensitive flip-flop 75 Robert ick Advanced igital Logic esign

158 LSS -algorithm review Redundancy elimination esign/synthesis for testability level sensitive flip-flop L L L 2 L 2 C normal C test T mode control C test2 level sensitive flip-flop 75 Robert ick Advanced igital Logic esign

159 LSS -algorithm review Redundancy elimination esign/synthesis for testability level sensitive flip-flop L L L 2 C normal C test mode control C test2 level sensitive flip-flop 75 Robert ick Advanced igital Logic esign

160 Full scan disadvantages -algorithm review Redundancy elimination esign/synthesis for testability Increased area 5% 5% Increased delay epends on critical path average combinational logic depth Slow when implemented serially Need to serially clock through every register in IC High pin requirements to speed up 76 Robert ick Advanced igital Logic esign

161 Partial scan -algorithm review Redundancy elimination esign/synthesis for testability Instead of scanning all latches, scan a subset Need to carefully select scanned latches based on Test coverage effects Testing speed 77 Robert ick Advanced igital Logic esign

162 Advanced FT/SFT techniques -algorithm review Redundancy elimination esign/synthesis for testability Testing core-based systems-on-chip (SoC) Related to board-level boundary-scan Fault injection Reliability evaluation Insert fault into system and determine reaction RTL synthesis for testability Software fault modeling and testing Extremely difficult problem 78 Robert ick Advanced igital Logic esign

163 Personal observations on testing -algorithm review Redundancy elimination esign/synthesis for testability espite continued research on advanced testing techniques, industry continues to use full-scan In order for industry to accept a more complicated testing technique, the advantages must be tremendous Companies don t like complexity Testing is a fairly mature field Some people in academia have shifted their interest away from testing It remains a huge practical problem for industry 79 Robert ick Advanced igital Logic esign

164 Personal observations on testing -algorithm review Redundancy elimination esign/synthesis for testability Companies don t want increased complexity Researchers want to see their ideas used Therefore, reduction in interest in testing among researchers Therefore, reduction in interest in testing among companies However, companies still have huge testing problems Therefore, high demand for MS and Ph.. graduates with testing experience One option: target a research problems involving testing and another area, e.g., synthesis 8 Robert ick Advanced igital Logic esign

165 Testing summary -algorithm review Redundancy elimination esign/synthesis for testability Low defect rate requires high test coverage Functional testing requires too many patterns Use structural testing based on a fault model, e.g., single stuck-at Can use fault equivalence to reduce patterns Can automatically generate a test for a specific fault Combine ATPG with fault simulator to generate a set of tests with high coverage 8 Robert ick Advanced igital Logic esign

166 Testing summary -algorithm review Redundancy elimination esign/synthesis for testability Can use ATPG for logic simplification redundancy difficult for large circuits Use FT to make testing easier Use design automation to make FT easier 82 Robert ick Advanced igital Logic esign

167 references -algorithm review Redundancy elimination esign/synthesis for testability Sujit ey, Anand Raghunathan, and Rabindra K. Roy. Considering testability during high-level design. In Proc. Asia & South Pacific esign Automation Conf., February 998 Survey on high-level design/synthesis for test techniques Kwang-Ting Cheng. Gate-level test generation for sequential circuits. ACM Trans. esign Automation Electronic Systems, (4):45 442, October 996 Survey on sequential test generation 83 Robert ick Advanced igital Logic esign