Switching Hardware. Spring 2018 CS 438 Staff, University of Illinois 1

Transcription

1 Switchig Hardware Sprig 208 CS 438 Staff, Uiversity of Illiois

2 Where are we? Uderstad Differet ways to move through a etwork (forwardig) Read sigs at each switch (datagram) Follow a kow path (virtual circuit) Carry istructios (source routig) Bridge approach to extedig LAN cocept Next: how switches are built ad cotetio withi switches Sprig 208 CS 438 Staff, Uiversity of Illiois 2

3 Switch Desig Chicago Bloomigto Champaig St. Louis Sprigfield Effigham Idiaapolis How should we desig Champaig to accommodate traffic flows? Sprig 208 CS 438 Staff, Uiversity of Illiois 3

4 Switch architecture Juiper EX2200 Juiper EX8200 Sprig 208 CS 438 Staff, Uiversity of Illiois Cisco Catalyst

5 Switch Desig Iput Port Iput Port Iput Port Iput Port Switch Fabric Iput Port Iput Port Sprig 208 CS 438 Staff, Uiversity of Illiois 5

6 Switch Architecture Problem Iput Port Coect N iputs to M outputs Iput Port Iput Port Iput Port Switch Fabric NxM ( N by M ) switch Iput Port Commo case: N = M Iput Port Goals Avoid cotetio High throughput Good scalability Near-liear size/cost growth Sprig 208 CS 438 Staff, Uiversity of Illiois 6

7 Switch high level architecture Ports hadle complexity Iput Port Forwardig decisios at iput ports Iput Port Iput Port Iput Port Switch Fabric Bufferig at output ad possibly iput ports Iput Port Iput Port Simple fabric (it seems ) Move packets from iputs to outputs May have a small amout of iteral bufferig Sprig 208 CS 438 Staff, Uiversity of Illiois 7

8 Switch Desig Goals Miimize Cotetio Avoid cotetio through itelliget bufferig Use output bufferig whe possible Apply back pressure through switch fabric Improve iput bufferig through o-fifo buffers Reduces head-of-lie blockig Drop packets if iput buffers overflow Sprig 208 CS 438 Staff, Uiversity of Illiois 8

9 Switch Desig Goals Maximize Throughput Mai problem is cotetio Need a good traffic model Arrival time Destiatio port Packet legth Telephoy modelig is well uderstood Util faxes ad modems Data traffic has differet properties E.g., phoe call arrivals are Poisso, but packet arrivals are heavy-tailed Sprig 208 CS 438 Staff, Uiversity of Illiois 9

10 Cotetio Problem Some packets may be destied for the same output port Solutios Oe packet gets set first Other packets get delayed or dropped Delayig packets requires bufferig Buffers are fiite, so we may still have to drop Bufferig at iput ports Icreases, adds false cotetio Sometimes ecessary Bufferig at output ports Bufferig iside switch Sprig 208 CS 438 Staff, Uiversity of Illiois 0

11 Bufferig stadard checkout lies customer service Waitig to buy food We eed bufferig, places where people ca wait before they get service Waitig for Cust. service Sprig 208 CS 438 Staff, Uiversity of Illiois

12 Bufferig stadard checkout lies customer service Waitig to buy food Waitig for Cust. service How big should buffers be? à Should make sure we ca hold eough à But do t wat people to wait forever Sprig 208 CS 438 Staff, Uiversity of Illiois 2

13 Switch Desig Iput Port Output Queues Iput Port 2 2 Iput Port 3 3 Iput Port 4 4 Iput Port 5 Iput Port 6 5 Add output queues to hold packets Packet remais queued here util 6 output port available to sed Sprig 208 CS 438 Staff, Uiversity of Illiois 3

14 Iput Port Bufferig stadard checkout lies customer service Waitig to buy food People waitig to get ito the store We also eed bufferig at the iput, sice processig ca be slower tha iput rate, or delays at output Waitig for Cust. service Sprig 208 CS 438 Staff, Uiversity of Illiois 4

15 Switch Desig Iput Port Iput Queues Output Queues Iput Port 2 2 Iput Port 3 3 Iput Port 4 Add iput queues to temporarily hold received packets util they ca be processed Packet Iput remais Port 5 queued util iput queue empties, util output queue has free slots Iput Port Sprig 208 CS 438 Staff, Uiversity of Illiois 5

16 Switch desig: puttig the pieces together Iput Port Iput Queues Itercoectio Network Output Queues Iput Port 2 2 Iput Port 3 3 Iput Port 4 4 Iput Port 5 5 Iput Port 6 6 Sprig 208 CS 438 Staff, Uiversity of Illiois 6

17 Switch desig: puttig the pieces together Iput Port Looks i forwardig table, fids output port 3 is associated Itercoectio with Iput destiatio Network Output Queues Queues Iput Port 2 2 Iput Port 3 3 Iput Port 4 4 Packet remais queued util Iput iput Port queue 5 empties ad output queue 3 has free slots Iput Port 6 5 Packet remais queued util output port available to sed 6 Sprig 208 CS 438 Staff, Uiversity of Illiois 7

18 Cotetio Head of Lie Blockig stadard checkout lies customer service cashiers are stadig by! waitig for free slots i cust. svc lie People waitig to get ito the store Head of lie blockig slows throughput Sprig 208 CS 438 Staff, Uiversity of Illiois 8

19 Head of Lie Blockig Iput Port Two packets with same output port à cotetio Itercoectio Iput etwork: Queues switch fabric Output Queues Iput Port 2 2 Iput Port 3 3 Iput Port 4 4 Iput Port 5 5 Iput Port 6 We ca t sed this packet, eve though it s ot cotedig for resources! 6 Sprig 208 CS 438 Staff, Uiversity of Illiois 9

20 Ublockig head of lie blockig Solutio : No iput queue Switchig fabric (hopefully) keeps up with iput rate Solutio 2: No eed to always serve packet at head of queue. Could pick ay! Each iput port has separate queue for each output port Next questio: which packet do we pick? Sprig 208 CS 438 Staff, Uiversity of Illiois 20

21 Pickig packets ports Iput port 2 3 Output port Iput port 2 Iput port Switchig fabric Output port 2 Output port 3 Iput port Output port 4 Sprig 208 CS 438 Staff, Uiversity of Illiois 2

22 Pickig packets ports Iput port 2 3 Output port Iput port 2 Iput port Switchig fabric Output port 2 Output port 3 Iput port Output port 4 Uderlyig problem for max throughput i sigle timestep: bipartite matchig Pick max subset of edges usig edge per ode Sprig 208 CS 438 Staff, Uiversity of Illiois 22

23 Pickig packets ports Iput port 2 3 Output port Iput port 2 Iput port Switchig fabric Output port 2 Output port 3 Iput port Output port 4 Switches may ot fid optimal solutio: we also wat Fairess Simplicity of implemetatio Sprig 208 CS 438 Staff, Uiversity of Illiois 23

24 What we kow so far Bufferig masks temporary cotetio Need to carefully maage queues Head-of-lie blockig problem Fairess Throughput Sprig 208 CS 438 Staff, Uiversity of Illiois 24

25 What we kow so far Did we completely solve cotetio problem? Could a packet ever be dropped? Yes: queues ca still overflow Solutio : pla allowed packet rates i advace virtual circuit switchig Solutio 2: dyamically request rate reductio backpressure Sprig 208 CS 438 Staff, Uiversity of Illiois 25

26 Cotetio Back Pressure Let the receiver tell the seder to slow dow Propagatio delay requires that the receiver react before the buffer is full Typically used i etworks with small propagatio delay switch switch 2 o more, please Sprig 208 CS 438 Staff, Uiversity of Illiois 26

27 Cotetio Back Pressure Need to sed backpressure before queue fills So, better whe propagatio delay small e.g., switch fabrics e.g., Etheret pause-based flow cotrol (IEEE 802.3x) used to ru FibreChael over Etheret Switch stop stop stop Switch Discard: 78 9 Sprig 208 CS 438 Staff, Uiversity of Illiois 27

28 Switch Desig Goals High Throughput Number of packets a switch ca forward per secod High Scalability How may iput/output ports ca it coect Low Cost Per port moetary costs Sprig 208 CS 438 Staff, Uiversity of Illiois 28

29 Two simple fabrics Two simple fabrics for very large highperformace switches! Shared bus or memory: Low $, low throughput Full mesh: High $, high throughput Sprig 208 CS 438 Staff, Uiversity of Illiois 29

30 Special Purpose Switches Problem Coect N iputs to M outputs NxM ( N by M ) switch Ofte N = M Goals Iput Port Iput Port Iput Port Iput Port Iput Port Iput Port High throughput Best is MIN(sum of iputs, sum of outputs) Avoid cotetio Good scalability Liear size/cost growth Switch Fabric Sprig 208 CS 438 Staff, Uiversity of Illiois 30

31 Switch Desig Ports hadle complexity Forwardig decisios Bufferig Simple fabric Iput Port Iput Port Iput Port Iput Port Iput Port Iput Port Move packets from iputs to outputs Switch Fabric May have a small amout of iteral bufferig Sprig 208 CS 438 Staff, Uiversity of Illiois 3

32 Switch Desig Goals Throughput Mai problem is cotetio Need a good traffic model Arrival time Destiatio port Packet legth Telephoy modelig is well uderstood Util faxes ad modems Modelig of data traffic is ew Not well uderstood Will good models help? Sprig 208 CS 438 Staff, Uiversity of Illiois 32

33 Switch Desig Goals Cotetio Avoid cotetio through itelliget bufferig Use output bufferig whe possible Apply back pressure through switch fabric Improve iput bufferig through o-fifo buffers Reduces head-of-lie blockig Drop packets if iput buffers overflow Sprig 208 CS 438 Staff, Uiversity of Illiois 33

34 Switch Desig Goals Scalability O(N) ports Port desig complexity O(N) gives O(N 2 ) for etire switch Port desig complexity of O() gives O(N) for etire switch Sprig 208 CS 438 Staff, Uiversity of Illiois 34

35 Switch Desig Crossbar Switches Baya Networks Batcher Networks Sushie Switch Sprig 208 CS 438 Staff, Uiversity of Illiois 35

36 Crossbar Switch Every iput port is coected to every output port NxN Output ports Complexity scales as O(N 2 ) Sprig 208 CS 438 Staff, Uiversity of Illiois 36

37 Crossbar Switch Iput Port Iput Port Iput Port Iput Port Sprig 208 CS 438 Staff, Uiversity of Illiois 37

38 Kockout Switch Problem Full crossbar requires each output port to hadle up to N iput packets Assumptio It is ulikely that N iputs will have packets destied for the same output port Istead implemet each port to hadle L<N packets at the same time Challeges What value of L to use Maagig hotspots Sprig 208 CS 438 Staff, Uiversity of Illiois 38

39 Kockout Switch Output port desig Packet filters Recogize packets destied for a specific port Cocetrator Queue Selects up to L packets from those destied for this port Kocks out (discards) excess packets Legth L Sprig 208 CS 438 Staff, Uiversity of Illiois 39

40 Kockout Switch Goal Wat some fairess No sigle iput should have its packets always kocked out Approach Essetially a kock out teis touramet with each game of 2 players (packets) chose radomly Overall wier is selected by playig log N rouds, ad keepig the wier Sprig 208 CS 438 Staff, Uiversity of Illiois 40

41 Kockout Switch Pick L from N packets at a port Output port maitais L cyclic buffers Shifter places up to L packets i oe cycle Each buffer gets oly oe packet Output port uses roud-robi betwee buffers Arrival order is maitaied Output ports scale as O(N) Sprig 208 CS 438 Staff, Uiversity of Illiois 4

42 Kockout Switch R R 4 R 2 R 3 Choose L of N Ex: 2 of 4 R 2x2 radom selector 4 4 D Choice R 3 Choice Discard What happes if more tha L arrive? Discard D Delay uit Sprig 208 CS 438 Staff, Uiversity of Illiois 42

43 Self-Routig Fabrics Idea Use source routig o etwork i switch Iput port attaches output port umber as header Fabric routes packet based o output port Types Baya Network Batcher-Baya Network Sushie Switch Sprig 208 CS 438 Staff, Uiversity of Illiois 43

44 Baya Network A etwork of 2x2 switches Each elemet routes to output 0 or based o packet header A switch at stage i looks at bit i i the header Sprig 208 CS 438 Staff, Uiversity of Illiois 44

45 Baya Network Sprig 208 CS 438 Staff, Uiversity of Illiois 45

46 Baya Network Sprig 208 CS 438 Staff, Uiversity of Illiois 46

47 Baya Network Perfect Shuffle N iputs requires log 2 N stages of N/2 switchig elemets Complexity o order of N log 2 N Collisios If two packets arrive at the same switch destied for the same output port, a collisio will occur If all packets are sorted i ascedig order upo arrival to a baya etwork, o collisios will occur! Sprig 208 CS 438 Staff, Uiversity of Illiois 47

48 Collisio i a Baya Network Collisio! Happes because iput is usorted Sprig 208 CS 438 Staff, Uiversity of Illiois 48

49 Batcher Network Performs merge sort A etwork of 2x2 switches Each elemet routes to output 0 or based o packet header A switch at stage i looks at the whole header Two types of switches Up switch Seds higher umber to top output (0) Dow switch Seds higher umber to bottom output () U D Sprig 208 CS 438 Staff, Uiversity of Illiois 49

50 Batcher Network 7 3 D D D 3 6 U Sort 6 7 D 7 Merge 6 6 D 7 7 Merge Sprig 208 CS 438 Staff, Uiversity of Illiois 50

51 Batcher Network Sort iputs 0 3 i ascedig order D D D D D D U D D D D D Merge 0 3 with 4 7 8x8 Switch D U U D D D U U U D D D Sort iputs 4 7 i descedig order Sprig 208 CS 438 Staff, Uiversity of Illiois 5

52 Batcher Network How it really works Merger is preseted with a pair of sorted lists, oe i ascedig order, oe i descedig order First stage of merger seds packets to the correct half of the etwork Secod stage seds them to the correct quarter Size N/2 switches per stage log 2 N x ( + log 2 N)/2 stages Complexity = N log 22 N Sprig 208 CS 438 Staff, Uiversity of Illiois 52

53 Batcher-Baya Network Idea Attach a batcher etwork back-to-back with a baya etwork Arbitrary uique permutatios ca be routed without cotetio Sprig 208 CS 438 Staff, Uiversity of Illiois 53