Elementary Educational Computer
|
|
- Alice Bryant
- 6 years ago
- Views:
Transcription
1 Chapter 5 Elemetary Educatioal Computer. Geeral structure of the Elemetary Educatioal Computer (EEC) The EEC coforms to the 5 uits structure defied by vo Neuma's model (.) All uits are preseted i a simplified form cosistig of oly basic compoets. (.) Structure of the EEC preseted i Aex 5. (.3). Presetatio of the EEC uits.. Memory Uit (MU) Oe level memory cosistig of the Mai Memory (MM) Every locatio idetified by its ow address o k bits. Commuicatio with other uits through: a) MAR Memory Address Register b) MBR Memory Buffer Register or Memory Data Register Orgaizatio of the memory: k locatios of bits, thus k memory array Two operatios are allowed: ad WRITE, cotrolled by the Cotrol Uit Descriptio of the cycle ) Address placed i MAR ) cotrol sigal 3) Extractio from the addressed locatio 4) Store data i MBR 5- (..) (..) (..3) (..4) (..5) (..6) Descriptio of the WRITE cycle ) Address placed i MAR ) Data trasferred i MBR 3) WRITE cotrol sigal 4) Store data i the addressed locatio Types of WRITE ad commads issued by the Cotrol Uit: two idepedet(r,w) or oe commo (R / W ).. Arithmetic ad Logic Uit (ALU) 5- (..7) (..8) Implemets biary arithmetic o bits (..) Dimesio of ALU operatioal uits is assumed (..) All registers iside ALU are -dimesioal (..3) ALU cotais a simple register file ad a (..4) processig device Processig sectio cosists of a Adder/Subtractor (..5) ad a Shifter Register file cosists of a Accumulator, three auxiliary registers RX,, ad a Flag (..6) (Status) register () ALU performs a limited set of primitive (..7) operatios Commuicatio betwee ALU ad CU: CU seds the commads via cotrol lies, whereas ALU seds the status of the registers cotet (status (..8) sigals, flags, coditio sigals), usually of the Accumulator. Possible set of status bits: zero, parity, sig, (..9) overflow etc. Operads are extracted either from register file (local memory) or from MM. Extractio from (..0) MM implies a cycle. Role of the Accumulator: it is a special register commuicatig directly with the processig (..) device, that cotais oe of the operads ad where the result after processig is stored.
2 The Arithmetic ad Logic operatios performed i ALU are o oe or two operads (moadic or diadic operatios)..3. Cotrol Uit (CU) The CU is formed of the followig blocks: ) Program Couter (), o k bits ) Istructio Register (), o bits 3) Fuctio decoder (DEC L/ L ) 4) Cotrol Block (Logic Sequecer, Cotrol Sequecer) Program Couter cotais a memory address where the ext istructio to be executed is stored; sice the addressig space of MM is k, the dimesio of is k (idetical with the dimesio of MAR). has the icremetig facility, as well as a parallel load facility. Istructio Register () cotais the curret istructio which is i executio. The width of coicides with the width of a istructio ad i the case of EEC it is. is divided i two subregisters accordig to the format of the istructio. Structure of the : (..) (.3.) (.3.) (.3.3) (.3.4) (.3.5) (.3.6) The Address subregister cotais a address of the MM where oe operad is stored. I case of two operads operatio it is assumed that the other operad is i the Accumulator. For reaso of simplicity, there are missig the Fuctio Register ad the Address Register. Also, the address field cotais always the effective address of the operad (ot the logical address). The cetral role i the CU is played by the Cotrol Block (Cotrol Sequecer), which geerates the cotrol sigals for the other uits accordig to the operatio (fuctio) to be executed. The iputs i the Cotrol Block are the decoded (iterpreted) fuctio, master clock (from a Clock Geerator) ad status flags (from ALU). Cotrol Block is a complex sequetial machie, that is why it is also called Cotrol Sequecer..4. Iput/Output uits (I/O) I case of EEC the I/O system is composed of simple Iput/Output devices, at the lowest level a register o bits. They are commuicatig with the ALU (Accumulator) ad MM (MBR), as well as with the Cotrol Uit (Istructio Register). 3. The register structure of the EEC (.3.9) (.3.0) (.3.) (.3.) (.3.3) (.3.4) L K OODE ADDRESS SUBREGISTER SUBREGISTER The OODE subregister commuicates with the fuctio decoder to iterpret the curret istructio (to decide which fuctio must be executed) (.3.7) (.3.8) Ay digital system ca be viewed as a uio of geeralized registers ad the data paths itercoectig them. Eve the memory formed of k locatios ca be cosidered as formed of k registers, as each locatio is a -bit register. By mergig ALU with CU, to form the, the etire structure of the EEC ca be reduced to the followig set of registers (3.3): (3.) (3.)
3 AX AX AX3 x x y y y y z z z z k Addresses 0 zzzz k - Mai Memory WRITE x x y y y y IU OU (3.3) 4. Mode of operatio 4. Geeral cosideratios Accordig to the vo Neuma's priciples, both istructios ad data are located i memory, i biary coded form. Ay istructio is executed i two major phases FETCH phase, cosistig i extractig the curret istructio from the memory ad decodig the OODE field EXECUTE phase, cosistig i effective executio of the operatio o the defied operads (data). 4.. FETCH phase (4..) (4..) Where: = flag register (status register), o bits = Accumulator, o bits AX, AX, AX3 = auxiliary registers, o bits = Istructio Register, o bits (3.4) xx = the opcode field of the istructio, o L bits = the address field of the istructio, o k bits = Program Couter, o k bits IU = Iput uit, o bits OU = Output uit, o bits This register view of the EEC is useful for explaiig the flow of operatios that take place for executio of istructios. (3.5) The iitial address of the first istructio to be executed is already stored i (4..) The cotet of is trasferred to MAR. (4..) CU is issuig a commad to MM ad a read cycle is iitiated. (4..3) The cotet of the read locatio, represetig a Istructio, is trasferred to MBR. (4..4) From MBR the istructio is trasferred to from CU. (4..5) The subregister cotaiig OODE, o L bits, is trasferred to the Fuctio Decoder. (4..6) Fuctio Decoder decodes the OODE ad iforms the Cotrol Block of the CU, which, i tur, issues the (4..7) appropriate cotrol sigals to the other uits. CU is icremetig the to poit to the ext istructio. (4..8)
4 I a simplified RTL (Register Trasfer Laguage) the FETCH phase ca be described i the followig form:. MAR (). 3. (MBR) 4. DEC () OODE 5. ()+ 6. Go to EXECUTE phase (4..9) where: () OODE meas the cotet of the OODE subregister of the ; () meas the cotet of the ; (MBR) meas the cotet of the MBR. Schematically, this phase ca be represeted i the register view of the EEC as follows (4..) AX AX AX3 4 x x y y y y z z z z 5 3 zzzz Memory x x y y y y (4..0) (4..) IU OU 4.3. EXECUTE phase As stated before, the FETCH phase is commo for all Istructios, whereas EXECUTE phase is specific for (4.3.) each kid of Istructio. I what follows there are described extesively several simple Istructios that are executed i EEC. (4.3.) A) ADD, address This represets the additio of two operads Istructio, where the first operad is i the Accumulator, the secod operad is i the memory at the address (), while the sum is saved i the Accumulator. I a symbolic maer this operatio ca be described as follows: () + (Memory) ADDRESS The address () of the secod operad is give i the Istructio beig stored i the () ADDRESS subregister. The etire operatio takes place i the followig steps:. Trasfer the address field from () ADDRESS ito MAR, which meas trasfer ito MAR.. Iitiate a operatio from the locatio havig the address. 3. Trasfer of the extracted operad ito the ALU, i register RX. 4. Perform the additio betwee the cotets of ad AX, the store the result i the Accumulator 5. Chage the correspodig flags from the. 6. Go to the ext FETCH phase I RTL otatio:. MAR () ADDRESS. 3. (RX) (Memory) ADDRESS 4. () + (RX) 5. New flags 6. Go to FETCH phase (4.3.3) (4.3.4) (4.3.5) (4.3.6)
5 I the register view of the EEC the realizatio of ADD (4.3.7) Istructio is preseted i (4.3.8) Mai Memory NEW FLAGS RX OPERAND 3 OPERAND 4 4 result ADD (4.3.8) B) SUB, address This represets the subtractio operatio, where the subtrahed, that is the first operad, is i the Accumulator, while the miued, that is the secod (4.3.9) operad, is i the memory at the address specified explicitly i the istructio. The realizatio of the subtractio assumes readig from the memory of the secod operad ad trasferrig it ito the ALU, i the register RX. After that, the (4.3.0) subtractio takes place i the processig device ad the differece is saved i, accompaied by the correspodig chages of flags i the. Symbolically: () (Memory) ADDRESS (4.3.) The etire operatio takes place i the followig steps:. Trasfer the address field from () ADDRESS ito (4.3.) OPERAND MAR, which meas trasfer of ito MAR.. Iitiate a cycle, to extract the cotet of the locatio havig the address 3. Trasfer of the extracted operad i ALU, i the register RX. 4. The subtractio operatio takes place i the processig device by subtractig the cotet of RX from the cotet of ; the differece is saved i the Accumulator. 5. Chage the appropriate status bits i 6. Go to the ext FETCH phase. I RTL otatio:. MAR () ADDRESS. 3. RX (Memory) ADDRESS 4. () (RX) 5. New Flags 6. Go to FETCH phase I the register view the executio of SUB istructio is represeted i the ext figure (4.3.5) Mai Memory RX 4 NEW FLAGS OPERAND OPERAND 4 differece SUBTRACTION OPERAND (4.3.) (4.3.3) (4.3.4) (4.3.5)
6 C) LOAD, address The LOAD Istructio esures readig of a operad from the memory at the address () specified i the istructio ad trasferrig it ito the Accumulator. Symbolically: (Memory) ADDRESS The etire operatio takes place i the followig steps:. Trasfer the address field from () ADDRESS ito MAR, which meas trasfer ito MAR.. Iitiate a operatio from the locatio with the address. 3. Trasfer the extracted operad ito the ALU, i the Accumulator ad chage the flags from. 4. Go to the ext FETCH phase. I the register view of the EEC the realizatio of LOAD Istructio is preseted i the ext figure (4.3.0): RX NEW FLAGS OPERAND 4 3 Memory Uit OPERAND (4.3.6) (4.3.7) (4.3.8) (4.3.9) (4.3.0) Observatio: if i the OODE there is provided a subfield specifyig the destiatio register from the ALU, the there ca be defied variats of the LOAD istructio: RX (Memory) ADDRESS (Memory) ADDRESS (Memory) ADDRESS D) STORE, address The STORE Istructio esures the trasfer of the cotet of the Accumulator ito the memory ad storig it i the locatio havig the address () give i the istructio. Symbolically: Memory ADDRESS () The etire operatio takes place i the followig steps:. Trasfer the cotet of the () ADDRESS ito the MAR; the cotet of MAR becomes.. Trasfer the cotet of the Accumulator ito the MBR; i this way the operad is prepared for further storig i the memory. 3. Iitiate a WRITE operatio, realisig storig of the cotet from the MAR ito the locatio with the address. 4. Go to the ext FETCH phase. I the register view of the EEC this istructio is represeted i (4.3.6): (4.3.) (4.3.) (4.3.3) (4.3.4) (4.3.5) 5-5-
7 RX Mai Memory WRITE 3 I the register view of EEC represetatio the executio of this istructio is give i (4.3.30): Memory RX OPERAND OPERAND (4.3.6) (4.3.30) Observatio: The STORE Istructio ca preset variatios by icludig i the OODE a subfield specifyig the source register from ALU; i this way, the cotet of RX, or ca be stored i the memory at the specified address give i the Istructio (Memory) ADDRESS (RX) (Memory) ADDRESS () (Memory) ADDRESS () E) JUMP, address This is a ucoditioal JUMP at the address specified i the Istructio. The implemetatio is quite simple by trasferrig the address from the () ADDRESS ito the. I this way, istead of usig the address (), the address () will be used i the ext FETCH phase for extractig the ext istructio from the memory. The executio of this ucoditioal JUMP Istructio is very simple:. () () ADDRESS. Go to the ext FETCH phase. (4.3.7) (4.3.8) (4.3.9) F) Coditioal JUMP, address The coditioal JUMP Istructio tests a coditio ad if it is true the a jump takes place at the give address i the Istructio; otherwise the ormal flow of executio cotiues, that is the cotet of remais ualtered, so that the ext FETCH will take place at the address (). The test operatio cosists i checkig a flag (a coditio bit) from the Flag Register,. As metioed before, amog the usual flags the followig are commo: ZERO flag if the cotet of the Accumulator is 0 SIGN flag reproducig the most sigificat bit of the Accumulator (if it is 0, the a positive umber is i the, if it is, the a egative umber is i the ) Istructio to be fetched (4.3.3) (4.3.3)
8 PARITY flag shows if the umber of s i the Accumulator is odd or eve CARRY flag if after a additio/subtractio (4.3.3) operatio it was geerated a carry from the most sigificat colum. The OODE for this coditioal JUMP will cotai a subfield to idetify which flag is to be tested; thereby (4.3.33) there are may Coditioal JUMP Istructios depedig o how may flags are defied i the architecture. Symbolically, (4.3.34) If (coditio) go to (address) else () The steps of implemetig these istructios are:. Test the flag defied by the OODE. If the coditio is TRUE the trasfer the address (4.3.35) from () ADDRESS ito the, ad go to 4 3. If the coditio is FALSE the go to 4 4. Go to ext FETCH phase. I the register view of the EEC represetatio (4.3.37): (4.3.36) Memory RX Fj flag idetificatio switch / TRUE 5-5 Next Istructio for FALSE cod Next Istructio for TRUE cod (4.3.37) G) INPUT, address The address field would specify oe of the set of Iput Registers represetig the INPUT UNIT. I this particular case it was used a simple iput register, therefore the address field is irrelevat. But, i geeral case, there are defied k differet addresses of iput registers. This Istructio reads the cotet of the addressed register 5-6 (4.3.38) (4.3.39) ad trasfers it ito the, i the Accumulator. Thus, symbolically: (4.3.40) (Iput Register) ADDRESS The steps of implemetatio:. Idetify the Iput Register from the address stored i () ADDRESS. the addressed Iput Register ad trasfer its cotet ito the. 3. Go to ext FETCH phase. I the register view of the EEC the executio of this istructio is preseted i (4.3.43): Memory RX dddddd (4.3.4) (4.4.4) (4.3.43) Iput Register dddddd Output Register
9 H) OUPUT, address The address field would specify oe of the set of Output Registers represetig the Output Uit. I this particular case of EEC there is provided a sigle Output Register, so that the address field has o sigificace. I geeral case, there ca be defied k differet addresses of Output Registers. This istructio trasfers the cotet of the Accumulator to the addressed Output Register ad writes it i. Thus, symbolically: Output Register ADDRESS () The steps of the implemetatio:. Idetify the Output Register from the address existig i () ADDRESS. Trasfer the operad from to the idetified Output Register ad write it i the register. 3. Go to ext FETCH phase. I the register view of the EEC the executio of this istructio is preseted i (4.3.50): Mai Memory (4.3.44) (4.3.45) (4.3.46) (4.3.47) (4.3.48) (4.3.49) RX dddddd 5-7 WRITE (4.3.50) Iput Register Output Register dddddd
CSC 220: Computer Organization Unit 11 Basic Computer Organization and Design
College of Computer ad Iformatio Scieces Departmet of Computer Sciece CSC 220: Computer Orgaizatio Uit 11 Basic Computer Orgaizatio ad Desig 1 For the rest of the semester, we ll focus o computer architecture:
More informationEnd Semester Examination CSE, III Yr. (I Sem), 30002: Computer Organization
Ed Semester Examiatio 2013-14 CSE, III Yr. (I Sem), 30002: Computer Orgaizatio Istructios: GROUP -A 1. Write the questio paper group (A, B, C, D), o frot page top of aswer book, as per what is metioed
More informationAppendix D. Controller Implementation
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Appedix D Cotroller Implemetatio Cotroller Implemetatios Combiatioal logic (sigle-cycle); Fiite state machie (multi-cycle, pipelied);
More informationComputer Architecture. Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff
Computer rchitecture Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff Computer Hardware Orgaizatio Processor Performs all computatios; coordiates data trasfer Iput
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Part A Datapath Design
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter The Processor Part A path Desig Itroductio CPU performace factors Istructio cout Determied by ISA ad compiler. CPI ad
More informationChapter 4 The Datapath
The Ageda Chapter 4 The Datapath Based o slides McGraw-Hill Additioal material 24/25/26 Lewis/Marti Additioal material 28 Roth Additioal material 2 Taylor Additioal material 2 Farmer Tae the elemets that
More information1. SWITCHING FUNDAMENTALS
. SWITCING FUNDMENTLS Switchig is the provisio of a o-demad coectio betwee two ed poits. Two distict switchig techiques are employed i commuicatio etwors-- circuit switchig ad pacet switchig. Circuit switchig
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 13 Control and Sequencing: Hardwired and Microprogrammed Control
EE 459/500 HDL Based Digital Desig with Programmable Logic Lecture 13 Cotrol ad Sequecig: Hardwired ad Microprogrammed Cotrol Refereces: Chapter s 4,5 from textbook Chapter 7 of M.M. Mao ad C.R. Kime,
More informationK-NET bus. When several turrets are connected to the K-Bus, the structure of the system is as showns
K-NET bus The K-Net bus is based o the SPI bus but it allows to addressig may differet turrets like the I 2 C bus. The K-Net is 6 a wires bus (4 for SPI wires ad 2 additioal wires for request ad ackowledge
More informationChapter 1. Introduction to Computers and C++ Programming. Copyright 2015 Pearson Education, Ltd.. All rights reserved.
Chapter 1 Itroductio to Computers ad C++ Programmig Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Overview 1.1 Computer Systems 1.2 Programmig ad Problem Solvig 1.3 Itroductio to C++ 1.4 Testig
More information. Written in factored form it is easy to see that the roots are 2, 2, i,
CMPS A Itroductio to Programmig Programmig Assigmet 4 I this assigmet you will write a java program that determies the real roots of a polyomial that lie withi a specified rage. Recall that the roots (or
More informationChapter 5: Processor Design Advanced Topics. Microprogramming: Basic Idea
5-1 Chapter 5 Processor Desig Advaced Topics Chapter 5: Processor Desig Advaced Topics Topics 5.3 Microprogrammig Cotrol store ad microbrachig Horizotal ad vertical microprogrammig 5- Chapter 5 Processor
More informationAPPLICATION NOTE PACE1750AE BUILT-IN FUNCTIONS
APPLICATION NOTE PACE175AE BUILT-IN UNCTIONS About This Note This applicatio brief is iteded to explai ad demostrate the use of the special fuctios that are built ito the PACE175AE processor. These powerful
More informationComputer Systems - HS
What have we leared so far? Computer Systems High Level ENGG1203 2d Semester, 2017-18 Applicatios Sigals Systems & Cotrol Systems Computer & Embedded Systems Digital Logic Combiatioal Logic Sequetial Logic
More informationA New Morphological 3D Shape Decomposition: Grayscale Interframe Interpolation Method
A ew Morphological 3D Shape Decompositio: Grayscale Iterframe Iterpolatio Method D.. Vizireau Politehica Uiversity Bucharest, Romaia ae@comm.pub.ro R. M. Udrea Politehica Uiversity Bucharest, Romaia mihea@comm.pub.ro
More informationCMSC Computer Architecture Lecture 2: ISA. Prof. Yanjing Li Department of Computer Science University of Chicago
CMSC 22200 Computer Architecture Lecture 2: ISA Prof. Yajig Li Departmet of Computer Sciece Uiversity of Chicago Admiistrative Stuff Lab1 out toight Due Thursday (10/18) Lab1 review sessio Tomorrow, 10/05,
More informationPython Programming: An Introduction to Computer Science
Pytho Programmig: A Itroductio to Computer Sciece Chapter 6 Defiig Fuctios Pytho Programmig, 2/e 1 Objectives To uderstad why programmers divide programs up ito sets of cooperatig fuctios. To be able to
More informationThe Magma Database file formats
The Magma Database file formats Adrew Gaylard, Bret Pikey, ad Mart-Mari Breedt Johaesburg, South Africa 15th May 2006 1 Summary Magma is a ope-source object database created by Chris Muller, of Kasas City,
More informationFundamentals of. Chapter 1. Microprocessor and Microcontroller. Dr. Farid Farahmand. Updated: Tuesday, January 16, 2018
Fudametals of Chapter 1 Microprocessor ad Microcotroller Dr. Farid Farahmad Updated: Tuesday, Jauary 16, 2018 Evolutio First came trasistors Itegrated circuits SSI (Small-Scale Itegratio) to ULSI Very
More informationComputer Architecture
University of Craiova Faculty of Automation, Computers & Electronics Department of Computers & Information Technology Computer Architecture Elementary Educational Computer (EEC) Cătălina Mancaș catalina.mancas@yahoo.it
More informationEE123 Digital Signal Processing
Last Time EE Digital Sigal Processig Lecture 7 Block Covolutio, Overlap ad Add, FFT Discrete Fourier Trasform Properties of the Liear covolutio through circular Today Liear covolutio with Overlap ad add
More informationLecture 1: Introduction and Strassen s Algorithm
5-750: Graduate Algorithms Jauary 7, 08 Lecture : Itroductio ad Strasse s Algorithm Lecturer: Gary Miller Scribe: Robert Parker Itroductio Machie models I this class, we will primarily use the Radom Access
More informationLecture 3. RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram
Lecture 3 RTL Desig Methodology Trasitio from Pseudocode & Iterface to a Correspodig Block Diagram Structure of a Typical Digital Data Iputs Datapath (Executio Uit) Data Outputs System Cotrol Sigals Status
More informationEE260: Digital Design, Spring /16/18. n Example: m 0 (=x 1 x 2 ) is adjacent to m 1 (=x 1 x 2 ) and m 2 (=x 1 x 2 ) but NOT m 3 (=x 1 x 2 )
EE26: Digital Desig, Sprig 28 3/6/8 EE 26: Itroductio to Digital Desig Combiatioal Datapath Yao Zheg Departmet of Electrical Egieerig Uiversity of Hawaiʻi at Māoa Combiatioal Logic Blocks Multiplexer Ecoders/Decoders
More informationCMSC Computer Architecture Lecture 3: ISA and Introduction to Microarchitecture. Prof. Yanjing Li University of Chicago
CMSC 22200 Computer Architecture Lecture 3: ISA ad Itroductio to Microarchitecture Prof. Yajig Li Uiversity of Chicago Lecture Outlie ISA uarch (hardware implemetatio of a ISA) Logic desig basics Sigle-cycle
More informationChapter 10. Defining Classes. Copyright 2015 Pearson Education, Ltd.. All rights reserved.
Chapter 10 Defiig Classes Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Overview 10.1 Structures 10.2 Classes 10.3 Abstract Data Types 10.4 Itroductio to Iheritace Copyright 2015 Pearso Educatio,
More informationPython Programming: An Introduction to Computer Science
Pytho Programmig: A Itroductio to Computer Sciece Chapter 1 Computers ad Programs 1 Objectives To uderstad the respective roles of hardware ad software i a computig system. To lear what computer scietists
More informationDescription of Single Cycle Computer (SCC)
Descriptio of Sigle Cycle Computer (SCC) Refereces: Chapter 9 of M. Morris Mao ad Charles Kime, Logic ad Computer Desig Fudametals, Pearso Pretice Hall, 4 th Editio, 28. Overview Part Datapaths Itroductio
More informationChapter 3 Classification of FFT Processor Algorithms
Chapter Classificatio of FFT Processor Algorithms The computatioal complexity of the Discrete Fourier trasform (DFT) is very high. It requires () 2 complex multiplicatios ad () complex additios [5]. As
More informationEvaluation scheme for Tracking in AMI
A M I C o m m u i c a t i o A U G M E N T E D M U L T I - P A R T Y I N T E R A C T I O N http://www.amiproject.org/ Evaluatio scheme for Trackig i AMI S. Schreiber a D. Gatica-Perez b AMI WP4 Trackig:
More informationCMSC Computer Architecture Lecture 12: Virtual Memory. Prof. Yanjing Li University of Chicago
CMSC 22200 Computer Architecture Lecture 12: Virtual Memory Prof. Yajig Li Uiversity of Chicago A System with Physical Memory Oly Examples: most Cray machies early PCs Memory early all embedded systems
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Single-Cycle Disadvantages & Advantages
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 4 The Processor Pipeliig Sigle-Cycle Disadvatages & Advatages Clk Uses the clock cycle iefficietly the clock cycle must
More informationChapter 2. C++ Basics. Copyright 2015 Pearson Education, Ltd.. All rights reserved.
Chapter 2 C++ Basics Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Overview 2.1 Variables ad Assigmets 2.2 Iput ad Output 2.3 Data Types ad Expressios 2.4 Simple Flow of Cotrol 2.5 Program
More informationUNIVERSITY OF MORATUWA
UNIVERSITY OF MORATUWA FACULTY OF ENGINEERING DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING B.Sc. Egieerig 2014 Itake Semester 2 Examiatio CS2052 COMPUTER ARCHITECTURE Time allowed: 2 Hours Jauary 2016
More informationAnalysis Metrics. Intro to Algorithm Analysis. Slides. 12. Alg Analysis. 12. Alg Analysis
Itro to Algorithm Aalysis Aalysis Metrics Slides. Table of Cotets. Aalysis Metrics 3. Exact Aalysis Rules 4. Simple Summatio 5. Summatio Formulas 6. Order of Magitude 7. Big-O otatio 8. Big-O Theorems
More information% Sun Logo for. X3T10/95-229, Revision 0. April 18, 1998
Su Microsystems, Ic. 2550 Garcia Aveue Moutai View, CA 94045 415 960-1300 X3T10/95-229, Revisio 0 April 18, 1998 % Su Logo for Joh Lohmeyer Chairperso, X3T10 Symbios Logic Ic. 1635 Aeroplaza Drive Colorado
More informationGoals of the Lecture UML Implementation Diagrams
Goals of the Lecture UML Implemetatio Diagrams Object-Orieted Aalysis ad Desig - Fall 1998 Preset UML Diagrams useful for implemetatio Provide examples Next Lecture Ð A variety of topics o mappig from
More informationChapter 11. Friends, Overloaded Operators, and Arrays in Classes. Copyright 2014 Pearson Addison-Wesley. All rights reserved.
Chapter 11 Frieds, Overloaded Operators, ad Arrays i Classes Copyright 2014 Pearso Addiso-Wesley. All rights reserved. Overview 11.1 Fried Fuctios 11.2 Overloadig Operators 11.3 Arrays ad Classes 11.4
More informationChapter 4. Procedural Abstraction and Functions That Return a Value. Copyright 2015 Pearson Education, Ltd.. All rights reserved.
Chapter 4 Procedural Abstractio ad Fuctios That Retur a Value Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Overview 4.1 Top-Dow Desig 4.2 Predefied Fuctios 4.3 Programmer-Defied Fuctios 4.4
More informationDESIGN AND ANALYSIS OF LDPC DECODERS FOR SOFTWARE DEFINED RADIO
DESIGN AND ANALYSIS OF LDPC DECODERS FOR SOFTWARE DEFINED RADIO Sagwo Seo, Trevor Mudge Advaced Computer Architecture Laboratory Uiversity of Michiga at A Arbor {swseo, tm}@umich.edu Yumig Zhu, Chaitali
More informationA SOFTWARE MODEL FOR THE MULTILAYER PERCEPTRON
A SOFTWARE MODEL FOR THE MULTILAYER PERCEPTRON Roberto Lopez ad Eugeio Oñate Iteratioal Ceter for Numerical Methods i Egieerig (CIMNE) Edificio C1, Gra Capitá s/, 08034 Barceloa, Spai ABSTRACT I this work
More informationThe CCITT Communication Protocol for Videophone Teleconferencing Equipment
The CCITT Commuicatio Protocol for Videophoe Telecoferecig Equipmet Ralf Hiz Daimler-Bez AG Istitut ffir Iformatiostechik Tcl. 0731 / 505-21 32 Fax. 0731 / 505-41 04 Wilhelm-R.uge-Str. 11 7900 Ulm Abstract
More informationGetting Started. Getting Started - 1
Gettig Started Gettig Started - 1 Issue 1 Overview of Gettig Started Overview of Gettig Started This sectio explais the basic operatios of the AUDIX system. It describes how to: Log i ad log out of the
More informationIntroduction CHAPTER Computers
Iside a Computer CHAPTER Itroductio. Computers A computer is a electroic device that accepts iput, stores data, processes data accordig to a set of istructios (called program), ad produces output i desired
More informationCopyright 2016 Ramez Elmasri and Shamkant B. Navathe
Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 18 Strategies for Query Processig Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe Itroductio DBMS techiques to process a query Scaer idetifies
More information% Sun Logo for Frame. X3T10/95-229, Revision 2. September 28, 1995
Su Microsystems, Ic. 2550 Garcia Aveue Moutai View, CA 94045 415 960-1300 X3T10/95-229, Revisio 2 September 28, 1995 % Su Logo for Frame Joh Lohmeyer Chairperso, X3T10 Symbios Logic Ic. 1635 Aeroplaza
More informationImage Segmentation EEE 508
Image Segmetatio Objective: to determie (etract) object boudaries. It is a process of partitioig a image ito distict regios by groupig together eighborig piels based o some predefied similarity criterio.
More information9.1. Sequences and Series. Sequences. What you should learn. Why you should learn it. Definition of Sequence
_9.qxd // : AM Page Chapter 9 Sequeces, Series, ad Probability 9. Sequeces ad Series What you should lear Use sequece otatio to write the terms of sequeces. Use factorial otatio. Use summatio otatio to
More informationChapter 3. Floating Point Arithmetic
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 3 Floatig Poit Arithmetic Review - Multiplicatio 0 1 1 0 = 6 multiplicad 32-bit ALU shift product right multiplier add
More informationImprovement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation
Improvemet of the Orthogoal Code Covolutio Capabilities Usig FPGA Implemetatio Naima Kaabouch, Member, IEEE, Apara Dhirde, Member, IEEE, Saleh Faruque, Member, IEEE Departmet of Electrical Egieerig, Uiversity
More informationReversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits
Egieerig Letters, :, EL Reversible Realizatio of Quaterary Decoder, Multiplexer, ad Demultiplexer Circuits Mozammel H.. Kha, Member, ENG bstract quaterary reversible circuit is more compact tha the correspodig
More informationDescriptive Statistics Summary Lists
Chapter 209 Descriptive Statistics Summary Lists Itroductio This procedure is used to summarize cotiuous data. Large volumes of such data may be easily summarized i statistical lists of meas, couts, stadard
More informationComputers and Scientific Thinking
Computers ad Scietific Thikig David Reed, Creighto Uiversity Chapter 15 JavaScript Strigs 1 Strigs as Objects so far, your iteractive Web pages have maipulated strigs i simple ways use text box to iput
More informationPattern Recognition Systems Lab 1 Least Mean Squares
Patter Recogitio Systems Lab 1 Least Mea Squares 1. Objectives This laboratory work itroduces the OpeCV-based framework used throughout the course. I this assigmet a lie is fitted to a set of poits usig
More informationMorgan Kaufmann Publishers 26 February, COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 5
Morga Kaufma Publishers 26 February, 28 COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 5 Set-Associative Cache Architecture Performace Summary Whe CPU performace icreases:
More informationSolution printed. Do not start the test until instructed to do so! CS 2604 Data Structures Midterm Spring, Instructions:
CS 604 Data Structures Midterm Sprig, 00 VIRG INIA POLYTECHNIC INSTITUTE AND STATE U T PROSI M UNI VERSI TY Istructios: Prit your ame i the space provided below. This examiatio is closed book ad closed
More informationOne advantage that SONAR has over any other music-sequencing product I ve worked
*gajedra* D:/Thomso_Learig_Projects/Garrigus_163132/z_productio/z_3B2_3D_files/Garrigus_163132_ch17.3d, 14/11/08/16:26:39, 16:26, page: 647 17 CAL 101 Oe advatage that SONAR has over ay other music-sequecig
More informationForms of Information Representation in Digital Computers.
Chapter Forms of Iformatio Represetatio i Digital Computers.. Geeral Cosideratios There are distiguished the followig two fudametal modes of iformatio represetatio: (.) a) iteral; b) exteral; Iteral represetatios
More informationICS Regent. Communications Modules. Module Operation. RS-232, RS-422 and RS-485 (T3150A) PD-6002
ICS Reget Commuicatios Modules RS-232, RS-422 ad RS-485 (T3150A) Issue 1, March, 06 Commuicatios modules provide a serial commuicatios iterface betwee the cotroller ad exteral equipmet. Commuicatios modules
More informationLecture 2. RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram
Lecture 2 RTL Desig Methodology Trasitio from Pseudocode & Iterface to a Correspodig Block Diagram Structure of a Typical Digital Data Iputs Datapath (Executio Uit) Data Outputs System Cotrol Sigals Status
More informationReview: The ACID properties
Recovery Review: The ACID properties A tomicity: All actios i the Xactio happe, or oe happe. C osistecy: If each Xactio is cosistet, ad the DB starts cosistet, it eds up cosistet. I solatio: Executio of
More informationImproving Template Based Spike Detection
Improvig Template Based Spike Detectio Kirk Smith, Member - IEEE Portlad State Uiversity petra@ee.pdx.edu Abstract Template matchig algorithms like SSE, Covolutio ad Maximum Likelihood are well kow for
More informationHow do we evaluate algorithms?
F2 Readig referece: chapter 2 + slides Algorithm complexity Big O ad big Ω To calculate ruig time Aalysis of recursive Algorithms Next time: Litterature: slides mostly The first Algorithm desig methods:
More informationChapter 9. Pointers and Dynamic Arrays. Copyright 2015 Pearson Education, Ltd.. All rights reserved.
Chapter 9 Poiters ad Dyamic Arrays Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Overview 9.1 Poiters 9.2 Dyamic Arrays Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Slide 9-3
More information3D Model Retrieval Method Based on Sample Prediction
20 Iteratioal Coferece o Computer Commuicatio ad Maagemet Proc.of CSIT vol.5 (20) (20) IACSIT Press, Sigapore 3D Model Retrieval Method Based o Sample Predictio Qigche Zhag, Ya Tag* School of Computer
More informationIMP: Superposer Integrated Morphometrics Package Superposition Tool
IMP: Superposer Itegrated Morphometrics Package Superpositio Tool Programmig by: David Lieber ( 03) Caisius College 200 Mai St. Buffalo, NY 4208 Cocept by: H. David Sheets, Dept. of Physics, Caisius College
More informationCIS 121 Data Structures and Algorithms with Java Spring Stacks and Queues Monday, February 12 / Tuesday, February 13
CIS Data Structures ad Algorithms with Java Sprig 08 Stacks ad Queues Moday, February / Tuesday, February Learig Goals Durig this lab, you will: Review stacks ad queues. Lear amortized ruig time aalysis
More informationNeuro Fuzzy Model for Human Face Expression Recognition
IOSR Joural of Computer Egieerig (IOSRJCE) ISSN : 2278-0661 Volume 1, Issue 2 (May-Jue 2012), PP 01-06 Neuro Fuzzy Model for Huma Face Expressio Recogitio Mr. Mayur S. Burage 1, Prof. S. V. Dhopte 2 1
More informationBOOLEAN MATHEMATICS: GENERAL THEORY
CHAPTER 3 BOOLEAN MATHEMATICS: GENERAL THEORY 3.1 ISOMORPHIC PROPERTIES The ame Boolea Arithmetic was chose because it was discovered that literal Boolea Algebra could have a isomorphic umerical aspect.
More informationΤεχνολογία Λογισμικού
ΕΘΝΙΚΟ ΜΕΤΣΟΒΙΟ ΠΟΛΥΤΕΧΝΕΙΟ Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών Τεχνολογία Λογισμικού, 7ο/9ο εξάμηνο 2018-2019 Τεχνολογία Λογισμικού Ν.Παπασπύρου, Αν.Καθ. ΣΗΜΜΥ, ickie@softlab.tua,gr
More informationCopyright 2016 Ramez Elmasri and Shamkant B. Navathe
Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 19 Query Optimizatio Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe Itroductio Query optimizatio Coducted by a query optimizer i a DBMS Goal:
More informationIS-IS in Detail. ISP Workshops
IS-IS i Detail ISP Workshops These materials are licesed uder the Creative Commos Attributio-NoCommercial 4.0 Iteratioal licese (http://creativecommos.org/liceses/by-c/4.0/) Last updated 27 th November
More informationSoftware development of components for complex signal analysis on the example of adaptive recursive estimation methods.
Software developmet of compoets for complex sigal aalysis o the example of adaptive recursive estimatio methods. SIMON BOYMANN, RALPH MASCHOTTA, SILKE LEHMANN, DUNJA STEUER Istitute of Biomedical Egieerig
More informationModule Instantiation. Finite State Machines. Two Types of FSMs. Finite State Machines. Given submodule mux32two: Instantiation of mux32two
Give submodule mux32two: 2-to- MUX module mux32two (iput [3:] i,i, iput sel, output [3:] out); Module Istatiatio Fiite Machies esig methodology for sequetial logic -- idetify distict s -- create trasitio
More informationBasic allocator mechanisms The course that gives CMU its Zip! Memory Management II: Dynamic Storage Allocation Mar 6, 2000.
5-23 The course that gives CM its Zip Memory Maagemet II: Dyamic Storage Allocatio Mar 6, 2000 Topics Segregated lists Buddy system Garbage collectio Mark ad Sweep Copyig eferece coutig Basic allocator
More informationCMSC Computer Architecture Lecture 15: Multi-Core. Prof. Yanjing Li University of Chicago
CMSC 22200 Computer Architecture Lecture 15: Multi-Core Prof. Yajig Li Uiversity of Chicago Course Evaluatio Very importat Please fill out! 2 Lab3 Brach Predictio Competitio 8 teams etered the competitio,
More informationThe Closest Line to a Data Set in the Plane. David Gurney Southeastern Louisiana University Hammond, Louisiana
The Closest Lie to a Data Set i the Plae David Gurey Southeaster Louisiaa Uiversity Hammod, Louisiaa ABSTRACT This paper looks at three differet measures of distace betwee a lie ad a data set i the plae:
More informationBezier curves. Figure 2 shows cubic Bezier curves for various control points. In a Bezier curve, only
Edited: Yeh-Liag Hsu (998--; recommeded: Yeh-Liag Hsu (--9; last updated: Yeh-Liag Hsu (9--7. Note: This is the course material for ME55 Geometric modelig ad computer graphics, Yua Ze Uiversity. art of
More informationTHE WAY OF CALCULATING THE TRAFFIC AND SIGNALING NETWORK DIMENSION OF COMMON CHANNEL SIGNALING NO.7 (CCS7)
The Way of Calculatig The Traffic... THE WAY OF CALCULATIG THE TRAFFIC AD SIGALIG ETWORK DIMESIO OF COMMO CHAEL SIGALIG O.7 (CCS7) Departeme Tekik Elektro, Fakultas Tekik, Uiversitas Sumatera Utara Abstract:
More informationDigital System Design
July, 22 9:55 vra235_ch Sheet umber Page umber 65 black chapter Digital System Desig a b c d e f g h 8 7 6 5 4 3 2. Bd3 g6+, Ke8 d8 65 July, 22 9:55 vra235_ch Sheet umber 2 Page umber 66 black 66 CHAPTER
More informationPanel for Adobe Premiere Pro CC Partner Solution
Pael for Adobe Premiere Pro CC Itegratio for more efficiecy The makes video editig simple, fast ad coveiet. The itegrated pael gives users immediate access to all medialoopster features iside Adobe Premiere
More informationOn Infinite Groups that are Isomorphic to its Proper Infinite Subgroup. Jaymar Talledo Balihon. Abstract
O Ifiite Groups that are Isomorphic to its Proper Ifiite Subgroup Jaymar Talledo Baliho Abstract Two groups are isomorphic if there exists a isomorphism betwee them Lagrage Theorem states that the order
More informationBaan Tools User Management
Baa Tools User Maagemet Module Procedure UP008A US Documetiformatio Documet Documet code : UP008A US Documet group : User Documetatio Documet title : User Maagemet Applicatio/Package : Baa Tools Editio
More informationSorting in Linear Time. Data Structures and Algorithms Andrei Bulatov
Sortig i Liear Time Data Structures ad Algorithms Adrei Bulatov Algorithms Sortig i Liear Time 7-2 Compariso Sorts The oly test that all the algorithms we have cosidered so far is compariso The oly iformatio
More informationArchitectural styles for software systems The client-server style
Architectural styles for software systems The cliet-server style Prof. Paolo Ciacarii Software Architecture CdL M Iformatica Uiversità di Bologa Ageda Cliet server style CS two tiers CS three tiers CS
More informationChapter 8. Strings and Vectors. Copyright 2015 Pearson Education, Ltd.. All rights reserved.
Chapter 8 Strigs ad Vectors Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Overview 8.1 A Array Type for Strigs 8.2 The Stadard strig Class 8.3 Vectors Copyright 2015 Pearso Educatio, Ltd..
More informationCopyright 2016 Ramez Elmasri and Shamkant B. Navathe
Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 26 Ehaced Data Models: Itroductio to Active, Temporal, Spatial, Multimedia, ad Deductive Databases Copyright 2016 Ramez Elmasri ad Shamkat B.
More informationDEFINITION OF CELL BEHAVIOUR. Actions and Behaviour. CELL = a CELL CELL = b CELL
Actios ad Behaviour Let us start to itroduce some modellig laguage features which will allow us to model the behaviour of a cell compoet. Suppose the cell compoet holds a sigle piece of iformatio which
More informationPackage popkorn. R topics documented: February 20, Type Package
Type Pacage Pacage popkor February 20, 2015 Title For iterval estimatio of mea of selected populatios Versio 0.3-0 Date 2014-07-04 Author Vi Gopal, Claudio Fuetes Maitaier Vi Gopal Depeds
More information1.8 What Comes Next? What Comes Later?
35 1.8 What Comes Next? What Comes Later? A Practice Uderstadig Task For each of the followig tables, CC BY Hiroaki Maeda https://flic.kr/p/6r8odk describe how to fid the ext term i the sequece, write
More informationAPPLICATION NOTE. Automated Gain Flattening. 1. Experimental Setup. Scope and Overview
APPLICATION NOTE Automated Gai Flatteig Scope ad Overview A flat optical power spectrum is essetial for optical telecommuicatio sigals. This stems from a eed to balace the chael powers across large distaces.
More informationOutline n Introduction n Background o Distributed DBMS Architecture
Outlie Itroductio Backgroud o Distributed DBMS Architecture Datalogical Architecture Implemetatio Alteratives Compoet Architecture o Distributed DBMS Architecture o Distributed Desig o Sematic Data Cotrol
More informationIXS-6600-C IXS-6700-C
INTEGRATED ROUTING SYSTEM PACK IXS-6600-C IXS-6700-C INTEGRATED ROUTING SYSTEM IXS-6600 IXS-6700 IKS-6030M IKS-A6011 IKS-A6015 IKS-A6050 IKS-A6061 IKS-V6010M IKS-V6010SD IKS-V6050M IKS-V6050SD IKS-V6060M
More informationThreads and Concurrency in Java: Part 1
Cocurrecy Threads ad Cocurrecy i Java: Part 1 What every computer egieer eeds to kow about cocurrecy: Cocurrecy is to utraied programmers as matches are to small childre. It is all too easy to get bured.
More informationChapter 8. Strings and Vectors. Copyright 2014 Pearson Addison-Wesley. All rights reserved.
Chapter 8 Strigs ad Vectors Overview 8.1 A Array Type for Strigs 8.2 The Stadard strig Class 8.3 Vectors Slide 8-3 8.1 A Array Type for Strigs A Array Type for Strigs C-strigs ca be used to represet strigs
More informationOutline. CSCI 4730 Operating Systems. Questions. What is an Operating System? Computer System Layers. Computer System Layers
Outlie CSCI 4730 s! What is a s?!! System Compoet Architecture s Overview Questios What is a?! What are the major operatig system compoets?! What are basic computer system orgaizatios?! How do you commuicate
More informationn n B. How many subsets of C are there of cardinality n. We are selecting elements for such a
4. [10] Usig a combiatorial argumet, prove that for 1: = 0 = Let A ad B be disjoit sets of cardiality each ad C = A B. How may subsets of C are there of cardiality. We are selectig elemets for such a subset
More informationMapReduce and Hadoop. Debapriyo Majumdar Data Mining Fall 2014 Indian Statistical Institute Kolkata. November 10, 2014
MapReduce ad Hadoop Debapriyo Majumdar Data Miig Fall 2014 Idia Statistical Istitute Kolkata November 10, 2014 Let s keep the itro short Moder data miig: process immese amout of data quickly Exploit parallelism
More informationOnes Assignment Method for Solving Traveling Salesman Problem
Joural of mathematics ad computer sciece 0 (0), 58-65 Oes Assigmet Method for Solvig Travelig Salesma Problem Hadi Basirzadeh Departmet of Mathematics, Shahid Chamra Uiversity, Ahvaz, Ira Article history:
More informationThreads and Concurrency in Java: Part 1
Threads ad Cocurrecy i Java: Part 1 1 Cocurrecy What every computer egieer eeds to kow about cocurrecy: Cocurrecy is to utraied programmers as matches are to small childre. It is all too easy to get bured.
More information