1GB Unbuffered DDR SDRAM DIMM

Transcription

1 Description PRELIMINARY DATA SHEET 1GB Unbuffered DDR SDRAM DIMM EBD11UD8ABFB (128M words 64 bits, 2 Banks) The EBD11UD8ABFB is 128M words 64 bits, 2 banks Double Data Rate (DDR) SDRAM unbuffered module, mounted 16 pieces of 512M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe () both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board. Features 184-pin socket type dual in line memory module (DIMM) PCB height: 31.75mm Lead pitch: 1.27mm 2.5V power supply Data rate: 333Mbps/266Mbps (max.) 2.5 V (SSTL_2 compatible) I/O Double Data Rate architecture; two data transfers per clock cycle Bi-directional, data strobe () is transmitted /received with data, to be used in capturing data at the receiver Data inputs and outputs are synchronized with 4 internal banks for concurrent operation (Component) is edge aligned with data for READs; center aligned with data for WRITEs Differential clock inputs (CK and /CK) DLL aligns and transitions with CK transitions Commands entered on each positive CK edge; data referenced to both edges of Auto precharge option for each burst access Programmable burst length: 2, 4, 8 Programmable /CAS latency (CL): 2, 2.5 Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval 2 variations of refresh Auto refresh Self refresh Document No. E0296E20 (Ver. 2.0) Date Published August 2002 (K) Japan URL: Elpida Memory, Inc. 2002

2 Ordering Information Part number EBD11UD8ABFB EBD11UD8ABFB -7A EBD11UD8ABFB -7B Data rate Mbps (max.) Component JEDEC speed bin (CL-tRCD-tRP) DDR333B ( ) DDR266A (2-3-3) DDR266B ( ) Package 184-pin DIMM Contact pad Gold Mounted devices EDD5108ABTA Pin Configurations 1 pin Front side 52 pin 53 pin 92 pin 93 pin 144 pin 145 pin 184 pin Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREF 47 NC 93 VSS 139 VSS A NC 3 VSS 49 NC A VSS 96 VD 142 NC NC 97 0/9 143 VD BA NC 7 VDD VSS VD 100 VSS NC NC NC NC 148 VDD 11 VSS NC 149 4/ VSS 104 VD BA VSS 15 VD / CK1 62 VD 108 VDD 154 /RAS 17 /CK1 63 /WE VSS VD /CAS 111 CKE VSS 112 VD CKE NC 159 5/14 22 VD VSS A VDD 116 VSS NC NC 26 VSS A VD 27 A / VSS 120 VDD

3 Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 29 A7 75 /CK NC 30 VD 76 CK2 122 A8 168 VDD VD /15 32 A VSS A VSS VD VSS NC VDDID 128 VD A / VDD A3 176 VSS VDD / VSS A VSS NC 180 VD 43 A1 89 VSS 135 NC 181 SA0 44 NC 90 NC 136 VD 182 SA1 45 NC 91 SDA 137 CK0 183 SA2 46 VDD 92 SCL 138 /CK0 184 VDDSPD 3

4 Pin Description Pin name A0 to A12 BA0, BA1 0 to 63 /RAS /CAS /WE 0, 1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 0 to 7 0 to 7/9 to 16 SCL SDA SA0 to SA2 VDD VD VDDSPD VREF VSS VDDID NC Function Address input Row address A0 to A12 Column address A0 to A9, A11 Bank select address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for circuit Power for serial EEPROM Input reference voltage Ground VDD identification flag No connection 4

5 Serial PD Matrix Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 1 Number of bytes utilized by module manufacturer Total number of bytes in serial PD device H 128 bytes H 256 bytes 2 Memory type H DDR SDRAM 3 Number of row address DH 13 4 Number of column address BH 11 5 Number of DIMM banks H 2 6 Module data width H 64 7 Module data width continuation H 0 8 Voltage interface level of this assembly H SSTL DDR SDRAM cycle time, CL = H 6.0ns* 1-7A, -7B H 7.5ns* 1 SDRAM access from clock (tac) H 0.7ns* 1-7A, -7B H 0.75ns* 1 11 DIMM configuration type H None. 12 Refresh rate/type H 7.6µs 13 Primary SDRAM width H 8 14 Error checking SDRAM width H None. 15 SDRAM device attributes: Minimum clock delay back-to-back H 1 CLK column access 16 SDRAM device attributes: Burst length supported EH 2,4,8 17 SDRAM device attributes: Number of banks on SDRAM device H 4 18 SDRAM device attributes: /CAS latency CH 2, SDRAM device attributes: latency H 0 20 SDRAM device attributes: /WE latency H 1 21 SDRAM module attributes H Differential Clock 22 SDRAM device attributes: General C0H VDD ± 0.2V Minimum clock cycle time at CL = 2, -7A H 7.5ns* 1-7B A0H 10ns* 1 Maximum data access time (tac) from clock at CL = H 0.7ns* 1-7A, -7B H 0.75ns* 1 25 to H 27 Minimum row precharge time (trp) H 18ns -7A, -7B H 20ns 5

6 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments Minimum row active to row active delay (trrd) H 12ns -7A, -7B CH 15ns Minimum /RAS to /CAS delay (trcd) H 18ns -7A, -7B H 20ns Minimum active to precharge time (tras) AH 42ns -7A, -7B DH 45ns 31 Module bank density H 512M bytes Address and command setup time before clock (tis) H 0.75ns* 1-7A, -7B H 0.9ns* 1 Address and command hold time after clock (tih) H 0.75ns* 1-7A, -7B H 0.9ns* 1 Data input setup time before clock (tds) H 0.45ns* 1-7A, -7B H 0.5ns* 1 Data input hold time after clock (tdh) H 0.45ns* 1-7A, -7B H 0.5ns* 1 36 to 40 Superset information H Future use Active command period (trc) CH 60ns* 1-7A, -7B H 68ns* 1 Auto refresh to active/ Auto refresh command cycle (trfc) H 75ns* 1-7A, -7B BH 75ns* 1 43 SDRAM tck cycle max. (tck max.) H 12ns* Dout to skew DH 450ps* 1-7A, -7B H 500ps* 1 Data hold skew (tqhs) H 550ps* 1-7A, -7B H 750ps* 1 46 to 61 Superset information H Future use 62 SPD Revision H 63 Checksum for bytes 0 to H -7A FCH -7B H 64 to 65 Manufacturer s JEDEC ID code FH Continuation code 6

7 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 66 Manufacturer s JEDEC ID code FEH Elpida Memory 67 to 71 Manufacturer s JEDEC ID code H 72 Manufacturing location (ASCII-8bit code) 73 Module part number H E 74 Module part number H B 75 Module part number H D 76 Module part number H 1 77 Module part number H 1 78 Module part number H U 79 Module part number H D 80 Module part number H 8 81 Module part number H A 82 Module part number H B 83 Module part number H F 84 Module part number H B 85 Module part number DH Module part number H 6-7A, -7B H 7 Module part number -7A H A, -7B H B 88 to 90 Module part number H (Space) 91 Revision code H Initial 92 Revision code H (Space) 93 Manufacturing date 94 Manufacturing date 95 to 98 Module serial number Year code (HEX) Week code (HEX) 99 to 127 Manufacture specific data Note: These specifications are defined based on component specification, not module. 7

8 Block Diagram to to to U1 U11 U3 U10 U2 U12 1 0/9 1/10 2/11 3/12 24 to U13 U4 4/13 32 to to to to U14 U6 U16 U8 U5 U15 U7 U17 5/14 6/15 7/16 * U1 to U8, U10 to U17: 512M bits DDR SDRAM U20: 2k bits EEPROM : 22Ω VDD, VD VREF VSS VDDID open Clock wiring Clock input CK0, /CK0 CK1, /CK1 CK2, /CK2 DDR SDRAMS 4DRAM loads 6DRAM loads 6DRAM loads U1 to U8, U10 to U17 U1 to U8, U10 to U17 U1 to U8, U10 to U17 Note: Wire per Clock loading table/wiring diagrams. A0 to A12 BA0, BA1 SCL /RAS /CAS /WE CKE0 CKE1 3.3Ω A0 to A12 (U1 to U8, U10 to U17) 3.3Ω BA0, BA1 (U1 to U8, U10 to U17) 3.3Ω /RAS (U1 to U8, U10 to U17) 3.3Ω /CAS (U1 to U8, U10 to U17) 3.3Ω /WE (U1 to U8, U10 to U17) CKE (U1, U3, U6, U8, U11, U13, U14, U16) CKE (U2, U4, U5, U7, U10, U12, U15, U17) Serial PD SCL SDA SDA U20 A0 A1 A2 SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. 8

9 Logical Clock Net Structure 6DRAM loads DRAM1 5DRAM loads DRAM1 CLK DIMM connector R = 120Ω DRAM2 DRAM3 DIMM connector R = 120Ω DRAM2 DRAM3 /CLK DRAM4 DRAM5 DRAM5 DRAM6 DRAM6 4DRAM loads DRAM1 3DRAM loads DRAM1 DIMM connector R = 120Ω DRAM2 DIMM connector R = 120Ω DRAM3 DRAM5 DRAM5 DRAM6 2DRAM loads DRAM1 1DRAM loads DIMM connector R = 120Ω DIMM connector R = 120Ω DRAM3 DRAM5 9

10 Electrical Specifications All voltages are referenced to VSS (GND). After power up, wait more than 200 µs and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT 0.5 to +3.6 V Supply voltage relative to VSS VDD, VD 0.5 to +3.6 V Short circuit output current IO 50 ma Power dissipation PD 16 W Operating temperature TA 0 to +70 C 1 Storage temperature Tstg 55 to +125 C Note: DDR SDRAM device specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TA = 0 to +70 C) (DDR SDRAM Device Specification) Parameter Symbol Min Typ Max Unit Notes Supply voltage VDD,VD V 1 VSS V Input reference voltage VREF 0.49 VD 0.50 VD 0.51 VD V Termination voltage VTT VREF 0.04 VREF VREF V Input high voltage VIH (DC) VREF VD V 2 Input low voltage VIL (DC) 0.3 VREF 0.15 V 3 Input voltage level, VIN (DC) 0.3 VD V 4 CK and /CK inputs Input differential cross point VIX (DC) 0.5 VD 0.2V 0.5 VD 0.5 VD + 0.2V V voltage, CK and /CK inputs Input differential voltage, VID (DC) 0.36 VD V 5, 6 CK and /CK inputs Notes: 1. VD must be lower than or equal to VDD. 2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. 3. VIL is allowed to outreach below VSS down to 1.0V for the period shorter than or equal to 5ns. 4. VIN (DC) specifies the allowable dc execution of each differential input. 5. VID (dc) specifies the input differential voltage required for switching. 6. VIH (CK) min assumed over VREF V, VIL (CK) max assumed under VREF 0.18V if measurement. 10

11 DC Characteristics 1 (TA = 0 to 70 C, VDD, VD = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Grade max. Unit Test condition Notes Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) IDD0 IDD1-7A, -7B -7A, -7B ma ma CKE VIH, trc = trc (min.) CKE VIH, BL = 4, CL = 2.5, trc = trc (min.) Idle power down standby current IDD2P 48 ma CKE VIL 4 Floating idle standby current IDD2F -7A, -7B Quiet idle standby current IDD2Q 400 ma Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current ma CKE VIH, VIH,,, = VREF CKE VIH, VIH,,, = VREF IDD3P 320 ma CKE VIL 3 IDD3N IDD4R IDD4W IDD5-7A, -7B -7A, -7B -7A, -7B -7A, -7B Self refresh current IDD6 64 ma Operating current (4 banks interleaving) IDD7A -7A, -7B ma ma ma ma CKE VIH, VIH tras = tras (max.) CKE VIH, BL = 2, CL = 2.5 CKE VIH, BL = 2, CL = 2.5 trfc = trfc (min.), Input VIL or VIH Input VDD 0.2 V Input 0.2 V 1, 2, 9 1, 2, 5 4, 5 4, 10 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6 ma BL = 4 5, 6, 7 Notes. 1. These IDD data are measured under condition that pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one cycle. 6. Data/Data mask transition twice per one cycle banks active. Only one bank is running at trc = trc (min.) 8. The IDD data on this table are measured with regard to tck = tck (min.) in general. 9. Command/Address transition once every two clock cycles. 10. Command/Address stable at VIH or VIL. DC Characteristics 2 (TA = 0 to 70 C, VDD, VD = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol min. max. Unit Test condition Notes Input leakage current ILI µa VDD VIN VSS Output leakage current ILO µa VDD VOUT VSS Output high current IOH 15.2 ma VOUT = 1.95V Output low current IOL 15.2 ma VOUT = 0.35V Pin (TA = 25 C, VDD, VD = 2.5V ± 0.2V) Parameter Symbol Pins max. Unit Notes Input capacitance CI1 Address, /RAS, /CAS, /WE,, CKE Input capacitance CI2 CK, /CK TBD pf Data and input/output capacitance TBD CO, TBD pf pf 11

12 AC Characteristics (TA = 0 to +70 C, VDD, VD = 2.5V ± 0.2V, VSS = 0V) (DDR SDRAM Device Specification) -7A -7B Parameter Symbol min. max. min. max min. max Unit Notes Clock cycle time (CL = 2) tck ns 10 (CL = 2.5) tck ns CK high-level width tch tck CK low-level width tcl tck CK half period output access time from CK, /CK output access time from CK, /CK thp min (tch, tcl) min (tch, tcl) min (tch, tcl) tck tac ns 2, 11 tck ns 2, 11 to skew tq ns 3 / output hold time from tqh thp tqhs thp tqhs thp tqhs ns Data hold skew factor tqhs ns Data-out high-impedance time from CK, /CK Data-out low-impedance time from CK, /CK thz ns 5, 11 tlz ns 6, 11 Read preamble trpre tck Read postamble trpst tck and input setup time tds ns 8 and input hold time tdh ns 8 and input pulse width tdipw ns 7 Write preamble setup time twpres ns Write preamble twpre tck Write postamble twpst tck 9 Write command to first latching transition falling edge to CK setup time falling edge hold time from CK ts tck tdss tck tdsh tck input high pulse width th tck input low pulse width tl tck Address and control input setup time Address and control input hold time Address and control input pulse width Mode register set command cycle time Active to Precharge command period Active to Active/Auto refresh command period tis ns 8 tih ns 8 tipw ns 7 tmrd tck tras ns trc ns 12

13 -7A -7B Parameter Symbol min. max. min. max min. max Unit Notes Auto refresh to Active/Auto refresh command period trfc ns Active to Read/Write delay trcd ns Precharge to active command period Active to auto precharge delay Active to active command period trp ns trap trcd min. trcd min. trcd min. ns trrd ns Write recovery time twr ns Auto precharge write recovery and precharge time tdal Internal write to Read command delay Average periodic refresh interval (twr/tck)+ (trp/tck) (twr/tck)+ (trp/tck) (twr/tck)+ (trp/tck) tck 13 twtr tck tref µs Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see Timing Waveforms section. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. thz is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tlz is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tck (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tck = tck (min.) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tck. 12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. 13. tdal = (twr/tck)+(trp/tck) For each of the terms above, if not already an integer, round to the next highest integer. Example: For 7A Speed at CL = 2.5, tck = 7.5ns, twr = 15ns and trp= 20ns, tdal = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tdal = 5 clocks 13

14 Timing Parameter Measured in Clock Cycle for unbuffered DIMM Number of clock cycle tck 6ns 7.5ns Parameter Symbol min. max. min. max. Write to pre-charge command delay (same bank) twpd 4 + BL/2 3 + BL/2 Read to pre-charge command delay (same bank) trpd BL/2 BL/2 Write to read command delay (to input all data) twrd 2 + BL/2 2 + BL/2 Burst stop command to write command delay (CL = 2) tbstw 2 2 (CL = 2.5) tbstw 3 3 Burst stop command to High-Z (CL = 2) tbstz (CL = 2.5) tbstz Read command to write command delay (to output all data) (CL = 2) trwd 2 + BL/2 2 + BL/2 (CL = 2.5) trwd 3 + BL/2 3 + BL/2 Pre-charge command to High-Z (CL = 2) thzp (CL = 2.5) thzp Write command to data in latency twcd Write recovery time twr 3 2 to data in latency td Mode register set command cycle time tmrd 2 2 Self refresh exit to non-read command tsnr Self refresh exit to read command tsrd Power down entry tpden Power down exit to command input tpdex

15 Pin Functions CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except s, s and s are referred to the cross point of the CK rising edge and the VREF level. When a read operation, s and s are referred to the cross point of the CK and the /CK. When a write operation, s and s are referred to the cross point of the and the VREF level. s for write operation are referred to the cross point of the CK and the /CK. (input pin) When is low, commands and data can be input. When is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via thea0 to the A9 and the A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 BA1 Bank 0 L L Bank 1 H L Bank 2 L H Bank 3 H H Remark: H: VIH. L: VIL. CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tis, at the next CK rising edge CKE level must be kept with proper hold time tih. (input and output pins) Data are input to and output from these pins. (input and output pin) provide the read data strobes (as output) and the write data strobes (as input). 15

16 (input pins): is the reference signal of the data input mask function. s are sampled at the cross point of and VREF VDD and VD (power supply pins) 2.5V is applied. (VDD is for the internal circuit and VD is for the output buffer.) VDDSPD (power supply pin) 2.5V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. Detailed Operation Part, AC Characteristics and Timing Waveforms Refer to the EDD5104ABTA, EDD5108ABTA datasheet (E0237E). 16

17 Physical Outline Unit: mm ± 0.15 (64.48) (DATUM -A-) 4.00 max 2.30 Component area (Front) 4.00 min 1 92 B A 1.27 ± φ 2.50 ± Component area (Back) ± ± 0.10 R min Detail A 2.50 ± typ 0.20 ± 0.15 Detail B 6.62 (DATUM -A-) R ± ± 0.10 Note: Tolerance on all dimensions ± 0.13 unless otherwise specified. ECA-TS

18 CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME

19 The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E