efpgasim Features & Applications

Transcription

1 efpgasim Features & Applications Christian Dufour, Ph.D. Senior Simulation specialist, Power System and Motor Drive Applications OPAL-RT TECHNOLOGIES, Montréal, Canada

2 Presentation objective Introduction to real-time simulation technologies applied to controlled system design Explain efpgasim: a solver suite for the real-time simulation of power electronic systems and converters on FPGAs Demonstrate efpgasim with some client cases

3 Testing and design process of controllers and protections using Model-Based Design Rapid-Control Prototyping to design the control laws. Integration into Production Level Controller (PLC) Integrate and test PLC until release using HIL. Many more tests possible using a virtual plant. Use the same process for all PLC software releases. Real-Time Simulation Requirements Test Offline Simulation Architecture Design Integration Verification HIL HIL: Hardware-In-the-Loop Prototype Concept Assessment Demonstration Manufacture In-service

4 Boehm, Barry. Software Engineering Economics. Englewood Cliffs, NJ: Prentice-Hall, Inc Testing and design process of controllers and protections using Model-Based Design Other benefits: free some costly Dyno time! End objective: Early defect detection and cost savings

5 FOBDP I/Os Controller Advantages of FPGA simulation Excellent resolution for IGBT gating (up to khz) Excellent latency (typ µs) for PWM or direct current-control motor applications (ex: hysteretic ctrl) Notably fast enough to verify Fast On-Board Drive Protections (FOBDP) like IGBT short circuit protection. CPU ALU cores PCIe FPGA Logic & mem bus Real-Time Simulator

6 Disadvantages of FPGA simulation Higher coding complexity than CPU counterparts. User has more control over lower level abstraction levels but this increases the complexity of the designs Many basic CPU coding schemes must be explicited in the FPGA design. Ex: for loops in matrix multiplications Very long compilation time Generating a new FPGA bitstream from FPGA code can take 1-2 hours on big FPGA chips like Virtex-6 or Virtex-7 Increased debugging/probing difficulty Accessing data on the chip is difficult, one may need to recompile the bitstream if a new data is to be probed on the chip

7 General structure of the efpgasim Suite of electric system models and solvers on FPGA Model interconnection and parameters can be changed without re-flashing nor making new FPGA bitstream! Fast iteration of models and design is possible. All models are connected using floating-point format

8 ehs: a user programmable non-flashing FPGA solver for electronic converters Electric Hardware Solver (ehs) enables the simulation of switched electric circuits on FPGA directly from a SimPowerSystems or PLECS model Uses a fixed-admittance matrix nodal method SimPowerSystems or PLECS editor

9 ehs solver principles Fixed Admittance Matrix Nodal Method (FAMNM) All switches in the circuit are modeled as : a capacitor when open (ex: ns) an inductor when closed (ex: ns) If L/h=h/C then the admittance matrix is constant (For Backward Euler method, h is the time step)

10 FPGA user models using RT-XSG Enables the user to code his own model in the Xilinx System Generator blockset for Simulink No VHDL knowledge required

11 Customized solutions in efpgasim Dual-PMSM motor drive with boost converter Application: Hybrid Electric Vehicles Motors with FEA data from JMAG-RT, MotorSolve or Maxwell software

12 PMSM Spatial Harmonic Model Requires the storage of 3-D tables on the FPGA Flux mapping Torque mapping Features: cogging torque, slot induced torque fluctuation, slot effects, saturation, etc

13 Boost converter on FPGA Boost converter was coded on the FPGA using a state-space method Enable to drive the boost converter IGBT up to 50 khz Below we compare real FPGA simulation (captured on Analog Outputs of the MotorHIL) and off-line simulation with 50 khz PWM

14 Customized solutions in efpgasim SRM drive with H-bridge buck-boost converter Application: Hybrid Electric Vehicles Motors with FEA from Infolytica s MotorSolve Multi-core CPU (Intel Core i7) FPGA (Virtex 6) SRM Torque Data High-Level Mechanical system (modeled in Simulink and RTW) SRM Flux Data L -1 (,i abc) CAN I/Os & sig. cond. SG User designed I/O Digital Output (quad enc) Master ECU Battery voltage H-bridge Buck-Boost converter (3-phase shown) SRM Drive L abc rotor i abc (6/4 SRM shown) SRM Motor Analog Output (resolver) Digital Input (5 ns) (IGBT gates) Analog Output (currents) Analog Input (resolver excitation) ECU under test DC-DC PWM khz Internal test modulators SRM controller (hysterisis current type) FPGA (Virtex 6)

15 SRM drive on FPGA SRM inductance data can be obtained from Infolytica s MotorSolve Left: Three-dimensional relationship between excitation current, rotor position and flux linkages for 12/8 SRM motor Right: FEA analysis on the 12/8 SRM in MotorSolve.

16 H-bridge buck-boost converter 120 ns sampling time 100 khz gating frequency H-bridge buck-boost converter DC-DC converter load step. FPGA on-chip results (left) vs. SPS offline simulation (right)

17 ehs design: Matrix Converter Drive - 22 switches in total in the converter - Connected to PMSM on the FPGA - Calculation time on FPGA :0.59 µs 17

18 AD-Drive-eHs01: Matrix Converter Drive Test 1 - ehs Solver accuracy Description Comparison between ehs Solver running on FPGA in realtime versus the same SimPowerSystem model running offline (Tustin solver) with a time step of 500ns. Matrix converter switching frequency : 10 khz Output frequency : 200 Hz Source frequency : 50Hz Conclusion The results obtained in real time using ehs solver and the ML605EX1 FPGA simulator are exactly the same as the results obtained with an SPS offline reference model, using Tustin solver with 500 ns time step. Witch verifies the ehs solver accuracy. The frequency of the output currents and voltage is well regulated to the frequency set point Fref=200Hz. 18

19 FPGA models can be extended to CPU - Complex Active front-end rectifier + 3-level inverters - Using 2 ehs modules on one FPGA + AC-feeder on CPU - If you want a more complex feeder circuit on CPU and use the full simulation power of the OP5600 simulator - Ex: 700 node distribution system on 6 65 µs

20 efpgasim in OP5600 simulator 1 ML605 Xilinx FPGA card for efpgasim models 12-core Intel i7 3.3 GHz real-time simulator I/Os: bit 1 µs Analog Output; bit 2µs Analog Inputs; 128 digital inputs and 128 digital output sampled on the FPGA. Can be extended! Ex: MMC systems with 1000 s of I/Os

21 Summary efpgasim was designed to accelerate user test cycles In particular, we want to avoid very long Place And Route time of modern, large FPGAs Non-flashing, variable parameter and variable topology methodology Do not require advanced FPGA programming skills. efpgasim is a useful tool for control & test engineers Increase test coverage of power electronic systems Early detection of issues in the design process Diminish overall project costs