Implementation of a Low-Cost Real-Time Virtue Test Bed for Hardware-In-The-Loop Testing

Transcription

1 Implementation of a Low-Cost Real-Time Virtue Test Bed for Hardware-In-The-Loop Testing School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332, USA Phone: , Fax: binlu@ece.gatech.edu Abstract Over the years, many real-time systems have been proposed for hardware-in-the-loop (HIL) testing. However, these environments are single platform, single solver, and based on costly commercial products. The high cost of these systems often makes them infeasible in many applications. To provide an efficient solution for HIL testing, a very low-cost, multi-solver, hard real-time simulation environment, the real-time virtual test bed (VTB-RT), has been developed in the University of South Carolina, completely based on open-source software and off-the-shelf hardware. In previous publications, the VTB-RT has already been successfully applied in many fields, such as real-time simulations, power electronics controls, and digital controller designs. This paper presents a detailed but general implementation procedure of the VTB-RT from the software and hardware points of view. The readers could follow this procedure to build the VTB-RT or their own real-time systems. Besides, in this paper the application of the VTB-RT is extended to motor drive systems, which have even higher time critical requirements. For verification purposes, a well-known dc motor drive system is realized using the VTB-RT and the consistency of the experimental results with the theoretical results proves the reliability of the VTB-RT. Index Terms hardware-in-the-loop, real-time simulation, dc motor drive, Virtual Test Bed (VTB), Linux, RTAI, Comedi. Bin Lu, Xin Wu, and Antonello Monti Department of Electrical Engineering University of South Carolina Columbia, SC 29208, USA Phone: , Fax: {wu6, monti}@engr.sc.edu Over the past a few years, the VTB-RT has already been successfully applied in many fields, such as real-time simulations [1], power converters controls [2][3], and digital controller design for fuel-cell applications [4]. Previous publications mainly focused on the control design without providing readers with the details on how to build such a real-time system. [1] has a relatively comprehensive explanation of the VTB-RT, but it does not include the latest development. This paper presents a detailed implementation procedure of the VTB-RT from the software and hardware points of view. More generally, the readers can follow this procedure to build the low-cost hard real-time systems of their own using other simulation solvers and models. Real-time HIL simulation has a wide application, such as power quality disturbances investigation, and modern automotive electronic control unit development. In [2], an efficient real-time HIL testing approach using the VTB-RT for power electronics control system designs is proposed. In this paper, this testing approach is further extended to motor drive systems, which have even higher time critical requirements. For a verification purpose, a well-known dc motor drive system is realized using the VTB-RT. I. INTRODUCTION Real-time Hardware-In-the-Loop (HIL) simulation replaces the emulated hardware under test or control logic in the simulation model with real hardware that interacts with the computer models. This increases the realism of the simulation and provides access to the hardware features currently not available in software-only simulation models, hence reduces the risks of discovering an error in the very last stage of the on-the-field testing [1]-[4]. Many HIL simulation experiments have been proposed in literature [5]-[8]; however, these systems are soft real-time or even non-real-time [5], hardware dependent or based on costly proprietary solutions [6], or supported only by a single platform or solver [7][8]. In order to extend the application of this technology, a very low-cost hard real-time virtue test bed for HIL experiments completely built on open-source software and off-the-shelf hardware is developed by the University of South Carolina [1]-[3]. It is called VTB-RT or RTVTB. In this paper, this system is referred as VTB-RT. The VTB-RT has unique properties such as multi-platform, multi-solver, and hard real-time. Instead of competing with commercial systems, it is designed to provide a very low-cost alternative for real-time HIL applications while maintaining acceptable resolutions. II. VTB-RT ENVIRONMENT The Virtual Test Bed (VTB) is a software environment for prototyping of large-scale, multi-technical dynamic systems [9][10]. It allows proof-testing of new designs prior to hardware construction. The VTB environment supports multi-formalism, multi-platform, multi-solver, highly interactive interface, and high-level visualization. It uses two solvers, the simulated analog computer (SAC) solver and the signal extension resistive companion (SRC) solver. Particularly, the SRC solver supports natural coupling between the simulation models and real hardware. Additionally, it supports signal coupling because of a multi-backplane that allows for mixed-signal simulation. A. VTB-RT Overview In the case that real hardware is involved in the simulation process, the software must deal with additional challenges. These challenges motivate towards the VTB-RT, the real-time extension of the VTB. Hardware-oriented simulation has to deal with more problems than simply software-based simulation, especially the inexorable forward progression of time. This requires the simulation environment to operate in hard real-time mode. The hardware abstraction layer of Windows makes it difficult and /05/$ IEEE 239

2 inefficient to achieve hard real-time. UNIX-like systems such as Linux provide better support for real-time simulation. Therefore, Linux was adopted as the underlying operating system for the VTB-RT. Both the SAC and SRC solvers are transplanted from the VTB to the VTB-RT. The SRC solver enables the natural coupling between VTB-RT and the hardware plant, and thus enables the virtual power exchange between the simulation software and the hardware under test. This greatly extends the design and testing capability of the VTB-RT from mere control system to almost any hardware system. A detailed description of the hard real-time feature of VTB-RT using the SRC solver is given in [3]. B. VTB-RT Components Many systems for HIL simulation have already been developed, such as RT-Lab, RTDS, and HyperSim. However, all of them are based on proprietary solutions. The objective of the VTB-RT is not to compete with these commercial systems, but instead, to provide an extremely low-cost solution for real-time HIL applications, while maintaining acceptable performance. The VTB-RT is completely implemented with open-source software and low-cost off-the-shelf hardware. From the software point of view, the VTB-RT consists of four free software packages: 1) Linux Linux is selected as the operating system of the VTB-RT because of it is open-source with high performance and good real-time support. It provides the user interface, basic functions, and development tools. In the development process of the VTB-RT, various Linux distributions including Mandrake, Redhat, Caldera, and Suse have been demonstrated to be suitable as the operating system [1]. 2) Real-Time Application Interface Hard real-time requires the operating system to be preemptive and deterministic. In the VTB-RT, an open-source package, the Real-Time Application Interface (RTAI), is used to achieve this requirement. The RTAI is a kernel modification and enhancement package of Linux that permits the handling of time-critical tasks. 3) Comedi An HIL simulation system requires I/O interfaces to the hardware. In the VTB-RT, this is achieved by Comedi, freeware that develops open-source device drivers for many different data acquisition (DAQ) devices. It consists of two complementary packages: comedi, which implements the kernel space functionality; and comedilib, which implements the user space access to the device driver functionality. Comedi works with a standard Linux kernel as well as the RTAI. 4) VTB Solvers and Simulation Models The SAC and SRC solvers are used by both the VTB and VTB-RT. The solvers and simulation models are developed using C++ language and the same source codes are shared in these environments. In the VTB-RT, the source codes of the solvers and models need to be recompiled and made compatible with the real-time Linux environment. At this point, the SRC solver is the main solver of the VTB-RT. The application example in section III uses the SRC solver. A complete insight description of the VTB-RT and these four components is available in [1]. More generally, the readers can use Linux, RTAI, Comedi, and their own solvers and models to construct hard real-time simulation systems of their own. C. VTB-RT Configuration The minimum and suggested hardware configurations for the VTB-RT host computer are listed in Table I. The minimum configuration represents the first version of the VTB-RT. The suggested configuration is the one used in [2], which has much better performance. The speed and resolution of VTB-RT can be improved easily by choosing higher level hardware. TABLE I MINIMUM AND SUGGESTED HARDWARE CONFIGURATIONS FOR VTB-RT Minimum configuration Suggested configuration CPU 200MHz 800MHz Hard Drive 2 Gigabytes 10 Gigabytes RAM 64M 128M Video RAM 2M 8M CD ROM No Yes Floppy Drive No Yes Network Yes Yes Free PCI Slots 1 At least 1 I/O DAQ Cards Yes ( ) Yes ( ) : DAQ card should be listed in the Comedi supported hardware list as Appendix B of [1]. Otherwise, Comedi does not support the device and the driver has to be developed individually. The software configuration for the VTB-RT includes the components in section II-B: a clean Linux kernel with an RTAI patch, Comedi drivers, and VTB solvers and models. D. The Installation Procedure of the VTB-RT In the VTB-RT, the software packages have to be installed in the following sequence: Linux, RTAI, Comedi, and the VTB-RT solvers and models. Fig. 1 shows the VTB-RT installation procedure. This installation procedure can be summarized into four major steps: 1. Install any Linux distribution and update a clean RTHAL-enabled generic Linux kernel. This step creates the basic software environment, including user interface and general purpose applications. 2. Install and configure RTAI. This most important step enables the hard real-time capability of the system. 3. Install and configure comedi and comedilib. This step provides the VTB-RT the ability to interface with the real hardware, and thus enables the HIL simulation. 4. Compile VTB solvers and models in the VTB-RT. This last step replicates all the functionality of the VTB into the VTB-RT, including the simulation solvers and models. For simplicity, the detailed information of each block in Fig. 1 is omitted here. They are explained in [1]. 240

3 Fig. 1 Complete installation procedure of the VTB-RT. E. Real-Time Implementation The hard real-time property of the VTB-RT is achieved by three major components: a real-time task, a Linux process, and a real-time first-in-first-out buffer (FIFO). 1) Real-Time Task The RTAI preempts the standard Linux kernel and handles hardware interrupts. In the VTB-RT, a real-time task is generated by the RTAI to manage the 8254 chip (clock generator) to generate a real time clock, which is used as the basis for defining the simulation step. This real-time task is a loadable module in Linux; it stays in the kernel-space upon being loaded. Fig. 2 shows the pseudo code of a typical real-time task. In a typical real-time task as Fig. 2, the following code sections are included: a) RTAI application interface function The application interface between the real-time task and the real-time FIFO is defined in this section. The application task sends a real-time clock message into the FIFO at the beginning of each time step. This message indicates a new simulation time interval for the user-space, where the VTB-RT solver is located. b) Real-time task initialization function A kernel module must contain an init_module( ) function. It is invoked by the insmod command when the module is loaded. It prepares for later invocation of the module s functions. The step size and real-time application task are defined in this section. c) Real-time task cleanup function A cleanup function cleanup_module( ) is also required for the kernel module. It is invoked by the rmmod command when the module is unloaded. It informs the kernel that the module has been removed and none of its functions are called anymore. Fig. 2 Pseudo code of a typical real-time task. 2) Linux Process The VTB-RT solvers are realized by a set of standard Linux processes. They are similar to other Linux programs, such as a text editor. In each step interval, the solver takes in 241

4 the system inputs from the input channels of the DAQ device, solves the system state, and sends the system outputs through the output channels of the DAQ device. The Linux process is a user-space application program and hence has no direct communication with the real-time task. Fig. 3 shows the pseudo code of a typical VTB-RT solver. b) DAQ output function This function sends the output data of the under test system to the output channels of the DAQ device. c) Solver function This function transplants the VTB solver to the Linux environment. It is the heart of the VTB-RT platform. It solves the state of the under test system using the input data and generates the system outputs during each simulation interval. Generally, it could be any solver that the user may be interested in, not limited to the VTB-RT solvers. d) Main program The main program incorporates the previous three functions. It polls the real-time FIFO for the real-time clock update. If an updated real-time clock is detected, it will call the DAQ input function, solver function, and DAQ output function in sequence. 3) Real-Time FIFO Because in the VTB-RT the real-time clock information has to be passed to the solver, a real-time FIFO is applied as the bridge between the real-time task and the Linux process. The real-time FIFO is a uni-directional read/write buffer created by the RTAI. After simulation starts, it continuously records the real-time clock generated by the real-time task. Simultaneously, the Linux process polls the real-time FIFO, detects the real-time clock, and performs the simulation. In terms of the code, the real-time FIFO can be divided into two parts: one part embedded in the real-time task, and the other in the Linux process, as shown in Fig. 2 and Fig. 3. To summarize the VTB-RT real-time implementation, Fig. 4 graphically illustrates the relationship between the previously discussed three major components. Example codes of these components are available in [1]. Fig. 4 Real-time implementation. F. VTB-RT Architecture Fig. 3 Pseudo code of a typical VTB-RT solver. In a typical VTB-RT solver as Fig. 3, the following code sections are included: a) DAQ input function This function reads the input data of the under test system from the input channels of the DAQ device. The architecture of the VTB-RT is shown in Fig. 5. This architecture allows the user to perform a real-time HIL testing of a system that includes real hardware. This testing phase can be considered as the very last step before the real on-line testing of power electronics controls. Through this process the user can verify not only the algorithmic correctness of the system (e.g., a controller) in the simulator, but also its capability to meet the real-time constraints. 242

5 determines the duty ratio of the buck converter, and hence controls the speed of the motor. In this study, a step up speed reference from 0 to 100 rad/s is chosen. As shown in Fig. 7, the whole system is designed and simulated in a non-real-time mode in the VTB. The speed response of the dc motor at a step speed reference is shown in Fig. 8. Fig. 5 The architecture of VTB-RT. In the VTB-RT, the simulation schematics can be created using the VTB schematic editor under a Windows platform. The schematic file format,.vts, is compatible with the VTB-RT under Linux. This enables the user to directly export a simulation from non-real-time platform to hard real-time platform. III. APPLYING VTB-RT INTO DC MOTOR DRIVE SYSTEM In [2], an efficient real-time HIL testing approach using VTB-RT for power electronics control system designs is proposed. This approach is summarized in four steps, as shown in Fig. 6. In this paper, the same testing approach is extended to motor drive systems, which have even higher time critical requirements than power electronics controls. Specifically, a dc motor drive system is studied. For simplicity, only step 1 and step 4 of the design approach are presented in this section. TABLE II RTVTB-RT CONFIGURATIONS Hardware configuration Software configuration CPU Intel PIII 1.26 GHz Linux release Mandrake 9.0 Hard drive 15 Gigabytes Linux kernel RAM 128M SDRAM RTAI Network 100Mbps ether net Comedi I/O DAQ device NI PCI-6070E Comedilib gcc version 3.2 TABLE III PARAMETERS OF THE DC MOTOR Rated input voltage 24 V Terminal resistance 2 Ω Rated output power 70.8 W Input inductance 270 μh No-load speed 5300 rpm Back EMF constant mv/rpm Mechanical time constant 7 ms Rotor inertia 9.063e-4 oz-in-sec 2 Fig. 7. Description of the dc motor drive system in the VTB. Step 1: Non-real-time simulation in VTB or Simulink Step 2 (Optional): Non-real-time co-simulation Step 3: Real-time/Non-real-time distributed Simulation. Step 4: Real-time HIL testing with real hardware. Fig. 6. Design approach of real-time control for a dc motor. A VTB-RT platform is constructed for this experiment following the procedure presented in section II. Its hardware and software configurations are listed in Table II. The motor under study is a Faulhaber 3557K024CR dc motor, with parameters given in Table III. The dc motor drive system is described in Fig. 7. The motor is powered through a buck converter, which has a fixed 100 V input voltage. A proportional-integral (PI) controller Fig. 8. Speed response of the dc motor from the VTB non-real-time simulation, when speed reference steps up from 0 to 100 rad/s. The whole system is then divided into two subsystems: the dc motor subsystem and the controller subsystem. The dc motor subsystem is transplanted into the VTB-RT, as shown in Fig. 9; whereas the controller subsystem is implemented in 243

6 a Xilinx Virtex-II Pro FPGA. The two subsystems interact with each other through DAQ devices. The motor speed response at a step up speed reference (0-127 rad/s) from the real-time HIL simulation is shown in Fig. 10. The speed feedback from the VTB-RT to the FPGA is scaled from rad/s to a voltage in the range of V. Therefore, Fig. 10 shows that the speed of the motor rises from 0 rad/s at the start-up to 100 rad/s at the steady state. Clearly, the agreement between Fig. 8 and Fig. 10 verifies the feasibility of the VTB-RT as a real-time HIL simulation system for this dc motor drive system. Fig. 9. The dc motor subsystem in the VTB-RT. Fig. 10. Speed response of the dc motor from the VTB-RT real-time HIL simulation, when speed reference steps up from 0 to 100 rad/s. IV. CONCLUSIONS The expensive commercial real-time systems are often infeasible in many applications, where cost is in primary concern. The VTB-RT, the real-time extension of the virtue test bed, is designed to be very low-cost, yet capable of yielding comparable performance as the commercial systems. This paper presented a detailed implementation procedure of the VTB-RT from the software and hardware points of view, completely based on open-source software and off-the-shelf hardware. More generally, the readers can follow this procedure to build the low-cost hard real-time systems of their own. Besides, in this paper the VTB-RT is applied into a dc motor drive system. The consistency of the experimental results with the theoretical results proves the feasibility of the VTB-RT. V. ACKNOWLEDGMENT This work was supported in part by the U.S. Office of Naval Research under Grant N and N VI. REFERENCES [1] B. Lu, The real-time extension of the virtual test bed: A multi-solver hard real-time hardware-in-the-loop simulation environment, M.S. thesis, Dept. of Elect. Eng., Univ. of South Carolina, May [2] B. Lu, A. Monti, and R. Dougal, Real-time hardware-in-the-loop testing during design of power electronics controls, in Proc. 29th Annual Conference of the IEEE Industrial Electronics Society (IECON 03), vol. 2, Nov. 2003, pp [3] X. Wu, H. Figueroa, and A. Monti, Testing of digital controllers using real-time hardware in the loop simulation, in Proc. 35th IEEE Power Electronics Specialists Conference (PESC 04), vol. 5, June 2004, pp [4] Z. Jiang, R. Leonard, R. Dougal, H. Figueroa, and A. Monti, Processor-in-the-loop simulation, real-time hardware-in-the-loop testing, and hardware validation of a digitally-controlled, fuel-cell powered battery-charging station, in Proc. 35th IEEE Power Electronics Specialists Conference (PESC 04), vol. 3, June 2004, pp [5] S. Lentijo, A. Monti, E. Santi, C. Welch, and R. Dougal, A new testing tool for power electronic digital control, in Proc. 34th IEEE Power Electronics Specialists Conference (PESC 03), vol. 1, Jun. 2003, pp [6] P. Terwiesch, T. Keller, and E. Scheiben, Rail vehicle control system integration testing using digital hardware-in-the-loop simulation, IEEE Trans. Control System Technology, vol. 3, no. 7, May 1999, pp [7] S. Abourida, C. Dufour, J. Belanger, G. Murere, N. Lechevin, and B. Yu, Real-time PC-based simulator of electric systems and drives, in Proc. 17th IEEE Applied Power Electronics Conference and Exposition (APEC 02), vol.1, March 2002, pp [8] P. Baracos, G. Murere, C. Rabbath, and W. Jin, Enabling pc-based HIL simulation for automotive applications, in Proc IEEE International Electric Machines and Drives Conference (IEMDC 01), June 2001, pp [9] A. Monti, E. Santi, R. Dougal, and M. Riva, Rapid prototyping of digital controls for power electronics, IEEE Trans. Power Electronics, vol. 18, no. 3, May 2003, pp [10] T. Lovett, A. Monti, E. Santi, and R. Dougal, A multilanguage environment for interactive simulation and development controls for power electronics, in Proc. 32th IEEE Power Electronics Specialists Conference (PESC 01), vol. 3, June 2001, pp