Modeling HDL components for FPGAs in control applications

Transcription

1 Modeling HDL components for FPGAs in control applications Mark Corless, Principal Application Engineer, Novi MI 2014 The MathWorks, Inc. 1

2 Position sensing High resolution voltage modulation Critical diagnostics Why would I use an FPGA for a controls application? Low latency control loops System cost reduction FPGA = Field Programmable Gate Array 2

3 How do I get an idea out of my head and into an FPGA? 3

4 How do I get an idea out of my head and into an FPGA? How do I get an idea out of my head and into a microprocessor? 4

5 desktop simulation rapid prototyping production code generation 5

6 That sounds nice, but Show me! 6

7 Begin with existing C component models Current Units Position Velocity Units Mode Scheduler Disabled Open Loop Encoder Calibration Velocity Control Field Oriented Control Voltage Units 7

8 Create new HDL component models C HDL Mode Scheduler Disabled Open Loop Encoder Peripheral Current Units Position Velocity Units HDL = Hardware Description Language Encoder Calibration Velocity Control Field Oriented Control Voltage Units PWM Peripheral 8

9 Migrate some component models from C to HDL C HDL Mode Scheduler Disabled Open Loop Encoder Peripheral Current Units Position Velocity Units Encoder Calibration Velocity Control Field Oriented Control Voltage Units PWM Peripheral 9

10 How did models help us design C components? 10

11 Baseline three-phase motor control hardware setup Simulink Real-Time TM scheduler and peripheral interface FPGA with vendor provided peripherals We will use this for HDL implementation Controller model for C implementation 11

12 Rapid prototyping model with Speedgoat bitstream Controller model for C implementation Field-oriented controller is the fastest loop and runs at 25 khz 12

13 Rapid prototyping model with Speedgoat bitstream Interface block to PWM peripheral on FPGA Interface block to encoder peripheral on FPGA Controller model for C implementation 13

14 Rapid prototyping model with Speedgoat bitstream This is the end result, but it s not where we started 14

15 Simulate design on the desktop We started designing the controller at our desktops Mathematical models of motor, load, and peripherals Controller model for C implementation 15

16 Simulate design on the desktop Lumped parameter model of encoder sensor and peripheral 16

17 Compare desktop simulation and hardware data Correlation of simulation and hardware results provided confidence in the workflow 17

18 How do I create a new HDL component model? 18

19 Begin with existing C component models Current Units Position Velocity Units Mode Scheduler Disabled Open Loop Encoder Calibration Velocity Control Field Oriented Control Voltage Units 19

20 Create new HDL component models C HDL Mode Scheduler Disabled Open Loop Encoder Peripheral Current Units Position Velocity Units Encoder Calibration Velocity Control Field Oriented Control Voltage Units PWM Peripheral 20

21 Example workflow to design an HDL component 1. Design the component with a unit-level testbench 2. Integrate the component with the system-level testbench 3. Partition the design for code generation 4. Generate a bitstream for the FPGA 5. Prototype the design on real-time hardware 21

22 1. Design the component with a unit-level testbench Lo-fidelity model to capture 25 khz dynamics of combined sensor and peripheral Peripheral will run at 33 MHz on the FPGA 22

23 1. Design the component with a unit-level testbench 23

24 1. Design the component with a unit-level testbench 24

25 1. Design the component with a unit-level testbench Simulation results provide confidence in lo-fidelity and implementation fidelity peripheral models 25

26 2. Integrate the component with the system-level testbench Implementation fidelity peripheral models require a 1/33 MHz simulation step size so simulation time will be longer than the testbench with lo-fidelity peripherals 26

27 2. Integrate the component with the system-level testbench Use hi-fidelity peripheral implementation models to confirm integrated behavior Use lo-fidelity peripheral models for interactive control design 27

28 3. Partition the design for code generation Group C components Group HDL components Optionally generate algorithmic HDL code 28

29 4. Generate a bitstream for the FPGA Use HDL Workflow Advisor to specify additional information required to create a bitstream 29

30 4. Generate a bitstream for the FPGA Specify card and FPGA toolchain 30

31 4. Generate a bitstream for the FPGA Associate ports in model with pins on FPGA or PCI interface to processor HDL Workflow Advisor will automate interacting with the Xilinx toolchain to create the bitstream for the FPGA 31

32 4. Generate a bitstream for the FPGA HDL Workflow Advisor also generates an interface block which can be used with Simulink Real-Time 32

33 4. Generate a bitstream for the FPGA We use a MATLAB script to only expose ports of interest and make a prettier mask 33

34 5. Prototype the design on real-time hardware Integrate bitstream interface block into Simulink Real- Time model 34

35 5. Prototype the design on real-time hardware Correlation of simulation and hardware results provides confidence in the workflow 35

36 How do I migrate a component model from C to HDL? 36

37 Migrate some component models from C to HDL C HDL Mode Scheduler Disabled Open Loop Encoder Peripheral Current Units Position Velocity Units Encoder Calibration Velocity Control Field Oriented Control Voltage Units PWM Peripheral 37

38 Migrate some component models from C to HDL C HDL Mode Scheduler Disabled Open Loop Encoder Peripheral Current Units Position Velocity Units Encoder Calibration Velocity Control Field Oriented Control Voltage Units PWM Peripheral 38

39 Example workflow to migrate a component to HDL 1. Design the component with a unit-level testbench 2. Integrate the component with the system-level testbench 3. Partition the design for code generation Modify component to account for differences between C and HDL 4. Generate a bitstream for the FPGA 5. Prototype the design on real-time hardware Model to simplify timing constraints for disparate rates Add timing constraint file to FPGA project 39

40 Modify to account for differences between C and HDL States can be reset through enable or trigger ports States are explicitly reset using signals 40

41 Modify to account for differences between C and HDL Parameters are tunable directly from blocks or data objects Tunable parameters are explicitly routed to ports 41

42 Modify to account for differences between C and HDL Typically floating point for rapid prototyping Typically fixed-point for rapid prototyping 42

43 Model to simplify timing constraints for disparate rates Integrate 25 khz control loop with 33 MHz peripheral components 43

44 Model to simplify timing constraints for disparate rates Insert slow delay at fast to slow rate transitions, this makes it simple to author timing constraint file Example constraint file 44

45 Compare simulation and hardware results Correlation of simulation and hardware results provides confidence in the workflow 45

46 What did we learn? 46

47 Position sensing High resolution voltage modulation Critical diagnostics Models can help you design FPGA components for control applications Low latency control loops System cost reduction 47

48 Through this exercise we learned that C and HDL components often run at disparate rates Design components with similar rates of interest Confirm system level behavior by integrating components Consider low fidelity peripheral models for control design tasks There are some differences when modeling for HDL than C Explicitly reset states and route tunable parameters for HDL Typically model HDL algorithms in fixed-point Consider adding delays to simplify timing constraint specification Overall Model-Based Design is similar for C and HDL Simulate components to reduce dependency on hardware Rapid prototype to verify behavior on hardware Generate algorithm code for integration into production environment 48