Agilent i p Software update. October 9, Santa Clara, CA. October 9, 2008

Transcription

1 Agilent i p Software update Santa Clara, CA

2 What s New in ver 7.20p? VTEP v2.0 Powered! with Cover-Extend Technology (CET) IEEE Solution (Phase 2) Enhancements (including enhanced guarding for VTEP) Many other CR s

3 Our History of Leadership With CET, we re leveraging on our leadership position in 2 of the most important technologies in EMT arena today (Vectorless Test and BScan) and combining the best of both. Cover-Extend Technology 1993 TestJet 2003 VTEP 2006 ivtep 2007 VTEP v2.0 with NPM technology 2008 VTEP v2.0 Powered! with Cover-Extend technology IEEE standard introduced InterconnectPlus Silicon Nails Scanworks Dot6

4 Cover-Extend Technology Hybrid technology between VTEP and Boundary Scan Uses the BScan device as a stimulus to the VTEP sensor Is a limited-access solution because utilizes the TAP pins

5 CET H/W Requirements CET Card Hardware New VTEP mux card (with the VTEP v2.0 Powered! label) USB Interface Kit

6 CET S/W Requirements Software i3070 s/w ver 07.20p and above Production Cover-Extend Technology License InterconnectPlus Boundary Scan License (E1194B) Test Development No special license needed.

7 Coverage Matrix VTEP v2.0 Unpowered/Powered! Devices (ICs) Connectors Sockets VTEP (Enhanced Speed ver 7.10p) (Enhanced Guarding ver 7.20p) ivtep N/A N/A NPM CET

8 Benefits Key benefits : - Test Coverage without Test Access - Lower Cost of Test - Improved Quality Given this criteria, an estimated 10%-20% fixture cost reduction can be realized with ~30% virtual access on a ~2000 node board. From Intel s ITC whitepaper (yet to released) Article

9 IEEE Boundary Scan (Dot6)

10 Why use Dot6? From IEEE Document IEEE Standard for Boundary Scan Testing of Advanced Digital Networks AC-coupled Differential Channel Allows : - Greater noise immunity - Faster transmission - Interfacing of different logic families But, renders the IEEE Boundary Scan ineffective because works in the DC domain.

11 Our Dot6 Coverage Phase 1 (07.10p) - Interconnect Test Phase 2 (07.20p) - Powered shorts, Bus-wire, Connect Test* and Shorted Caps test

12 Requirements Hardware No new hardware required. Software Product No. : i3070 s/w ver 7.10p and above License E1196A : Advanced Boundary Scan - Dot6 requires license - As builds on the capabilities of , users need to have E1194B present in the system for E1196A to work.

13 Cover Extend Technology Overview of Cover-Extend Technology Hardware and software Result

14 The Solution Cover Extend Technology VTEP1 VTEP1 LET s BOUNDARY START WITH SCAN VTEP J1 J1 VTEP 2 VTEP 3 J2 J2 VTEP VTEP4 4 U1 U1 U2 U2 TDI1 TDI1 TDI1 TMS TMS TCK TCK TDO1 TDO1 TDI2 TDI2 Figure 45: ICT Test using Cover-Extend Figure 3 4 ICT Test using Boundary Scan TDO2 TDO2 = ICT Test = ICT Test Probe Probe

15 Cover Extend Hardware Top Cover CET Signal Conditioner Card Daughter card plugs into VTEP Mux Unpowered test VTEP pass through Auxconnect or DUT supply powered CET Card VTEP Mux Board Fixture USB Interface kit Field upgrade kit mounts on ASRU Mint field access Fixturing support USB interface PC Controller USB Kit VTEP ASRU Card auxconnect 5 System card Control XTP Card DUT Supply Pin Cards Medalist i3070

16 Software - Test Development Board Config

17 Board Consultant

18 AUTOMATIC TEST GENERATION Once the library was automatically generated the Cover extend test will be AUTOMATICALLY GENERATED TOO

19 Critical Success Factor Good CET Signal Condition card wiring (Twisted pair). Good VTEP Mux card to VTEP Amplifier (Twisted Pair) Good VTEP to Sensor plate connection (soldering). Ground plane and short wire to ensure stable Boundary Scan operation. Short wire to minimize crosstalk and noise in fixture. This is very important for stable Cover Extend test Proper disabling on upstream devices, Clock and Vreg devices.

20 Cover- Extend Result Cover-Extend Measurement Results on LGA1366 CPU socket With fault injected solder balls.

21 Medalist i p - IEEE Boundary scan Enhancement Quick Boundary Scan review What s new on p software revision? Failure Result on shorted capacitor

22 Medalist i p Software release IEEE Coverage to AC/DC interconnect tests.6.6 TR Also adding Differential pair reporting for.1 nets TR 7.10p interconnect Boundary Scan coverage suite.6.1 TR.6 to.6 AC/DC.6 to.1 DC.1 to.1 DC.1 to.6 DC TR TR

23 What are added in 07.20p License: boundary scan AC interconnect shorted capacitor test u5_u6_sc Powered short test u5_u6_ps_aio Bus Wire test u5_u6_bus_aio

24 Boundary Scan interconnect test IEEE shorted capacitor coverage input cell output cell

25 Config

26 STD_1149_6_2003 location

27 shorted capacitor failure One classy board Mon Aug 18 14:58: u35_u21_sc HAS FAILED Suspect shorted capacitor c25 A short has been detected between the following nodes: ACT_RINGOUT_B_0_P, pins: c25.1 u22.c27 RINGOUT_B_0_P, pins: c25.2 j sb%ringb0p.1 RINGIN_B_0_P, pins: j sb%ringb0p.2 u22.e12 Suspect shorted capacitor c24 A short has been detected between the following nodes: ACT_RINGOUT_B_0_N, pins: c24.1 u22.c28 RINGOUT_B_0_N, pins: c24.2 j sb%ringb0n.1 RINGIN_B_0_N, pins: j sb%ringb0n.2 u22.d

28 Additional 07.20p Enhancements

29 1) New BT-Basic "wsedited function - Enhanced messaging when testplan was edited and not resaved. - Add the following statement in the testplan: if wsedited then print "" print WARNING! print TESTPLAN MODIFIED.." end if wait for start:

30 2) Find Device History Find Device windows can remember previous find components, nodes and etc.

31 3) testplan File name Graphical User Interface File-Open accepts other than testplan file name. Example: testplan_org; testplan_ver1 and etc

32 4)

33 VTEP ENHANCED GUARDING What it does? Enhanced guarding provides an improved guard path (lower impedance) for better VTEP and NPM measurements. Why its important? Some DUTs have devices with pins that are connected through low-valued resistors to a fixed node. When these are guarded during the VTEP test, the small guard path impedance forms voltage dividers that allows the stimulus to leak into the fixed node. These many small signals sum together and causes the reading for the stimulus pin to be higher. This can mask an open. How is it done? A new option is available to close the hybrid card switched ground connections automatically when running a VTEP test. This dramatically reduces the guard path impedance and improves the VTEP reading. The new guarding will not impact throughput and will not cause an unpowered short to system ground error.

34 VTEP ENHANCED GUARDING HOW TO USE IT? Better VTEP measurements for devices with pins connected to a fixed node via a small resistor Fewer escapes Less variation from board to board

35 Throughput Adjustment 4 = Enhanced Guarding Beginning with the 7.20 release: IPG will add default throughput adjustment 4 to new VTEP test sources Autodebug will preserve throughput adjustment 4 but will not add it A customer wanting enhanced guarding can add tpa4 throughput adjustment 4 to the source Throughput adjustment 4 is not used in Cover Extend tests Throughput adjustment 4 is ignored and makes no difference on ivtep Throughput adjustment 4 is important for VTEP and NPM Throughput adjustment 4 is ignored for TestJet

36 TPA0 Slow Mode Testjet Only TPA1 Fast Mode TestJet only TPA2 ivtep Can you still remember throughput adjustment TPA3 modes? Reserved TPA4 Enhanced Guarding

37 TPA4 - FAQ 1. Can I continue to use throughput adjustment (TPA) 0,1 and 2? Ans: Yes, there isn t any changes in use model. 2. What will be the default if I didn t specify any throughput adjustment? Ans: It is still throughput adjustment What throughput adjustment will IPG write as default? Ans: From 07.20, IPG will write throughput adjustment 4 as default. 4. Why there isn t any throughput adjustment 3? Ans: Throughput adjustment 3 is reserved for restricted used (Not for general usage). 5. Can throughput adjustment 4 works with SW Rev 7.1 or lower? Ans: Compiler will compile and ignore the above TPA.

38 Questions and closing comments Evaluation Forms turned in? Have you signed up for webex series training?