The Boundary - Scan Handbook

Transcription

1 The Boundary - Scan Handbook By Kenneth P. Parker Agilent Technologies * KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / London

2 TABLE OF CONTENTS List of Figures xiii List of Tables xvi List of Design-for-Test Rules xvii Preface to the First Edition xxi Preface to the Second Edition xxiii Preface to the Third Edition xxiv Acknowledgement xxvii 1 Boundary-Scan Basics and Vocabulary Digital Test Before Boundary-Scan Edge-Connector Functional Testing In-Circuit Testing The Philosophy of Basic Architecture The TAP Controller The Instruction Register Data Registers The Boundary Register Optimizing a Boundary Register Cell Design Architecture Summary Field-Programmable 1С Devices Boundary-Scan Chains Non-Invasive Operational Modes BYPASS IDCODE USERCODE SAMPLE PRELOAD Pin-Permission Operational Modes EXTEST INTEST RUNBIST HIGHZ CLAMP Exceptions Due to Clocking Extensibility Subordination of IEEE Costs and Benefits Costs Benefits Trends Other Testability Standards 47

3 2 Boundary-Scan Description Language (BSDL) The Scope of BSDL Testing Compliance Assurance Synthesis Structure of BSDL Entity Descriptions Generic Parameter Logical Port Description Standard USE Statement Use Statements Component Conformance Statement Device Package Pin Mappings Grouped Port Identification TAP Port Identification Compliance Enable Description Instruction Register Description Optional Register Description Register Access Description Boundary-Scan Register Description RUNBIST Execution Description INTEST Execution Description User Extensions to BSDL Design Warnings Some advanced BSDL Topics Merged Cells Asymmetrical Drivers BSDL Description of 74BCT Packages and Package Bodies STD_1149_1_ Cell Description Constants Basic Cell Definitions BC_0 to BC_ Cells BC_8 to BC_10 Introduced in User-Defined Boundary Cells Definition of BSDL Extensions Writing BSDL, Summary Boundary-Scan Testing Basic Boundary-Scan Testing The Scanning Sequence Basic Test Algorithm The "Personal Tester" Versus ATE In-Circuit Boundary-Scan С Test 119 Vlll

4 С BIST Testing with Boundary-Scan Chains Chain Integrity Interconnect Test Connection Tests Interaction Tests BIST and Custom Tests Porting Boundary-Scan Tests Boundary-Scan Test Coverage Summary Advanced Boundary-Scan Topics DC Parametric 1С Tests Sample Mode Tests Concurrent Monitoring Non-Scan 1С Testing Non-Digital Device Testing Mixed Digital/Analog Testing Multi-Chip Module Testing Firmware Development Support In-System Configuration Flash Programming Hardware Fault Insertion Power Pin Testing Design for Boundary-Scan Test Integrated Circuit Level DFT TAP Pin Placement Power and Ground Distribution Instruction Capture Pattern Damage Resistant Drivers Output Pins Bidirectional Pins Post-Lobotomy Behavior IDCODEs User-Defined Instructions Creation and Verification of BSDL Board-Level DFT Chain Configurations TCK/TMS Distribution Mixed Logic Families Board Level Conflicts Control of Critical Nodes Power Distribution Boundary-Scan Masters Post-Lobotomy Board Behavior System-Level DFT 197 IX

5 5.3.1 The MultiDrop Problem Coordination with Other Standards Summary Analog Measurement Basics Analog In-Circuit Testing Analog Failures Measuring an Impedance Errors and Corrections Measurement Hardware Limited Access Testing Node Voltage Analysis Testing With Node Voltages Limited Access Node Voltage Testing The Mixed-Signal Test Environment Summary IEEE : Analog Boundary-Scan Vocabulary and Basics The Target Fault Spectrum Extended Interconnect Digital Pins Analog Pins General Architecture of an С Silicon "Switches" The Analog Test Access Port (ATAP) The Test Bus Interface Circuit (TBIC) The Analog Boundary Module (ABM) The Digital Boundary Module (DBM) The Instruction Set The EXTEST Instruction The CLAMP Instruction The HIGHZ Instruction The PROBE Instruction The RUNBIST Instruction The INTEST Instruction Other Provisions of Differential ATAP Port Differential I/O Partitioned Internal Test Buses Specifications and Limits Design for Testability Integrated Circuit Level Board Level System Level Summary 265 x

6 8 IEEE : Testing Advanced I/O The Advanced I/O Problem Traditional Inter-IC Communication Advanced Inter-IC Communication AC Coupled Signal Paths Testing Advanced I/O Vocabulary and Basics Advanced I/O Signal Pin Categories Operational Modes TEST FACILITIES FOR AC PINS Provisions for All Signal Pins Provisions for AC Pin Drivers AC/DC Selection Cells Provisions for AC Pin Receivers The Defect Model for The Test Receiver Test Receiver Definitions Transitions Test Receiver DC Response Test Receiver AC Response Guaranteed AC-Coupling An Integrated AC/DC Test Receiver Initializing and Capturing Hysteretic Memory BSDL Extensions for Boundary Registers Cells for STD_1149_6_ Example Device and BSDL Design for Testability Integrated Circuit Level DFT Board-Level DFT Summary IEEE 1532: In-System Configuration IEEE 1532 Vocabulary and Basics Fixed System Pins ISC System Pins System Modal States System I/O Behavior ISC Pin I/O Cell Design Programming Features of IEEE Core 1532 Programming Instructions Programming a Single, Simple 1532 Device Concurrent Programming of Multiple Devices Design for IEEE 1532 Programmability Epilog: What Next for ,1149.4, and 1532? 341 xi

7 A. BSDL Syntax Specifications 345 A.l Conventions 345 A.2 Lexical elements of BSDL 346 A.3 Notes on syntax definition 349 A.4 BSDL Syntax 351 A.5 User Package Syntax 355 A Extention Attribute Syntax 355 Bibliography 357 Index 365 xii