Boundary-Scan Integration to In-Circuit Test

Transcription

1 Boundary-Scan Integration to In-Circuit Test John Carlos O Farrill, Test Engineer, Jabil Circuit, Inc., Advanced Test Technology Carlos_O Farrill@Jabil.com

2 TOPICS Scope of the Paper The Distinct Advantages of the Integration concept ICT Test Set Maximized and Light The Three Solutions / Case Studies (Exclusive, Non-exclusive, and File conversion) Conclusions

3 SCOPE The scope of this paper is to address standalone boundary-scan test vector integration solutions to In-Circuit Test systems. Three solutions are addressed, and a case study for each solution is presented to demonstrate the integration concept and identify the benefits and limitations of each solution. The boards that were chosen for the case studies were for proof of concept, and may not have followed boundary-scan DFT or Design Guidelines. The scope of this paper is not to debate the benefits of Boundary-scan technology itself, as well as the pricing associated with each solution. (Vendors can provide creative pricing.)

4 The Distinct Advantages of Integration Reuse of known good test vectors: The development of standalone boundary-scan tests at the prototype stage of a product and the implementation of the same tests during the normal production cycle. Reduces test development and debug times, by using known good tests. Assists in identifying areas conducive for test point reduction when applicable. Can lead to faster test implementation times. Utilization of dedicated boundary-scan hardware versus ICT system resources: Can enhance stability of boundary-scan test at ICT by reducing ground bounce. Provides faster TCK clocking speed options than traditional ICT.

5 ICT Test Set Development Maximized and Light Maximized ICT Test Set Conventional development strategy Light ICT Test Set Boundary-Scan test vector reuse strategy

6 Test Set Development for Maximized In-Circuit Test Maximized or traditional ICT test set development, includes as much fault coverage as possible utilizing ICT system resources. This may employ the development of custom component models not supported by the ICT system s standard component library. Other options may include the test system s native boundary-scan tools and supported vectorless test methods. This can result in: Some level of uncertainty for Fault Coverage (until tests are fully validated). Overlapping of Fault Coverage. Increased Test Set costs

7 Test-Set Development for Light In-Circuit Test Light ICT test set development, provides fault coverage only for the components that are not tested via the previously developed boundary-scan tests. Generally, when boundary-scan DFT guidelines are followed, boundary-scan tests can provide fault coverage for a high percentage of the digital devices. Boundary-scan coverage reports will quantify this amount for each device, before ICT is developed. This can result in: Reduced test programming and debug (due to previously developed and validated boundary-scan tests). Reduced overlapping fault coverage Reduced Test Set costs

8 Integration Solution 1 Exclusive Solution 1: The Exclusive Solution This solution requires the installation of a prescribed list of boundary scan hardware and software in a specific ICT system. Benefit: The UUT TAP connections and the boundary-scan test vector integration are automated and accomplished within the ICT development environment. Limitations: One boundary-scan tool set only. One specifically configured ICT system only. Loss of Fault coverage in Shorts Test. Lack of flexibility.

9 Case Study Integration Solution 1, Exclusive UUT Description Unit Under Test Boundary-Scan Coverage: Total Number of Nets % Total Number of Tested Nets % Total Number of Untested Nets % Boundary-scan DFT comments: The UUT has one boundary-scan chain and was designed to achieve high fault coverage. One DFT violation was noted when the TDI TAP pin was found to be connected to a device pin on the scan chain through a series resistor. This was overcome by excluding the device pin in question from the test.

10 Case Study Integration - Solution 1, Exclusive Details / Results Boundary-scan tests were developed during the prototype stage of the UUT. Jabil GTS developed a Light test set allocating tester resources for Nets not fully tested by the standalone boundary-scan tests. Standalone boundary-scan tests were integrated in less than one hour with minimal debug required, with all tests validated and passing. Boundary-scan test fault reporting at the ICT systems was limited to Interconnect tests only.

11 Integration Solution 2 Non-Exclusive Solution 2: The Non-exclusive Solution This solution is not limited to a specific boundary-scan tool set or ICT system. Benefit: Flexibility is the benefit for Solution 2. Limitations: The UUT TAP connections and the test program integration to the ICT system is not fully automated. Loss of Fault coverage in Shorts Test.

12 Case Study Integration - Solution 2, Non- Exclusive UUT Description Unit Under Test Boundary-Scan Coverage Total Number of Nets % Total Number of Tested Nets % Total Number of Untested Nets % Boundary-scan DFT comments: The UUT was designed with four boundary-scan chains however lacked TAP headers for the chains and did not contain a defined power connection. TAP signals TMS and TRST* lacked any termination schemes.

13 Case Study Integration - Solution 2, Non- Exclusive Details / Results Minimal software was developed that allowed the ICT system to communicate with the installed boundary-scan hardware. Four header connectors were designed into the ICT fixture to connect the four UUT TAP s to the boundary-scan hardware. As a result of the boards DFT violations: Initial attempts to test the UUT on the ICT fixture using the original standalone tests vectors were unsuccessful. Boundary-scan tests were redeveloped for each of the four chains. Three out of the four chains tested successfully.

14 Integration - Solution 3, File Conversion Solution 3: File Conversion Method This converts pre-developed boundaryscan test vectors into a target ICT system s file format. Benefit: No hardware prerequisites for ICT implementation. Limitations: Fault reporting does not indicate failing nets or devices, it only displays the vector number where the failure occurred. May hinder test set debug if the converted vectors are unstable when ported to the ICT system. Provides limited guidance for diagnostic technicians. Loss of Fault coverage in Shorts Test.

15 Case Study Integration Solution 3, File Conversion UUT Description Solution 3: Unit Under Test Boundary-Scan Coverage Total Number of Nets % Total Number of Tested Nets % Total Number of Untested Nets % Boundary-scan DFT comments: This UUT was not intended for boundary-scan testing but was chosen due to availability of boards and ICT fixture. This board was chosen for proof of concept.

16 Case Study Integration Solution 3, File Conversion Details / Results Standalone boundary-scan Infrastructure and Interconnects tests were developed and applied to the UUT with all tests passing consistently. The test vectors were converted to Pattern Capture Format (PCF) and applied to the UUT via the ICT fixture which than exhibited unstableness, intermittently passing and failing the Interconnects test. Several unsuccessful attempts were made to stabilize the intermittent test by adjusting the signal timing and voltage threshold. The failing test was never stabilized and further work ceased until UUT net and device pin info can be associated to a failing vector number, thus allowing for debug opportunities.

17 Conclusions The solutions presented cannot be described as fully integrated, since the interaction of allocated ICT system resources in conjunction with the previously developed boundary-scan tests is not supported. Recommendations have been made to the solution vendors with the intent of enhancing the overall performance of the tools thus making them more viable solutions. Solutions 1 and 2 are viable solutions that can: Address designs that have limited access through test point reduction methods. Reduce in-circuit test set development and debug times by reducing requirements for traditional digital device modeling thus leading to faster test turn on times. Provide a more stable boundary-scan test set by reduced ground bounce phenomenon through the use of boundary-scan hardware.

18 Conclusions continued Solution 3 Although it was never proved stable in this case study, due to time constraints, Solution 3 may become a viable solution. In order for this solution to gain wider acceptance, further enhancements are required to: Provide better diagnostic information, (associate a UUT net and device pin to a failing vector) thus allowing more efficient trouble-shooting and test set debugging capabilities.

19 Conclusions continued PROS CONS CONCLUSIONS Exclusive Ease of test integration Lacks flexibility to accommodate multiple test system configurations, requires additional custom hardware for ICT Viable test solution Non-Exclusive Very flexibile, accomodates multiple configurations More dificult to integrate the test, requires the same "standalone" hardware for ICT Viable test solution File Conversion Requires no additional test system hardware Lacks fault & debug resolution Not Viable at this time, but shows potential

20 Questions?