AT25010B, AT25020B, AT25040B

Transcription

1 AT21B, AT22B, AT24B SPI Serial EEPROM 1K (128x8), 2K (26x8), 4K (12x8) DATASHEET Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (1,1) Data Sheet Describes Mode Operation Low-voltage and Standard-voltage Operation V CC = 1.8V to.v 2MHz Clock Rate (V) 8-byte Page Mode Block Write Protection Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Itructio for Both Hardware and Software Data Protection Self-timed Write Cycle (ms max) High Reliability Endurance: 1,, Write Cycles Data Retention: 1 Years Green (Pb/Halogen-free/RoHS Compliant) Packaging Optio Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers Description The Atmel AT21B/2B/4B provides 1,24/2,48/4,96 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 128/26/12 words of 8 bits each. The device is optimized for use in many industrial and commercial applicatio where low-power and low-voltage operation are essential. The AT21B/2B/4B is available in space saving, JEDEC IC, UDFN, TSP, XDFN, and VFBGA packages. The AT21B/2B/4B is enabled through the Chip Select pin () and accessed via a 3-Wire interface coisting of Serial Data Input (), Serial Data Output (), and Serial Clock (). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Block Write protection is enabled by programming the status register with one of four blocks of Write Protection. Separate Program Enable and Program Disable itructio are provided for additional data protection. Hardware Data Protection is provided via the WP pin to protect agait inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.

2 1. Pin Configuratio Table 1-1. Pin Configuratio Pin Name Function 8-lead IC 8-lead TSP GND Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground WP GND Top View V CC HOLD WP GND Top View V CC HOLD V CC WP HOLD Power Supply Write Protect Suspends Serial Input V CC 8-pad UDFN/XDFN 8 1 HOLD 7 2 V CC 8-ball VFBGA 8 1 HOLD WP 6 3 WP 4 GND 4 GND Bottom View Bottom View Note: Drawings are not to scale. 2. Absolute Maximum Ratings* Operating Temperature C to + 12 C Storage Temperature C to + 1 C Voltage on any pin with respect to ground v to + 7V Maximum Operating Voltage V DC Output Current ma *Notice: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. 2 AT21B/2B/4B [DATASHEET]

3 3. Block Diagram Figure 3-1. Block Diagram V CC Status Register Memory Array 128/26/12 x 8 Address Decoder Data Register Mode Decode Logic Output Buffer Clock Generator AT21B/2B/4B [DATASHEET] 3

4 4. Electrical Characteristics 4.1 Pin Capacitance Table 4-1. Pin Capacitance (1) Applicable over recommended operating range from T A = 2 C, f = 1MHz, V CC = +V (unless otherwise noted). Symbol Test Conditio Max Units Conditio C OUT Output Capacitance () 8 pf V OUT = V C IN Input Capacitance (,,, WP, HOLD) 6 pf V IN = V Note: 1. This parameter is characterized and is not 1% tested. 4.2 DC Characteristics Table 4-2. DC Characteristics Applicable over recommended operating range from: T AI = -4 C to +8 C, V CC = +1.8V to +.V, (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units V CC1 Supply Voltage 1.8. V V CC2 Supply Voltage 2.. V V CC3 Supply Voltage 4.. V I CC1 Supply Current V CC = V at 2MHz = Open, Read 8. 1 ma I CC2 Supply Current V CC = V at 1MHz = Open, Read, Write 4. ma I CC3 Supply Current V CC = V at 1MHz = Open, Read, Write 2 3 ma I SB1 Standby Current V CC = 1.8V, = V CC.1. μa I SB2 Standby Current V CC = 2.V, = V CC.2 1 μa I SB3 Standby Current V CC = V, = V CC 2 3. μa I IL Input Leakage V IN = V to V CC 3 μa I OL Output Leakage V IN = V to V CC T AC = C to 7 C 3 3 μa V IL (1) V IH (1) Input Low-voltage.6 V CC x.3 V Input High-voltage V CC x.7 V CC +. V V OL1 Output Low-voltage 3.6V V CC.V I OL = 3mA.4 V V OH1 Output High-voltage 3.6V V CC.V I OH = 1.6mA V CC.8 V V OL2 Output Low-voltage 1.8V V CC 3.6V I OL =.1mA.2 V V OH2 Output High-voltage 1.8V V CC 3.6V I OH = 1μA V CC.2 V Note: 1. V IL min and V IH max are reference only and are not tested. 4 AT21B/2B/4B [DATASHEET]

5 4.3 AC Characteristics Table 4-3. AC Characteristics Applicable over recommended operating range from T AI = -4 to +8 C, V CC = As Specified, CL = 1 TTL Gate and 3pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units f Clock Frequency MHz t RI Input Rise Time μs t FI Input Fall Time μs t WH High Time t WL Low Time t High Time t S Setup Time t H Hold Time t SU Data In Setup Time t H Data In Hold Time t HD Hold Setup Time t CD Hold Hold Time t V Output Valid t HO Output Hold Time AT21B/2B/4B [DATASHEET]

6 Table 4-3. AC Characteristics (Continued) Applicable over recommended operating range from T AI = -4 to +8 C, V CC = As Specified, CL = 1 TTL Gate and 3pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units t LZ Hold to Output Low Z t HZ Hold to Output High Z t DIS Output Disable Time t WC Write Cycle Time ms Endurance (1) V, 2 C, Page Mode 1,, Write Cycles Note: 1. This parameter is characterized and is not 1% tested.. Serial Interface Description Master: The device that generates the serial clock. Slave: Because the Serial Clock pin () is always an input, the AT21B/2B/4B always operates as a slave. Tramitter/Receiver: The AT21B/2B/4B has separate pi designated for data tramission () and reception (). MSB: The Most Significant Bit (MSB) is the first bit tramitted and received. Serial Opcode: After the device is selected with going low, the first byte will be received. This byte contai the opcode which defines the operatio to be performed. The opcode also contai address bit A8 in both the read and write itructio for the AT24B. Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT21B/2B/4B, and the serial output pin () will remain in a high-impedance state until the falling edge of is detected again. This will reinitialize the serial communication. Chip Select: The AT21B/2B/4B is selected when the pin is low. When the device is not selected, data will not be accepted via the pin, and the pin will remain in a high impedance state. Hold: The HOLD pin is used in conjunction with the pin to select the AT21B/2B/4B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the pin is low. To resume serial communication, the HOLD pin is brought high while the pin is low ( may still toggle during HOLD). Inputs to the pin will be ignored while the pin is in the high impedance state. Write Protect: The write protect pin (WP) will allow normal read/write operatio when held high. When the WP pin is brought low, all write operatio are inhibited. WP going low while is still low will interrupt a write to the AT21B/2B/4B. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation. 6 AT21B/2B/4B [DATASHEET]

7 Figure -1. SPI Serial Interface Master: Microcontroller Data Out (MO) Data In (MI) Serial Clock (SPI CK) SS SS1 SS2 SS3 Slave: AT21B/2B/4B AT21B/2B/4B [DATASHEET] 7

8 6. Functional Description The AT21B/2B/4B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 68 and 68HC11 series of microcontrollers. The AT21B/2B/4B utilizes an 8-bit itruction register. The list of itructio and their operation codes are contained in Figure 6-1. All itructio, addresses, and data are traferred with the MSB first and start with a high-to-low traition. Table 6-1. Itruction Set for the AT21B/2B/4B Itruction Name Itruction Format Operation WREN X11 Set Write Enable Latch WRDI X1 Reset Write Enable Latch RDSR X11 Read Status Register WRSR X1 Write Status Register READ A11 Read Data from Memory Array WRITE A1 Write Data to Memory Array Note: 1. A represents MSB address bit A8 for the AT24B. Write Enable (WREN): The device will power-up in the Write Disable state when V CC is applied. All programming itructio must therefore be preceded by a Write Enable itruction. The WP pin must be held high during a WREN itruction. Write Disable (WRDI): To protect the device agait inadvertent writes, the Write Disable itruction disables all programming modes. The WRDI itruction is independent of the status of the WP pin. Read Status Register (RDSR): The Read Status Register itruction provides access to the status register. The Read/Busy and Write Enable status of the device can be determined by the RDSR itruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR itruction. Table 6-2. Status Register Format Bit 7 Bit 6 Bit Bit 4 Bit 3 Bit 2 Bit 1 Bit X X X X BP1 BP WEN RDY Table 6-3. Bit Bit (RDY) Bit 1 (WEN) Read Status Register Bit Definition Definition Bit = (RDY) indicates the device is ready. Bit = 1 indicates the write cycle is in progress. Bit 1 = indicates the device is not write enabled. Bit 1 = 1 indicates the device is write enabled. Bit 2 (BP) See Table 6-4. Bit 3 (BP1) See Table 6-4. Bits 4 7 are zeros when device is not in an internal write cycle. Bits 7 are ones during an internal write cycle. 8 AT21B/2B/4B [DATASHEET]

9 Write Status Register (WRSR): The WRSR itruction allows the user to select one of four levels of protection. The AT21B/2B/4B is divided into four array segments. None, one-quarter (¼), one-half (½), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read-only. The block write protection levels and corresponding status register control bits are shown in Table 6-4. Bits BP1 and BP are nonvolatile cells that have the same properties and functio as the regular memory cells (e.g., WREN, t WC, RDSR). Table 6-4. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BP AT21B AT22B AT24B None None None 1 (¼) 1 6 7F C FF 18 FF 2 (½) 1 4 7F 8 FF 1 1FF 3 (All) 1 1 7F FF 1FF Read Sequence (READ): Reading the AT21B/2B/4B via the pin requires the following sequence. After the line is pulled low to select a device, the Read opcode (including A8 for the AT24B) is tramitted via the line followed by the byte address to be read (A7 A). Upon completion, any data on the line will be ignored. The data (D7 D) at the specified address is then shifted out onto the line. If only one byte is to be read, the line should be driven high after the data comes out. The Read Sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll-over to the lowest address allowing the entire memory to be read in one continuous read cycle. Write Sequence (WRITE): In order to program the AT21B/2B/4B, the Write Protect pin (WP) must be held high and two separate itructio must be executed. First, the device must be write enabled via the WREN itruction. Then a Write (WRITE) itruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection level. During an internal write cycle, all commands will be ignored except the RDSR itruction. A Write itruction requires the following sequence. After the line is pulled low to select the device, the Write opcode (including A8 for the AT24B) is tramitted via the line followed by the byte address (A7 A) and the data (D7 D) to be programmed. Programming will start after the pin is brought high. The low-to-high traition of the pin must occur during the low time immediately after clocking in the D (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) itruction. If Bit = 1, the write cycle is still in progress. If Bit =, the write cycle has ended. Only the RDSR itruction is enabled during the write programming cycle. The AT21B/2B/4B is capable of an 8-byte Page Write operation. After each byte of data is received, the three low-order address bits are internally incremented by one; the six high-order bits of the address will remain cotant. If more than eight bytes of data are tramitted, the address counter will roll-over and the previously written data will be overwritten. The AT21B/2B/4B is automatically returned to the Write Disable state at the completion of a write cycle. Note: If the WP pin is brought low or if the device is not Write Enabled (WREN), the device will ignore the Write itruction and will return to the standby state, when is brought high. A new falling edge is required to reinitiate the serial communication. AT21B/2B/4B [DATASHEET] 9

10 7. Timing Diagrams Figure 7-1. Synchronous Data Timing (for Mode ) V IH V IL t t S t H V IH t WH t WL V IL t SU t H V IH V IL Valid In t V t HO t DIS V OH HI-Z HI-Z V OL Figure 7-2. WREN Timing WREN Opcode HI-Z Figure 7-3. WRDI Timing WRDI Opcode HI-Z 1 AT21B/2B/4B [DATASHEET]

11 Figure 7-4. RDSR Timing Itruction High-impedance MSB Data Out Figure 7-. WRSR Timing Data In Itruction High-impedance Figure 7-6. READ Timing Itruction 8 9 th bit of Address Byte Address High-impedance Data Out MSB AT21B/2B/4B [DATASHEET] 11

12 Figure 7-7. WRITE Timing Itruction Byte Address Data In th bit of Address High-impedance Figure 7-8. HOLD Timing t CD t CD HOLD t HD t HD t HZ t LZ 12 AT21B/2B/4B [DATASHEET]

13 8. Ordering Code Detail AT21B-SSHL-B Atmel Designator Product Family 2 = Standard SPI Serial EPPROM Device Deity 1 = 1k 2 = 2k 4 = 4k Device Revision Shipping Carrier Option B = Bulk (Tubes) T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity Option Operating Voltage M = 1.8V to.v Package Device Grade or Wafer/Die Thickness H = Green, NiPdAu Lead Finish, Industrial Temperature Range (-4 C to +8 C) U = Green, Matte Sn Lead Finish, Industrial Temperature Range (-4 C to +8 C) 11 = 11mil Wafer Thickness Package Option SS = JEDEC IC X = TSP MA = UDFN ME = XDFN C = VFBGA WWU = Wafer uawn WDT = Die in Tape and Reel AT21B/2B/4B [DATASHEET] 13

14 9. Part Markings AT21B, AT22B and AT24B: Package Marking Information 8-lead IC 8-lead TSP 8-pad UDFN 2. x 3. mm Body ATMLHYWW AAAAAAAA ATHYWW AAAAAAA ### H%@ YXX 8-ball VFBGA 1. x 2. mm Body 8-pad XDFN 1.8 x 2.2 mm Body ###U YMXX ### YXX PIN 1 Note 1: designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT21B Truncation Code ###: 1B AT22B Truncation Code ###: 2B AT24B Truncation Code ###: 4B Date Codes Voltages Y = Year M = Month WW = Work Week of Assembly % = Minimum Voltage 4: 214 8: 218 A: January 2: Week 2 L: 1.8V min : 21 9: 219 B: February 4: Week 4 6: 216 : : 217 1: 221 L: December 2: Week 2 Country of Assembly Lot Number Grade/Lead Finish = Country of Assembly AAA...A = Atmel Wafer Lot Number H: Industrial/NiPdAu U: Industrial/Matte Tin/SnAgCu Trace Code XX = Trace Code (Atmel Lot Numbers Correspond to Code) Example: AA, AB... YZ, ZZ Atmel Truncation AT: Atmel ATM: Atmel ATML: Atmel 1/1/14 TITLE DRAWING NO. REV. Package Mark Contact: DL-O-Assy_eng@atmel.com BSM, AT21B, AT22B and AT24B Package Marking Information BSM B 14 AT21B/2B/4B [DATASHEET]

15 1. Ordering Information Atmel Ordering Code Lead Finish Package Delivery Information Form Quantity Operation Range AT21B-SSHL-B Bulk (Tubes) 1 per Tube 8S1 AT21B-SSHL-T Tape and Reel 4, per Reel AT21B-XHL-B Bulk (Tubes) 1 per Tube AT21B-XHL-T NiPdAu 8X (Lead-free/Halogen-free) Tape and Reel, per Reel AT21B-MAHL-T Tape and Reel, per Reel 8MA2 AT21B-MAHL-E Tape and Reel 1, per Reel Industrial Temperature (-4 to 8 C) AT21B-MEHL-T 8ME1 Tape and Reel, per Reel AT21B-CUL-T SnAgCu (Lead-free/Halogen-free) 8U3-1 Tape and Reel, per Reel AT21B-WWU11L (1) N/A Wafer Note 1 AT22B-SSHL-B Bulk (Tubes) 1 per Tube 8S1 AT22B-SSHL-T Tape and Reel 4, per Reel AT22B-XHL-B Bulk (Tubes) 1 per Tube AT22B-XHL-T NiPdAu 8X (Lead-free/Halogen-free) Tape and Reel, per Reel AT22B-MAHL-T Tape and Reel, per Reel 8MA2 AT22B-MAHL-E Tape and Reel 1, per Reel Industrial Temperature (-4 to 8 C) AT22B-MEHL-T 8ME1 Tape and Reel, per Reel AT22B-CUL-T SnAgCu (Lead-free/Halogen-free) 8U3-1 Tape and Reel, per Reel AT22B-WWU11L (1) N/A Wafer Note 1 AT24B-SSHL-B Bulk (Tubes) 1 per Tube 8S1 AT24B-SSHL-T Tape and Reel 4, per Reel AT24B-XHL-B Bulk (Tubes) 1 per Tube AT24B-XHL-T NiPdAu 8X (Lead-free/Halogen-free) Tape and Reel, per Reel AT24B-MAHL-T Tape and Reel, per Reel 8MA2 AT24B-MAHL-E Tape and Reel 1, per Reel Industrial Temperature (-4 to 8 C) AT24B-MEHL-T 8ME1 Tape and Reel, per Reel AT24B-CUL-T SnAgCu (Lead-free/Halogen-free) 8U3-1 Tape and Reel, per Reel AT24B-WWU11L (1) N/A Wafer Note 1 Note: 1. Contact Atmel Sales for Wafer sales. AT21B/2B/4B [DATASHEET] 1

16 Package Type 8S1 8X 8MA2 8ME1 8-lead,.1" wide, Plastic Gull Wing Small Outline (JEDEC IC) 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline Package (TSP) 8-pad, 2.mm x 3.mm body,.mm pitch, Plastic Ultra Thin Dual Flat No Lead (UDFN) 8-pad, 1.8mm x 2.2mm body,.4mm pitch, Extra Thin Dual Flat No Lead (XDFN) 8U3-1 8-ball, 1.mm x 2.mm body,.mm pitch, Die Ball Grid Array (VFBGA) 16 AT21B/2B/4B [DATASHEET]

17 11. Packaging Information S1 8-lead JEDEC IC C 1 E E1 N L TOP VIEW Ø END VIEW e b A COMMON DIMENONS (Unit of Measure = mm) A1 SYMBOL MIN NOM MAX NOTE A A1.1.2 b.31.1 C.17.2 D DE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-12, Variation AA for proper dimeio, tolerances, datums, etc. D 4.8. E E e 1.27 BSC L Ø 8 6/22/11 TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com 8S1, 8-lead (.1 Wide Body), Plastic Gull Wing Small Outline (JEDEC IC) SWB 8S1 G AT21B/2B/4B [DATASHEET] 17

18 11.2 8X 8-lead TSP 1 C Pin 1 indicator this corner E1 E L1 Top View b N A End View L A1 Notes: D e Side View 1. This drawing is for general information only. Refer to JEDEC Drawing MO-13, Variation AA, for proper dimeio, tolerances, datums, etc. 2. Dimeion D does not include mold Flash, protrusio or gate burrs. Mold Flash, protrusio and gate burrs shall not exceed.1mm (.6in) per side. 3. Dimeion E1 does not include inter-lead Flash or protrusio. Inter-lead Flash and protrusio shall not exceed.2mm (.1in) per side. 4. Dimeion b does not include Dambar protrusion. Allowable Dambar protrusion shall be.8mm total in excess of the b dimeion at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is.7mm.. Dimeion D and E1 to be determined at Datum Plane H. A2 COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A A A D , E 6.4 BSC E , b e.6 BSC L L1 1. REF C /27/14 TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com 8X, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSP) TNR 8X E 18 AT21B/2B/4B [DATASHEET]

19 11.3 8MA2 8-pad UDFN E 1 Pin 1 ID D 4 TOP VIEW C A2 A DE VIEW A1 E2 b (8x) 8 1 Notes: e (6x) 7 6 L (8x) Pin#1 ID BOTTOM VIEW 1. This drawing is for general information only. Refer to Drawing MO-229, for proper dimeio, tolerances, datums, etc. 2. The Pin #1 ID is a laser-marked feature on Top View. 3. Dimeio b applies to metallized terminal and is measured between.1 mm and.3 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimeion should not be measured in that radius area. 4. The Pin #1 ID on the Bottom View is an orientation feature on the thermal pad K D2 COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A...6 A1..2. A D D E E b C 1.2 REF L e. BSC K /26/14 Package Drawing Contact: packagedrawings@atmel.com TITLE 8MA2, 8-pad 2 x 3 x.6mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No-Lead Package (UDFN) GPC YNZ DRAWING NO. 8MA2 REV. G AT21B/2B/4B [DATASHEET] 19

20 11.4 8ME1 8-pad XDFN 8 7 D 6 PIN #1 ID E A1 Top View A e1 b Side View L COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE PIN #1 ID.1 A A D E e b b e e TYP 1.2 REF.2 End View L /1/212 Package Drawing Contact: packagedrawings@atmel.com TITLE 8ME1, 8-pad (1.8mm x 2.2mm body) Extra Thin DFN (XDFN) GPC DRAWING NO. REV. DTP 8ME1 B 2 AT21B/2B/4B [DATASHEET]

21 11. 8U3-1 8-ball VFBGA E D 2. b PIN 1 BALL PAD CORNER A1 TOP VIEW A2 A PIN 1 BALL PAD CORNER DE VIEW d Notes: 8 1. This drawing is for general information only. 2. Dimeion b is measured at maximum solder ball diameter. 3. Solder ball composition shall be 9.Sn-4.Ag-.Cu. 7 6 (e1) e BOTTOM VIEW 8 LDER BALLS (d1) COMMON DIMENONS (Unit of Measure - mm) SYMBOL MIN NOM MAX NOTE A A A b D 1. BSC E 2. BSC e. BSC e1.2 REF d 1. BSC d1.2 REF 6/11/13 Package Drawing Contact: packagedrawings@atmel.com TITLE 8U3-1, 8-ball, 1.mm x 2.mm body,.mm pitch, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GPC GXU DRAWING NO. REV. 8U3-1 F AT21B/2B/4B [DATASHEET] 21

22 12. Revision History Doc. Rev. Date Comments 877F 1/21 877E / D 4/ C 6/211 Add the UDFN Expanded Quantity Option. Update the 8MA2 package outline drawing and the ordering information section. Update part markings, package drawings, package 8A2 to 8X, template, logos, and disclaimer page. No change to functional specification. Correct WRSR waveform figure 4-, bit 7 is not writable. Update Atmel logos and disclaimer page. Correct AT24B-SSHL marking detail. Replace 8A2 package drawing with version E. 877B 1/21 Remove Preliminary. 877B 3/21 Replace 8Y6 with 8MA2. 877A 2/21 Initial document release. 22 AT21B/2B/4B [DATASHEET]

23 X X X X X X Atmel Corporation 16 Technology Drive, San Jose, CA 911 USA T: (+1)(48) F: (+1)(48) Atmel Corporation. / Rev.:. Atmel, Atmel logo and combinatio thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No licee, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBTE, ATMEL ASSUMES NO LIABILITY WHATEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUNESS INTERRUPTION, OR LOSS OF INFORMATION) ARING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSBILITY OF SUCH DAMAGES. Atmel makes no representatio or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specificatio and products descriptio at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applicatio. Atmel products are not intended, authorized, or warranted for use as components in applicatio intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applicatio where the failure of such products would reasonably be expected to result in significant personal injury or death ( Safety-Critical Applicatio ) without an Atmel officer's specific written coent. Safety-Critical Applicatio include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapo systems. Atmel products are not designed nor intended for use in military or aerospace applicatio or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applicatio unless specifically designated by Atmel as automotive-grade.