AT25320B and AT25640B

Transcription

1 ATB and AT64B SPI Serial EEPROM Kb (496 x 8) and 64Kb (89 x 8) DATASHEET Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and (,) Datasheet Describes Mode Operation Low-voltage and standard-voltage Operation.8V (V CC =.8V to.v) MHz Clock Rate (V) -byte Page Mode Block Write Protection Protect /4, /, or Entire Array Write Protect (WP) Pin and Write Disable Itructio for Both Hardware and Software Data Protection Self-timed Write Cycle (ms Max) High Reliability Endurance:,, Write Cycles Data Retention: Years Green (Pb/Halide-free/RoHS Compliant) Packaging Optio Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers Description The Atmel ATB/64B provides,768-/6,6-bits of Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM) organized as 4,96/8,9 words of 8 bits each. The device is optimized for use in many industrial and commercial applicatio where low-power and low-voltage operation are essential. The ATB/64B is available in space-saving 8-lead JEDEC IC, 8-lead TSP, 8-lead UDFN, 8-lead XDFN, and 8-ball VFBGA packages. The ATB/64B is enabled through the Chip Select pin () and accessed via a -wire interface coisting of Serial Data Input (), Serial Data Output (), and Serial Clock (). All programming cycles are completely self-timed, and no separate erase cycle is required before Write. Block Write Protection is enabled by programming the status register with one of four blocks of write protection. Separate Program Enable and Program Disable itructio are provided for additional data protection. Hardware data protection is provided via the WP pin to protect agait inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.

2 . Pin Configuratio and Pinouts Table -. Pin Configuratio Pin Name Function Chip Select Serial Data Clock WP GND 8-lead IC V CC HOLD WP GND 8-lead TSP V CC HOLD Serial Data Input Top View Top View Serial Data Output GND V CC WP Ground Power Supply Write Protect V CC 8 HOLD pad UDFN 4 WP GND V CC 8 HOLD pad XDFN 4 WP GND HOLD Suspends Serial Input Bottom View Bottom View 8-ball VFBGA V CC HOLD WP GND Bottom View Note: Drawings are not to scale.. Absolute Maximum Ratings* Operating Temperature C to + C Storage Temperature C to + C Voltage on Any Pin with Respect to Ground V to +7.V Maximum Operating Voltage V DC Output Current mA *Notice: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability.

3 . Block Diagram Figure -. Block Diagram V CC GND Status Register Memory Array 4,96/8,9 x 8 Address Decoder WP Data Register Mode Decode Logic Output Buffer Clock Generator HOLD

4 4. Electrical Characteristics 4. Pin Capacitance Table 4-. Pin Capacitance () Applicable over recommended operating range from T A = C, f =.MHz, V CC =.V (unless otherwise noted). Symbol Test Conditio Max Units Conditio C OUT Output Capacitance () 8 pf V OUT = V C IN Input Capacitance (,,, WP, HOLD) 6 pf V IN = V Note:. This parameter is characterized and is not % tested. 4. DC Characteristics Table 4-. DC Characteristics Applicable over recommended operating range from: T AI = -4 C to +8 C, V CC =.8V to.v (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units V CC Supply Voltage.8. V V CC Supply Voltage.. V V CC Supply Voltage 4.. V I CC Supply Current V CC =.V at MHz, = Open, Read 7.. ma I CC Supply Current V CC =.V at MHz, = Open, Read, Write 4.. ma I CC Supply Current V CC =.V at MHz, = Open, Read, Write ma I SB Standby Current V CC =.8V, = V CC <. 6. () μa I SB Standby Current V CC =.V, = V CC. 7. () μa I SB Standby Current V CC =.V, = V CC.. () μa I IL Input Leakage V IN = V to V CC -.. μa I OL Output Leakage V IN = V to V CC, T AC = C to 7 C -.. μa V IL () V IH () Input Low-voltage -.6 V CC x. V Input High-voltage V CC x.7 V CC +. V V OL Output Low-voltage I OL =.ma.4 V.6V V CC.V V OH Output High-voltage I OH = -.6mA V CC -.8 V V OL Output Low-voltage I OL =.ma. V.8V V CC.6V V OH Output High-voltage I OH = μa V CC -. V Notes:. V IL min and V IH max are reference only and are not tested.. Worst case measured at 8 C. 4

5 4. AC Characteristics Table 4-. AC Characteristics Applicable over recommended operating range from T AI = -4 C to +8 C, V CC = As Specified, CL = TTL Gate and pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units f Clock Frequency MHz t RI Input Rise Time μs t FI Input Fall Time μs t WH High Time 4 8 t WL Low Time 4 8 t High Time t S Setup Time t H Hold Time t SU Data In Setup Time t H Data In Hold Time t HD HOLD Setup Time t CD HOLD Hold Time t V Output Valid 4 8 t HO Output Hold Time

6 Table 4-. AC Characteristics (Continued) Applicable over recommended operating range from T AI = -4 C to +8 C, V CC = As Specified, CL = TTL Gate and pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units t LZ HOLD to Output Low Z t HZ HOLD to Output High Z 4 8 t DIS Output Disable Time 4 8 t WC Write Cycle Time ms Endurance ().V, C, Page Mode,, Write Cycles Note:. This parameter is characterized and is not % tested.. Serial Interface Description Master: The device that generates the serial clock. Slave: Because the Serial Clock pin () is always an input, the ATB/64B always operates as a slave. Tramitter/receiver: The ATB/64B has separate pi designated for data tramission () and reception (). MSB: The Most Significant Bit (MSB) is the first bit tramitted and received. Serial Opcode: After the device is selected with going low, the first byte will be received. This byte contai the opcode that defines the operatio to be performed. Invalid Opcode: If an invalid opcode is received, no data will be shifted into the ATB/64B, and the Serial Output pin () will remain in a high-impedance state until the falling edge of is detected again. This will reinitialize the serial communication. Chip Select: The ATB/64B is selected when the pin is low. When the device is not selected, data will not be accepted via the pin, and the Serial Output pin () will remain in a high-impedance state. Hold: The HOLD pin is used in conjunction with the pin to pause the ATB/64B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the pin is low. To resume serial communication, the HOLD pin is brought high while the pin is low ( may still toggle during HOLD). Inputs to the pin will be ignored while the pin is in the high-impedance state. Write Protect: The Write Protect pin (WP) will allow normal read/write operatio when held high. When the WP pin is brought low and WPEN bit is one, all write operatio to the status register are inhibited. WP going low while is still low will interrupt a Write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is zero. This will allow the user to itall the ATB/64B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functio are enabled when the WPEN bit is set to one. 6

7 Figure -. SPI Serial Interface Master: Microcontroller Data Out (MO) Data In (MI) Serial Clock (SPI CK) SS SS SS SS Slave: ATB/64B 7

8 6. Functional Description The ATB/64B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 68 and 68HC series of microcontrollers. The ATB/64B utilizes an 8-bit itruction register. The list of itructio and their operation codes are contained in Table 6-. All itructio, addresses, and data are traferred with the MSB first and start with a high-to-low traition. Table 6-. Itruction Set Itruction Name Itruction Format Operation WREN X Set Write Enable Latch WRDI X Reset Write Enable Latch RDSR X Read Status Register WRSR X Write Status Register READ X Read Data from Memory Array WRITE X Write Data to Memory Array Write Enable (WREN): The device will power-up in the write disable state when V CC is applied. All programming itructio must therefore be preceded by a Write Enable itruction. Write Disable (WRDI): To protect the device agait inadvertent writes, the Write Disable itruction disables all programming modes. The WRDI itruction is independent of the status of the WP pin. Read Status Register (RDSR): The Read Status Register itruction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR itruction. Similarly, the Block Write Protection Bits indicate the extent of protection employed. These bits are set by using the WRSR itruction. Table 6-. Status Register Format Bit 7 Bit 6 Bit Bit 4 Bit Bit Bit Bit WPEN X X X BP BP WEN RDY Table 6-. Bit Bit (RDY) Bit (WEN) Read Status Register Bit Definition Definition Bit = (RDY) indicates the device is READY. Bit = indicates the write cycle is in progress. Bit = indicates the device is not WRITE ENABLED. Bit = indicates the device is write enabled. Bit (BP) See Table 6-4 on page 9. Bit (BP) See Table 6-4 on page 9. Bits 4 6 are zeros when device is not in an internal write cycle. Bit 7 (WPEN) See Table 6- on page 9. Bits 7 are ones during an internal write cycle. 8

9 Write Status Register (WRSR): The WRSR itruction allows the user to select one of four levels of protection. The ATB/64B is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read-only. The Block Write Protection levels and corresponding status register control bits are shown in Table 6-4. The three bits BP, BP, and WPEN are nonvolatile cells that have the same properties and functio as the regular memory cells (e.g., WREN, t WC, RDSR). Table 6-4. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP BP ATB AT64B None None (/4) C FFF 8 FFF (/) 8 FFF FFF (All) FFF FFF The WRSR itruction also allows the user to enable or disable the Write Protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware Write Protection is enabled when the WP pin is low and the WPEN bit is one. Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is zero. When the device is hardware write protected, writes to the status register, including the Block Protect bits and the WPEN bit, and the block-protected sectio in the memory array are disabled. Writes are only allowed to sectio of the memory that are not block-protected. Note: When the WPEN bit is Hardware Write Protected, it cannot be changed back to zero as long as the WP pin is held low. Table 6-. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register X Protected Protected Protected X Protected Writeable Writeable Low Protected Protected Protected Low Protected Writeable Protected X High Protected Protected Protected X High Protected Writeable Writeable 9

10 Read Sequence (READ): Reading the ATB/64B via the Serial Output () pin requires the following sequence. After the line is pulled low to select a device, the Read opcode is tramitted via the line followed by the byte address to be read (A A, see Table 6-6). Upon completion, any data on the line will be ignored. The data (D7 D) at the specified address is then shifted out onto the line. If only one byte is to be read, the line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. Write Sequence (WRITE): In order to program the ATB/64B, two separate itructio must be executed. First, the device must be write enabled via the WREN itruction. Then a Write itruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection level. During an internal write cycle, all commands will be ignored except the RDSR itruction. A Write itruction requires the following sequence. After the line is pulled low to select the device, the Write opcode is tramitted via the line followed by the byte address (A A) and the data (D7 D) to be programmed (see Table 6-6). Programming will start after the pin is brought high. The low-to-high traition of the pin must occur during the low-time immediately after clocking in the D (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) itruction. If Bit =, the write cycle is still in progress. If Bit =, the write cycle has ended. Only the RDSR itruction is enabled during the write programming cycle. The ATB/64B is capable of a -byte page write operation. After each byte of data is received, the five low-order address bits are internally incremented by one; the high-order bits of the address will remain cotant. If more than -bytes of data are tramitted, the address counter will rollover and the previously written data will be overwritten. The ATB/64B is automatically returned to the write disable state at the completion of a write cycle. Note: If the device is not Write-enabled (WREN), the device will ignore the write itruction and will return to the standby state, when is brought high. A new falling edge is required to reinitiate the serial communication. Table 6-6. Address Key Address ATB AT64B A N A A A A Don t Care Bits A A A A

11 7. Timing Diagrams Figure 7-. Synchronous Data Timing (for Mode ) t V IH V IL t S t H V IH t WH t WL V IL t SU t H V IH V IL Valid In t V t HO t DIS V OH V OL HI-Z HI-Z Figure 7-. WREN Timing WREN Opcode HI-Z Figure 7-. WRDI Timing WRDI Opcode HI-Z

12 Figure 7-4. RDSR Timing Itruction High-impedance MSB Data Out Figure 7-. WRSR Timing Itruction Data In High-impedance Figure 7-6. Read Timing Byte Address Itruction 4... High-impedance 7 6 Data Out 4 MSB

13 Figure 7-7. Write Timing Itruction Byte Address Data In High-impedance Figure 7-8. HOLD Timing t CD t CD t HD HOLD t HD t HZ t LZ

14 8. Ordering Code Detail ATB-SSHL-B Atmel Designator Product Family = Standard SPI Serial EPPROM Device Deity = -kilobit 64 = 64-kilobit Device Revision Shipping Carrier Option B = Bulk (Tubes) T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity Option Operating Voltage L =.8V to.v Packaged Device Grade or Wafer/Die Thickness H = Green, NiPdAu Lead Finish Industrial Temperature Range (-4 C to +8 C) U = Green, Matte Sn Lead Finish Industrial Temperature Range (-4 C to +8 C) = mil Wafer Thickness Package Option SS = JEDEC IC X = TSP MA = UDFN ME = XDFN C = VFBGA WWU = Wafer Uawn WDT = Die in Tape and Reel 4

15 9. Part Markings ATB and AT64B: Package Marking Information 8-lead IC 8-lead TSP 8-lead UDFN. x. mm Body ATMLHYWW AAAAAAAA ATHYWW AAAAAAA ### HL@ YXX 8-ball VFBGA. x.7 mm Body 8-lead XDFN.8 x. mm Body ### YXX Note : designates pin Note : Package drawings are not to scale Catalog Number Truncation ATB AT64B Truncation Code ###: BB Truncation Code ###: CB Date Codes Voltages Y = Year M = Month WW = Work Week of Assembly L:.8V min : 6: 6 A: January : Week : 7: 7 B: February 4: Week 4 4: 4 8: : 9: 9 L: December : Week Country of Assembly Lot Number Grade/Lead Finish = Country of Assembly AAA...A = Atmel Wafer Lot Number U: Industrial/Matte Tin H: Industrial/NiPdAu Trace Code XX = Trace Code (Atmel Lot Numbers Correspond to Code) Example: AA, AB... YZ, ZZ Atmel Truncation AT: Atmel ATM: Atmel ATML: Atmel // TITLE DRAWING NO. REV. Package Mark Contact: DL-C-Assy_eng@atmel.com -64BSM, ATB and AT64B Package Marking Information -64BSM B

16 . Ordering Information Atmel Ordering Code Lead Finish Package Delivery Information Form Quantity Operation Range ATB-SSHL-B Bulk (Tubes) per Tube 8S ATB-SSHL-T Tape and Reel 4, per Reel ATB-XHL-B Bulk (Tubes) per Tube ATB-XHL-T 8X NiPdAu (Lead-free/Halogen-free) Tape and Reel, per Reel ATB-MAHL-T Tape and Reel, per Reel 8MA ATB-MAHL-E Tape and Reel, per Reel Industrial Temperature (-4 C to 8 C) ATB-MEHL-T 8ME Tape and Reel, per Reel ATB-CUL-T SnAgCu (Lead-free/Halogen-free) 8U- Tape and Reel, per Reel ATB-WWUL () N/A Wafer Sale Note AT64B-SSHL-B Bulk (Tubes) per Tube 8S AT64B-SSHL-T Tape and Reel 4, per Reel AT64B-XHL-B Bulk (Tubes) per Tube AT64B-XHL-T 8X NiPdAu (Lead-free/Halogen-free) Tape and Reel, per Reel AT64B-MAHL-T Tape and Reel, per Reel 8MA AT64B-MAHL-E Tape and Reel, per Reel Industrial Temperature (-4 C to 8 C) AT64B-MEHL-T 8ME Tape and Reel, per Reel AT64B-CUL-T SnAgCu (Lead-free/Halogen-free) 8U- Tape and Reel, per Reel AT64B-WWUL () N/A Wafer Sale Note Note:. Contact Atmel Sales for Wafer sales Package Type 8S 8X 8MA 8ME 8-lead,. wide, Plastic Gull Wing Small Outline (JEDEC IC) 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline Package (TSP) 8-pad,.mm x.mm body,.mm pitch, Ultra Thin, Dual No Lead (UDFN) 8-pad,.8mm x.mm body, Ultra Lead Frame Land Grid Array (XDFN) 8U- 8-ball,.mm x.7mm body,.7mm pitch (VFBGA) 6

17 . Packaging Information. 8S 8-lead JEDEC IC C E E N L TOP VIEW Ø END VIEW e b A COMMON DIMENONS (Unit of Measure = mm) A SYMBOL MIN NOM MAX NOTE A..7 A.. b.. C.7. D DE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-, Variation AA for proper dimeio, tolerances, datums, etc. D 4.8. E.8.99 E e.7 BSC L.4.7 Ø 8 6// TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com 8S, 8-lead (. Wide Body), Plastic Gull Wing Small Outline (JEDEC IC) SWB 8S G 7

18 . 8X 8-lead TSP C Pin indicator this corner E E L Top View b N A End View L A Notes: D e Side View. This drawing is for general information only. Refer to JEDEC Drawing MO-, Variation AA, for proper dimeio, tolerances, datums, etc.. Dimeion D does not include mold Flash, protrusio or gate burrs. Mold Flash, protrusio and gate burrs shall not exceed.mm (.6in) per side.. Dimeion E does not include inter-lead Flash or protrusio. Inter-lead Flash and protrusio shall not exceed.mm (.in) per side. 4. Dimeion b does not include Dambar protrusion. Allowable Dambar protrusion shall be.8mm total in excess of the b dimeion at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is.7mm.. Dimeion D and E to be determined at Datum Plane H. A COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A - -. A. -. A.8.. D.9.., E 6.4 BSC E , b e.6 BSC L L. REF C.9 -. /7/4 TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com 8X, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSP) TNR 8X E 8

19 . 8MA 8-pad UDFN E Pin ID D 4 TOP VIEW C A A DE VIEW A E b (8x) 8 Notes: e (6x) 7 6 L (8x) Pin# ID BOTTOM VIEW. This drawing is for general information only. Refer to Drawing MO-9, for proper dimeio, tolerances, datums, etc.. The Pin # ID is a laser-marked feature on Top View.. Dimeio b applies to metallized terminal and is measured between. mm and. mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimeion should not be measured in that radius area. 4. The Pin # ID on the Bottom View is an orientation feature on the thermal pad. 4 K D COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A...6 A... A - -. D.9.. D.4..6 E.9.. E...4 b.8.. C. REF L...4 e. BSC K. - - /6/4 Package Drawing Contact: packagedrawings@atmel.com TITLE 8MA, 8-pad x x.6mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No-Lead Package (UDFN) GPC YNZ DRAWING NO. 8MA REV. G 9

20 .4 8ME 8-pad XDFN 8 7 D 6 PIN # ID E 4 A Top View A e b Side View L COMMON DIMENONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE PIN # ID. A A..4.. D E e b b e e...4 TYP. REF. End View L.6.. 9// Package Drawing Contact: packagedrawings@atmel.com TITLE 8ME, 8-pad (.8mm x.mm body) Extra Thin DFN (XDFN) GPC DRAWING NO. REV. DTP 8ME B

21 . 8U- 8-ball VFBGA f. C d. (4X) d.8 C A BALL PAD CORNER D A C A BALL PAD CORNER E Øb j n. m C A B j n.8 m C e A B C (e) D B A A A (d) d TOP VIEW DE VIEW BOTTOM VIEW 8 LDER BALLS COMMON DIMENONS (Unit of Measure = mm) Notes:. This drawing is for general. Dimeion 'b' is measured at the maximum solder ball diameter.. Solder ball composition shall be 9.Sn-4.Ag-.Cu. SYMBOL MIN NOM MAX NOTE A.8.9. A... A.4.4. b... D. BSC E.7 BSC e.7 BSC e.74 REF d.7 BSC d.8 REF 6// Package Drawing Contact: packagedrawings@atmel.com TITLE 8U-, 8-ball,. x.7 mm Body,.7 mm pitch, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GPC GWW DRAWING NO. REV. 8U- G

22 . Revision History Doc. Rev. Date Comments 8H / 8G / 8F 6/ Add the UDFN Expanded Quantity Option. Update the 8X, 8MA, and 8ME package outline drawings and the ordering information. Update part markings to single page part marking. Update package drawings. Replace 8A package with 8X package. Update template and Atmel logos. Update 8A and 8S package drawings. Remove Preliminary. 8E 4/ Update Ordering Code Detail, Ordering Information, template. 8D 8/9 Change Catalog Numbering. Add new Part Marking Information. 8C /9 Add Part Marking information; changed to Preliminary status. 8B 7/8 Modify Endurance parameter on page 6. 8A 4/8 Initial document release.

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