2-Mbit (128K x 16) Static RAM

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1 2-Mbit (128K x 16) Static RAM Features Temperature Ranges Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Automotive-E: 40 C to 125 C High speed: 55 ns Wide voltage range: 2.7V 3.6V Ultra-low active, standby power Easy memory expansion with and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Available in standard Pb-free 44-pin TSOP Type II, Pb-free and non Pb-free 48-ball FBGA packages Functional Description [1] The CY62136VN is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected ( HIGH). The input/output pins (I/O 0 through I/O 15 ) are placed in a high-impedance state when: deselected ( HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation ( LOW, and LOW). Writing to the device is accomplished by taking Chip Enable () and Write Enable () inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 0 through I/O 7 ), is written into the location specified on the address pins (A 0 through A 16 ). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 through I/O 15 ) is written into the location specified on the address pins (A 0 through A 16 ). Reading from the device is accomplished by taking Chip Enable () and Output Enable (OE) LOW while forcing the Write Enable () HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O 0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 8 to I/O 15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. Logic Block Diagram A 10 A 9 A 8 A 7 A 6 A 5 A 4 ROW DECODER DATA IN DRIVERS 128K x 16 RAM Array I/O 0 I/O 7 A 3 A 2 I/O 8 I/O 15 A 1 A 0 COLUMN DECODER A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPS BHE OE BLE PinConfigurations [3] A 4 A 3 A 2 A 1 A 0 I/O 0 I/O 1 I/O 2 I/O 3 V SS I/O 4 I/O 5 I/O 6 I/O 7 A 16 A 15 A 14 A 13 A 12 TSOP II (Forward) Top View A 5 A 6 A 7 OE BHE BLE I/O 15 I/O 14 I/O 13 I/O 12 V SS I/O 11 I/O 10 I/O 9 I/O 8 A 8 A 9 A 10 A 11 Note: 1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: Rev. *A Revised August 3, 2006

2 Product Portfolio Power Dissipation Range (V) Operating, I CC (ma) Standby, I SB2 (µa) Product Min Typ. [2] Max Speed Ranges Typ. [2] Maximum Typ. [2] Maximum CY62136VNLL Industrial Automotive-A Industrial Automotive-A Automotive-E Pin Configurations [3] 1 FBGA Top View BLE OE A 0 A 1 A 2 A I/O 8 BHE A 3 A 4 I/O 0 B I/O 9 I/O 10 A 5 A 6 I/O 1 I/O 2 C V SS I/O 11 A 7 I/O 3 D I/O 12 A 16 I/O 4 V SS E I/O 14 I/O 13 A 14 A 15 I/O 5 I/O 6 F I/O 15 A 12 A 13 I/O 7 G A 8 A 9 A 10 A 11 H Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at = Typ, T A = 25 C. 3. pins are not connected on the die. Document #: Rev. *A Page 2 of 12

3 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage to Ground Potential V to +4.6V DC Voltage Applied to Outputs in High-Z State [4] V to + 0.5V DC Input Voltage [4] V to + 0.5V Output Current into Outputs (LOW) ma Static Discharge Voltage... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current... > 200 ma Operating Range Range Ambient Temperature [T A ] [5] Industrial 40 C to +85 C 2.7V to Automotive-A 40 C to +85 C 3.6V Automotive-E 40 C to +125 C Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ. [2] Max. Min. Typ. [2] Max. Unit V OH Output HIGH Voltage = 2.7V, I OH = 1.0 ma V V OL Output LOW Voltage = 2.7V, I OL = 2.1 ma V V IH Input HIGH Voltage = 3.6V V V V IL Input LOW Voltage = 2.7V V I IX Input Leakage GND < V I < Ind l µa Current Auto-A µa Auto-E µa I OZ Output Leakage GND < V O <, Ind l µa Current Output Disabled Auto-A µa Auto-E µa I CC Operating f = f MAX Ind l ma = 3.6V, Supply = 1/t RC I OUT = 0 ma, Auto-A Current CMOS Levels Auto-E 7 20 f = 1 MHz Ind l ma Auto-A Auto-E 1 2 I SB1 I SB2 Automatic Power-down Current CMOS Inputs Automatic Power-down Current CMOS Inputs > 0.3V, V IN > 0.3V or V IN < 0.3V, f = f MAX > 0.3V V IN > 0.3V or V IN < 0.3V, f = 0 Ind l µa Auto-A µa Auto-E 100 µa Ind l µa Auto-A Auto-E 1 20 Capacitance [6] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 6 pf C OUT Output Capacitance = (typ) 8 pf Notes: 4. V IL (min) = 2.0V for pulse durations less than 20 ns. 5. T A is the Instant-On case temperature. 6. Tested initially and after any design or process changes that may affect these parameters. V Document #: Rev. *A Page 3 of 12

4 Thermal Resistance [6] CY62136VN MoBL Parameter Description Test Conditions TSOPII FBGA Unit Θ JA Thermal Resistance Still Air, soldered on a 4.25 x inch, C/W (Junction to Ambient) 4-layer printed circuit board Θ JC Thermal Resistance (Junction to Case) C/W AC Test Loads and Waveforms OUTPUT 30 pf ILUDING JIG AND SCOPE R1 (a) R2 OUTPUT 5 pf ILUDING JIG AND SCOPE R1 (b) R2 Typ GND 10% Rise Time: 1 V/ns ALL INPUT PULSES 90% (c) Equivalent to: THÉ VENIN EQUIVALENT 90% 10% Fall Time: 1 V/ns OUTPUT RTH V Parameters Value Unit R Ohms R Ohms R TH 645 Ohms V TH 1.75 Volts Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions [9] Min. Typ. [2] Max. Unit V DR for Data Retention 1.0 V I CCDR Data Retention Current = 1.0V, > 0.3V, V IN > 0.3V or V IN < 0.3V, µa [6] t CDR Chip Deselect to Data 0 ns Retention Time t [7] R Operation Recovery Time 70 ns Data Retention Waveform DATA RETENTION MODE (min.) V DR > 1.0 V (min.) t CDR t R Note: 7. Full device operation requires linear ramp from V DR to (min) > 100 ms or stable at (min) > 8. No input may exceed + 0.3V 100 ms. Document #: Rev. *A Page 4 of 12

5 Switching Characteristics Over the Operating Range [9] 55 ns 70 ns Parameter Description Min. Max. Min. Max. Unit Read Cycle t RC Read Cycle Time ns t AA Address to Data Valid ns t OHA Data Hold from Address Change ns t A LOW to Data Valid ns t DOE OE LOW to Data Valid ns t LZOE OE LOW to Low-Z [10] 5 5 ns t HZOE OE HIGH to High-Z [10, 11] ns t LZ LOW to Low-Z [10] ns t HZ HIGH to High-Z [10, 11] ns t PU LOW to Power-up 0 0 ns t PD HIGH to Power-down ns t DBE BLE / BHE LOW to Data Valid ns t LZBE BLE / BHE LOW to Low-Z [10, 11] 5 5 ns t HZBE BLE / BHE HIGH to High-Z [12] ns [12, 13] Write Cycle t WC Write Cycle Time ns t S LOW to Write End ns t AW Address Set-up to Write End ns t HA Address Hold from Write End 0 0 ns t SA Address Set-up to Write Start 0 0 ns t P Pulse Width ns t BW BLE / BHE LOW to Write End ns t SD Data Set-up to Write End ns t HD Data Hold from Write End 0 0 ns t HZ LOW to High-Z [10, 11] ns t LZ HIGH to Low-Z [10] 5 10 ns Notes: 9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to typ., and output loading of the specified I OL /I OH and 30-pF load capacitance. 10. At any given temperature and voltage condition, t HZ is less than t LZ, t HZOE is less than t LZOE, and t HZ is less than t LZ for any given device. 11. t HZOE, t HZ, and t HZ are specified with C L = 5 pf as in (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 12. The internal write time of the memory is defined by the overlap of LOW and LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 13. The minimum write cycle time for write cycle 3 ( controlled, OE LOW) is the sum of t HZ and t SD. Document #: Rev. *A Page 5 of 12

6 Switching Waveforms Read Cycle No. 1 [14, 15] t RC ADDRESS t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 [15, 16] t RC OE t A t PD t HZ BHE/BLE t LZOE t DOE t HZOE t DBE t HZBE DATA OUT t LZBE HIGH IMPEDAN DATA VALID HIGH IMPEDAN t LZ SUPPLY CURRENT t PU 50% 50% I CC I SB Notes: 14. Device is continuously selected. OE, = V IL. 15. is HIGH for read cycle. 16. Address valid prior to or coincident with transition LOW. Document #: Rev. *A Page 6 of 12

7 Switching Waveforms (continued) Write Cycle No. 1 ( Controlled) [12, 17, 18] t WC ADDRESS t AW t HA t SA t P BHE/BLE t BW OE t SD t HD DATA I/O NOTE19 DATA IN VALID t HZOE [12, 17, 18] Write Cycle No. 2 ( Controlled) t WC ADDRESS t S t SA t AW tha BHE/BLE t BW t P t SD t HD DATA I/O DATA IN VALID Notes: 17. Data I/O is high impedance if OE = V IH. 18. If goes HIGH simultaneously with HIGH, the output remains in a high-impedance state. 19. During this period, the I/Os are in output state and input signals should not be applied. Document #: Rev. *A Page 7 of 12

8 Switching Waveforms (continued) Write Cycle No. 3 ( Controlled, OE LOW) [13, 18] t WC ADDRESS t AW t HA BHE/BLE t BW t SA t SD t HD DATA I/O NOTE 19 DATA IN VALID t HZ t LZ Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [19] t WC ADDRESS t AW t HA BHE/BLE t BW t SA t SD t HD DATA I/O NOTE 19 DATA IN VALID t HZ t LZ Document #: Rev. *A Page 8 of 12

9 Typical DC and AC Characteristics I CC SUPPLY VOLTAGE (V) Normalized Operating Current vs. Supply Voltage MoBL Access Time vs. Supply Voltage MoBL I SB (µa) Standby Current vs. Supply Voltage MoBL SUPPLY VOLTAGE (V) T AA (ns) SUPPLY VOLTAGE (V) Truth Table OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power-down Standby (I SB ) L H L L L Data Out (I/O 0 I/O 15 ) Read Active (I CC ) L H L H L Data Out (I/O 0 I/O 7 ); Read Active (I CC ) I/O 8 I/O 15 in High-Z L H L L H Data Out (I/O 8 I/O 15 ); Read Active (I CC ) I/O 0 I/O 7 in High-Z L H L H H High-Z Deselect/Output Disabled Active (I CC ) L H H L L High-Z Deselect/Output Disabled Active (I CC ) L H H H L High-Z Deselect/Output Disabled Active (I CC ) L H H L H High-Z Deselect/Output Disabled Active (I CC ) L L X L L Data In (I/O 0 I/O 15 ) Write Active (I CC ) L L X H L Data In (I/O 0 I/O 7 ); Write Active (I CC ) I/O 8 I/O 15 in High-Z L L X L H Data In (I/O 8 I/O 15 ); I/O 0 I/O 7 in High-Z Write Active (I CC ) Document #: Rev. *A Page 9 of 12

10 Ordering Information CY62136VN MoBL Speed (ns) Ordering Code Package Diagram Package Type Operating Range 55 CY62136VNLL-55ZXI pin TSOP II (Pb-Free) Industrial CY62136VNLL-55BAI Ball (7.00 mm x 7.00 mm) FBGA CY62136VNLL-55ZSXA pin TSOP II (Pb-Free) Automotive-A 70 CY62136VNLL-70ZXI pin TSOP II (Pb-Free) Industrial CY62136VNLL-70BAI Ball (7.00 mm x 7.00 mm) FBGA CY62136VNLL-70BAXA Ball (7.00 mm x 7.00 mm) FBGA (Pb-Free) Automotive-A CY62136VNLL-70ZSXA pin TSOP II (Pb-Free) CY62136VNLL-70ZSXE pin TSOP II (Pb-Free) Automotive-E Please contact your local Cypress sales representative for availability of these parts Package Diagrams 44-pin TSOP II ( ) *A Document #: Rev. *A Page 10 of 12

11 Package Diagrams (continued) 48-Ball (7.00 mm x 7.00 mm) FBGA ( ) TOP VIEW PIN 1 CORNER (LASER MARK) BOTTOM VIEW Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) PIN 1 CORNER A A B B C C 7.00±0.10 D E F G 7.00± D E F G H H A A B 7.00± B 7.00± C 0.53± ± C 0.15(4X) *F SEATING PLANE 0.36 C 1.20 MAX. MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the products of their respective holders. Document #: Rev. *A Page 11 of 12 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

12 Document History Page Document Title: CY62136VN MoBL 2-Mbit (128K x 16) Static RAM Document Number: Orig. of REV. ECN NO. Issue Date Change Description of Change ** See ECN RXU New Data Sheet *A See ECN NXR Added Automotive product Updated ordering Information table Document #: Rev. *A Page 12 of 12

13 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cypress Semiconductor: CY62136VNLL-55ZSXA CY62136VNLL-55ZSXAT CY62136VNLL-70BAXA CY62136VNLL-70BAXAT CY62136VNLL-70ZSXA CY62136VNLL-70ZSXAT

1-Mbit (64K x 16) Static RAM

1-Mbit (64K x 16) Static RAM Features Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive: 40 C to 125 C High speed t AA = 12 ns (Commercial & Industrial) t AA = 15 ns (Automotive)