64K x 32 Static RAM Module

Size: px

Start display at page:

Download "64K x 32 Static RAM Module"

Job Welch
6 years ago
Views:

1 31 CYM1831 Features High-density 2-Mbit SRAM module 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 High-speed CMOS SRAMs Access time of 15 ns Low active power 5.3W (max.) SMD technology TTL-compatible inputs and outputs Low profile Max. height of 0.50 in. Small PCB footprint 1.2 sq. in. Functional Description The CYM1831 is a high-performance 2-Mbit static RAM module organized as 6K words by 32 bits. This module is constructed from eight SRAMs in SOJ packages mounted 6K x 32 Static RAM Module on an epoxy laminate board with pins. Four chip selects (CS 1, CS 2, CS 3, and CS ) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate Chip Selects (CS N ) and Write Enable (WE) inputs are both LOW. Data on the input/output pins (I/O X ) is written into the memory location specified on the address pins (A 0 through A 15 ). Reading the device is accomplished by taking the Chip Selects (CS N ) LOW and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O X ). The data input/output pins stay in the high-impedance state when Write Enable (WE) is LOW or the appropriate chip selects are HIGH. Two pins (PD 0 and PD 1 ) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. Logic Block Diagram Pin Configuration ZIP/SIMM Top View A 0 A 15 OE WE CS 1 CS 2 CS 3 CS 16 SRAM SRAM SRAM SRAM I/O 0 I/O 3 I/O 8 I/O 11 I/O 16 I/O 19 I/O 2 I/O 27 PD 0 - OPEN 1 GND PD 1 - GND PD PD I/O I/O I/O I/O I/O I/O I/O V I/O 11 CC A A A 1 I/O I/O 7 A SRAM A 2 A 9 18 SRAM SRAM SRAM I/O 12 I/O 15 I/O 20 I/O 23 I/O 28 I/O 31 I/O I/O 5 I/O 6 I/O 7 WE A 1 CS 1 CS 3 NC GND I/O 16 I/O 17 I/O 18 I/O 19 A 10 A 11 A 12 A 13 I/O 20 I/O 21 I/O 22 I/O 23 GND I/O 12 I/O 13 I/O 1 I/O 15 GND A 15 CS 2 CS NC OE I/O 2 I/O 25 I/O 26 I/O 27 A 3 A A 5 V CC A 6 I/O 28 I/O 29 I/O 30 I/O 31 Cypress Semiconductor Corporation 3901 North First Street San Jose CA Document #: Rev. ** Revised March 15, 2002

2 Selection Guide Maximum Access Time (ns) Maximum Operating Current (ma) Maximum Standby Current (ma) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage to Ground Potential V to +7.0V DC Voltage Applied to Outputs in High Z State V to +7.0V DC Input Voltage V to +7.0V Output Current into Outputs (LOW)...20 ma Operating Range Ambient Range Temperature V CC Commercial 0 C to +70 C 5V ± 10% Electrical Characteristics Over the Operating Range , 30, 35, 5 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit V OH Output HIGH Voltage V CC = Min., I OH =.0 ma V V OL Output LOW Voltage V CC = Min., I OL = 8.0 ma V V IH Input HIGH Voltage 2.2 V CC 2.2 V CC 2.2 V CC V V IL Input LOW Voltage V I IX Input Load Current GND < V I < V CC µa I OZ Output Leakage GND < V O < V CC, µa Current Output Disabled I CC I SB1 I SB2 V CC Operating Supply Current V CC = Max., I OUT = 0 ma, ma CS N < V IL Automatic CS Power-Down Current [1] Min. Duty Cycle = V CC = Max., CS N > V IH, 100% Automatic CS Power-Down Current [1] V CC = Max., CS N > V CC 0.2V, V IN > V CC 0.2V or V IN < 0.2V ma ma Capacitance [2] Parameter Description Test Conditions Max. Unit C INA Input Capacitance (A 0 A 15, WE, OE) T A = 25 C, f = 1 MHz, 80 pf C INB Input Capacitance (CS) V CC = 5.0V 15 pf C OUT Output Capacitance 20 pf Notes: 1. A pull-up resistor to V CC on the CS input is required to keep the device deselected during V CC power-up, otherwise I SB will exceed values given. 2. Tested on a sample basis. Document #: Rev. ** Page 2 of 8

3 AC Test Loads and Waveforms R1 81Ω 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE (a) R1 81Ω 5V OUTPUT R2 255Ω 5 pf INCLUDING JIG AND SCOPE (b) R2 255Ω 3.0V GND <5ns 10% ALL INPUT PULSES 90% 90% 10% <5ns Equivalent to: THÉ VENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range [3] Parameter READ CYCLE Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. t RC Read Cycle Time ns t CS LOW to Low Z [] t AA Address to Data Valid ns t OHA Data Hold from Address Change ns t ACS CS LOW to Data Valid ns t DOE OE LOW to Data Valid ns t LZOE OE LOW to Low Z ns t HZOE OE LOW to High Z ns ns LZCS 0 t HZCS CS HIGH to High Z [, 5] ns WRITE CYCLE [6] t WC Write Cycle Time ns t SCS CS LOW to Write End ns t AW Address Set-Up to ns Write End t HA Address Hold from ns Write End t SA Address Set-Up to ns Write Start t PWE WE Pulse Width ns t SD Data Set-Up to Write ns End t HD Data Hold from Write ns End t LZWE WE HIGH to Low Z ns t HZWE WE LOW to High Z [5] ns Note: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance.. At any given temperature and voltage condition, t HZCS is less than t LZCS for any given device. These parameters are guaranteed by design and not 100% tested. 5. t HZCS and t HZWE are specified with C L = 5 pf as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mv from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: Rev. ** Page 3 of 8 Unit

4 Switching Waveforms [7, 8] Read Cycle No. 1 t RC ADDRESS t AA DATA OUT t OHA PREVIOUS DATA VALID DATA VALID [7, 9] Read Cycle No. 2 CS t RC t ACS OE DATA OUT t DOE t LZOE HIGH IMPEDANCE DATA VALID t HZOE t HZCS HIGH IMPEDANCE V CC SUPPLY CURRENT t LZCS t PU 50% t PD 50% ICC ISB Notes: 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = V IL and OE= V IL. 9. Address valid prior to or coincident with CS transition LOW. Document #: Rev. ** Page of 8

5 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [6] t WC ADDRESS CS t SCS t AW t SA t PWE t HA WE t SD t HD DATA IN DATA VALID DATA OUT DATA UNDEFINED t HZWE t LZWE HIGH IMPEDANCE [6, 10] Write Cycle No. 2 (CS Controlled) t WC ADDRESS t SA t SCS CS t AW t PWE t HA WE t SD t HD DATA IN DATA VALID t HZWE DATA OUT DATA UNDEFINED HIGH IMPEDANCE Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table CS N WE OE Inputs/Outputs Mode H X X High Z Deselect/Power-Down L H L Data Out Read L L X Data In Write L H H High Z Deselect Document #: Rev. ** Page 5 of 8

6 Ordering Information Package Package Operating Speed Ordering Code Name Type Range 15 CYM1831PM 15C PM01 6-Pin Plastic SIMM Module Commercial CYM1831PN 15C PN01 6-Pin Plastic Angled SIMM Module CYM1831PY 15C PM01 6-Pin Gold SIMM Module CYM1831PZ 15C PZ01 6-Pin Plastic ZIP Module 20 CYM1831PM 20C PM01 6-Pin Plastic SIMM Module Commercial CYM1831PN 20C PN01 6-Pin Plastic Angled SIMM Module CYM1831PY 20C PM01 6-Pin Gold SIMM Module CYM1831PZ 20C PZ01 6-Pin Plastic ZIP Module 25 CYM1831PM 25C PM01 6-Pin Plastic SIMM Module Commercial CYM1831PN 25C PN01 6-Pin Plastic Angled SIMM Module CYM1831PY 25C PM01 6-Pin Gold SIMM Module CYM1831PZ 25C PZ01 6-Pin Plastic ZIP Module 35 CYM1831PM 35C PM01 6-Pin Plastic SIMM Module Commercial CYM1831PN 35C PN01 6-Pin Plastic Angled SIMM Module CYM1831PY 35C PM01 6-Pin Gold SIMM Module CYM1831PZ 35C PZ01 6-Pin Plastic ZIP Module 5 CYM1831PM 5C PM01 6-Pin Plastic SIMM Module Commercial CYM1831PN 5C PN01 6-Pin Plastic Angled SIMM Module CYM1831PY 5C PM01 6-Pin Gold SIMM Module CYM1831PZ 5C PZ01 6-Pin Plastic ZIP Module Document #: Rev. ** Page 6 of 8

7 Package Diagrams DIA PLCS 6-Pin Plastic SIMM Module PM MAX MAX PIN (6 PINS) 0.62 R REF PIN 6 6-Pin Plastic Angled SIMM Module PN / / MAX.397/.03.25/.255 C1 C2 C3 C5 C7 U1 U2 U3 U C C6 C8 C9 C10.590/.600 PIN1.061/.063R.075/ / / / Pin Plastic ZIP Module PZ01 Bottom View MAX MAX Pin 1 DIMENSIONS IN INCHES MIN. MAX. Document #: Rev. ** Page 7 of 8 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

8 Document Title: CYM1831 6K x 32 Static RAM Module Document Number: Issue Orig. of REV. ECN NO. Date Change Description of Change ** /19/02 DSG Change from Spec number: 38-M to Document #: Rev. ** Page 8 of 8

I/O 0 I/O 7 WE CE 2 OE CE 1 A17 A18

I/O 0 I/O 7 WE CE 2 OE CE 1 A17 A18 2M x 8 Static RAM Features High speed t AA = 8, 10, 12 ns Low active power 1080 mw (max.) Operating voltages of 3.3 ± 0.3V 2.0V data retention Automatic power-down when deselected TTL-compatible inputs