Hands-On Workshop: ARM Architectures Optimization Hints & Tips

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1 Hands-On Workshop: ARM Architectures Optimization Hints & Tips FTF-AUT-F0337 Daniel McKenna Applications Engineer A P R TM External Use

2 Agenda This hands-on session will take a typical application project and apply various optimization techniques. Cortex A5 and Platform Example: Introduction to Benchmark DMA Example: Using DMA Cortex M4 and Dual Core Example: Using secondary core Cache Example: Using Cache] Example: Revisiting Benchmark External Use 1

3 The Class: The main goal is to explain the key architectural and system module features that can be tuned to optimize an application so that designers can make informed decisions when designing their system software. The Class is not: about coding techniques about compiler optimisation a step by step guide there is no universal set of rules! External Use 2

4 Cortex A5 and Platform External Use 3

5 Freescale Vybrid Controllers External Use 4

6 A5 Processor Core Details ARM Cortex -A5 Application Processor Operating at n:1 clock ratio compared to platform, where n = {2,3} Core frequencies = 266.6, MHz 8-stage pipeline provides 1.57 DMIPS per MHz performance Includes double precision FPU, NEON media engine, TrustZone Support for ARM and THUMB instruction sets 32K I- and 32K D-Caches with 32-byte cache line size Optional support for 512K L2 cache with 32-byte cache line size Partially enabled via an e-fuse Single 64-bit AXI system bus interface CoreSight debug and trace system Generic Interrupt Controller (GIC) External Use 5

7 ARM Cortex-A5 Processor Pipeline External Use 6

8 CPU Diagram to bus interface One bus interface, but Harvard Architecture cache External Use 7

9 Platform Diagram External Use 8

Masters TM Slaves NIC301 Bus NIC301 Internal Switches CoreLink Network Interconnect (NIC301) High-performance, optimized AMBAcompliant network infrastructure NIC301 optimised for 64-bit AXI interface

10 Masters TM Slaves NIC301 Bus NIC301 Internal Switches CoreLink Network Interconnect (NIC301) High-performance, optimized AMBAcompliant network infrastructure NIC301 optimised for 64-bit AXI interface CA5, GPU, 2D-ACE: 64-bit AXI interface Optimised master to slave connections Configurable at integration Reduces power and area of NIC301 Optimised for multi master data bandwidth, not data latency NIC301 has read/write buffering to improve throughput on larger data transfers Typ. 5 cycle latency for access between master & internal RAM External Use 9

11 AXI vs AHB AXI: Optimised for maximum throughput Burst-based, split transaction bus Ability to issue multiple outstanding addresses Out-of-order transaction completion AHB: Optimised for minimum latency Burst transfers, split transaction Master will wait for slave to respond Support for SPLIT transactions but predominantly in-order transaction completion External Use 10

12 Platform Masters Bus masters generate traffic Module Protocol Ports Data Width Cortex-A5 AXI 1 64 Cortex-M4 AHB-Lite 2 64 DMA2x AHB-Lite 1 64 DCU (x2) AXI 1 64 USB OTG (x2) AHB-Lite 1 32 Open VG AXI 1 64 ENET AHB-Lite 1 32 VIU3 AHB-Lite 1 64 esdhc (x2) AHB-Lite 1 32 NFC AHB-Lite 1 32 CAAM AXI 1 32 DAP AHB-Lite 1 32 External Use 11

13 Platform Slaves Internal SRAM: Total:1.5MB 1MB GRAM(no ECC) 2 x 256KB SRAM with ECC (32bit boundary) Module Protocol Ports Data Width ROM AHB-Lite 1 64 FlexBus AHB-Lite 1 32 QuadSPI (x2) AHB-Lite 1 64 OCRAM (x3) AXI 1 64 CM4_TCM AHB-Lite 1 64 SDRAMC (DDR) AXI 2 64 Peripheral Bridges (x2) AHB-Lite 1 64 External Use 12

14 DRAM Port Split DRAM has two ports. Accesses are split as: PORT 0 PORT 1 CM4 DCU0 USB VIU DMA0, ENET0, esdhc0, NFC, DBG CA5 GPU DCU1 DMA1, ENET1, USB, esdhc External Use 13

15 NIC Arbitration Known as Quality of Service (QoS) Primary arbitration: Higher QoS = higher priority Secondary arbitration: least recently granted Default: recommended configuration : Latency critical masters given higher priority Arbitration Priorities (abridged): Bus Master Default QoS Cortex-M4 Core 1 Cortex-M4 System 2 Cortex-A5 0 DMA 4 DCU 14 Open VG 12 VIU3 13 External Use 14

16 Example 1: Getting Started Locate and launch example 1 project. Note that main loop contains 3 main steps: -A memory copy -Data transmission via SPI -Mathematical Algorithm Run code and note A5 core loop time. External Use 15

17 DMA External Use 16

18 Introduction 2 x 32 channel DMA Memory Memory Memory Peripheral Alternative to interrupts Transfer data with no core intervention External Use 17

19 Peripherals: Selecting a DMA source Source # 1 Disabled Source # 2 Source # 3 Peripherals Source # 53 Always On #1 Always Enabled Always On #10 DMA Channel Mux DMA Channel #0 DMA Channel #1 DMA Channel #31 Software selects which DMA sources connect to the 32 DMA channels DMA request for channels can be initiated by: A peripheral (example: ADC conversion result ready to be put into queue) Software (example: set a bit to initiate a block move) External Use 18

20 DMA Configuration External Use 19

21 edma Mux: Channel Configuration Channel Configuration Registers [0:15] TRIG (PIT generated DMA request) is only available for channels 0:7 PIT timers 1:8 provide the TRIG for DMA channels 0:7 External Use 20

22 edma TCD: Transfer Control Descriptor Introduction Source Address (saddr) Signed Source Address Offset (soff) Transfer Attributes (smod, ssize, dmod, dsize) Inner Minor Byte Count (nbytes) Destination Address (daddr) Signed Destination Address Offset (doff) Current Major Iteration Count (citer) Last Source Address Adjustment (slast) Last Destination Address Adjustment (dlast_sga) Major Iteration Counter (biter) Channel Control Status (bwc, linkch, done, active, e_link, e_sg, dreq, int_half, int_maj, start) External Use 21

23 Peripherals: DMA TCD Loops Example Memory Array DMA Request... Minor Loop Current Major Loop Iteration Count (citer) 3 DMA Request... Minor Loop Major Loop 2 DMA Request... Minor Loop 1 Each DMA request initiates one minor loop transfer (iteration) without CPU intervention DMA arbitration can occur after each minor loop One level of minor loop DMA preemption is allowed The number of minor loops in a major loop = beginning iteration count (biter) External Use 22

24 edma TCD: Transfer Control Descriptor Introduction Source Address (saddr) Signed Source Address Offset (soff) Transfer Attributes (smod, ssize, dmod, dsize) Inner Minor Byte Count (nbytes) Destination Address (daddr) Signed Destination Address Offset (doff) Current Major Iteration Count (citer) Last Source Address Adjustment (slast) Last Destination Address Adjustment (dlast_sga) Major Iteration Counter (biter) Channel Control Status (bwc, linkch, done, active, e_link, e_sg, dreq, int_half, int_maj, start) External Use 23

25 Peripherals: DMA TCD Terms address starting address Minor Loop... Minor Loop size of one data transfer nbytes in minor loop (often the same value as size)... offset: number of bytes added to current address after each transfer (often the same value as size) Each DMA source and destination has their own: addr size offset last Peripheral queues typically have size and offset equal to nbytes. last: number of bytes added to current address after major loop (typically used to loop back) External Use 24

26 Peripherals: DMA Example (Different Size and Offset) Transferring alternating half-words DMA source: ADC output queue (in SRAM) DMA destination: SPI transmit eqadc Output Queue addr A/D Value 1 Time Stamp 1 A/D Value 2 Time Stamp 2 A/D Value 3 Time Stamp 3 size offset DMA transfers: A/D Value 1, A/D Value 2, A/D Value 3 SPI Tx Time stamps are not transferred because each DMA source reads 2 bytes, then increments the source address by 4 bytes. External Use 25

27 edma TCD: Transfer Control Descriptor Introduction Source Address (saddr) Signed Source Address Offset (soff) Transfer Attributes (smod, ssize, dmod, dsize) Inner Minor Byte Count (nbytes) Destination Address (daddr) Signed Destination Address Offset (doff) Current Major Iteration Count (citer) Last Source Address Adjustment (slast) Last Destination Address Adjustment (dlast_sga) Major Iteration Counter (biter) Channel Control Status (bwc, linkch, done, active, e_link, e_sg, dreq, int_half, int_maj, start) External Use 26

28 Peripherals: DMA TCD Scatter-Gather Feature Allows a DMA channel to use multiple TCDs Enables a DMA channel to scatter the DMA data to multiple destinations or gather it from multiple sources Example use: linked list of LIN messages TCD A (in flash or SRAM) TCD B (in flash or SRAM) sga sga (Scatter Gather Address) Sequence: 1. Initialization: Load TCD A from flash to DMA channel x s TCD 2. 1 st DMA request or START=1: Executes TCD A; TCD B loads automatically 3. 2 nd DMA request or START=1: Executes TCD B; TCD A loads automatically Option: TCD B could automatically execute with the 1 st DMA request if the TCD s start bit is set. External Use 27

29 Peripherals: DMA Channel Linking A DMA channel can link to another DMA channel, i.e., set the start bit of another TCD: At the end of every minor loop (except the last one) And/or at the end of the major loop Also enables linked lists Desired Link Behavior Link at end of minor loop Link at end of major loop TCD Control Field Name citer.e_link citer.linkch major.e_link major.linkch Description Enable channel-to-channel linking on minor loop completion (current iteration) Link channel number when linking at end of minor loop (current iteration) Enable channel-to-channel linking on major loop completion Link channel number when linking at end of major loop External Use 28

30 Peripherals: DMA Other Control & Status Fields (1 of 2) TCD Control Field Name start active Done d_req Description Control bit to explicitly start channel when using a software initiated DMA service. (Automatically cleared by hardware after service begins) (Note: Do not set START if DMA request comes from HW) Status bit indicating the channel is currently in execution Status bit indicating major loop completion (Set by hardware as CITER reaches 0. Cleared by software if using software initiated DMA service request.) Control bit to disable DMA request at end of major loop completion Clears channel enable bit, DMAERQ, at major loop completion so no additional DMA requests are recognized until channel is enabled again (Important for FIFOs later) External Use 29

31 Peripherals: DMA Other Control & Status Fields (2 of 2) TCD Control Field Name BWC[0:1] e_sg int_half int_major Description Control bits for throttling bandwidth control of a channel. Control bit to enable scatter-gather feature. Control bit to enable interrupt when major loop is half complete (DONE = 0) Control bit to enable interrupt when major loop completes (DONE = 1) BWC - Bandwidth Control Forces the edma to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar. 00 No DMA_Engine stalls (for inner loop) 01 reserved 10 DMA_Engine stalls for 4 cycles after each R/W 11 DMA_Engine stalls for 8 cycles after each R/W External Use 30

32 Peripherals: DMA Register and TCD Memory Map (1 of 2) Channels must be enabled before any DMA request is recognized Errors are caused from a bad configuration or a bus error 8-bit registers to easily modify a single channel s: Enable request bit Enable error interrupt bit Interrupt request (clear only) Error (clear only) TCD start bit (set only) TCD done bit (clear only) Signals the presence of an interrupt request for a channel Signals the presence of an error on a channel 0 31 Set Enable Request Reg (SERQR) Clear Interrupt Request Reg. (CINTR) Control Register (CR) Error Status Register (ESR) Clear Enable Request Reg. (CERQR) Clear Error Reg. (CERR) Ena. Request Reg Low (ERQRL) Ena. Error IRQ Reg Low (EEIRL) Set Enable Error Interrupt Reg. (SEEIR) Set Start Bit Reg. (SSBR) Clear Enable Error Interrupt Reg. (CEEIR) Clear Done Status Bit Reg. (CDSBR) Interrupt Request Low (INTRL) Error Low (ERRL) External Use 31

33 Peripherals: DMA Register and TCD Memory Map (1 of 2) 0 31 Priority Registers (PR) include capability for that channel to be preempted by a higher priority channel and priority assignment Channel 0 Priority Reg. Channel 1 Priority Reg. Channel 2 Priority Reg. Channel 3 Priority Reg. Channel 12 Priority Reg. Channel 13 Priority Reg. Channel 14 Priority Reg. Channel 15 Priority Reg. 16 Transfer Control Descriptors One per channel 8 words per TCD External Use 32

34 ASRC DMA Workflow: Support for Polling, Interrupt or DMA 48kHz Sample 1 OUTPUT INPUT 48kHz Sample 2 48kHz Sample 3 8kHz 24bit Sample 4 48kHz Sample 4 saddr (source address) = ASRC ASRDO saddr register (source address) = start of memory queue 48kHz Sample 5 daddr (destination addr.) = start of memory daddr (destination addr.) = ASRC ASRDI register 48kHz Sample 6 nbytes 8kHz 24bit = 4 Sample bytes 1 (minor loop size; # bytes nbytes per = request) 4 bytes (minor loop size; # bytes 48kHz per request) Sample 7 Input clock biter 8kHz = 24bit citer Sample = 302 (# minor loops in major biter loop) = citer = 5 (# minor Output loops clock in major loop) 48kHz Sample 8 d_req 8kHz 24bit = 0 Sample (keep 3 channel enabled after major d_req = loop) 0 (keep channel enabled after major 48kHz loop) Sample 9 48kHz Sample 10 ssize = 32 bits (read 4bytes per transfer) ssize = 32 bits (read 4bytes per transfer) 8kHz 24bit Sample 5 soff = 0 bytes (src. addr. increment after soff transfer) = 4 bytes (src. addr. increment after transfer) slast = 0 (disabled) slast = -20 (restart saddr to start when done) Input FIFO Output FIFO smod = 0 (disabled) smod Engine = 0 (disabled) ASRDI ASRDO dsize = 32 bits (write 4bytes per transfer) dsize = 32 bits (write 4bytes per transfer) doff = 4 bytes (add 0 to dest. addr after doff each = transfer) 0 bytes (add 0 to dest. addr after each transfer) dlast = -120 DMA bytes driven (restart (threshold) saddr to start dlast when = 0 done) bytes (disabled) DMA driven threshold dmod = 0 (disabled) dmod = 0 (disabled)... Channel N External Use 33

35 Chan0 Chan1 Chan2 Chan3 Chan4 Chan5 Chan6 Chan7 Chan8 Chan9 Chan10 Chan11 Chan12 Chan13 Chan14 Chan15 Peripherals: DMA Channel Arbitration Default is round-robin mode. Other options include: Fixed-priority arbitration Pro: Fastest latency for higher priorities. Prevents lower priority tasks from using too much DMA bandwidth in case of a high priority deadline Con: Potential to use up DMA bandwidth if a channel is always active in highest priority group Pre-emption Normally transfers must complete before another channel can initiate a transfer Fixed priority allows one level of preemption Note: 0 is lowest priority Example: Fixed Chan. Arbitration External Use 34

36 Vybrid Modules with DMA Support UART SPI PDB PORT SAI (I2S) ADC RLE FTM QSPI SPDIF I2C External Use 35

37 Review of Key Points DMA is often an alternative to CPU interrupt Peripheral flag causes DMA request to transfer data Multiple different transfers can take place with a single DMA request Allows combining multiple peripherals to a new super peripheral External Use 36

38 Example 2 and 3: DMA Usage Launch example 2 Enable DMA to perform memcpy Change from 32bit to 64bit transfers Launch example 3 Enable DMA to load data to SPI buffer External Use 37

39 Dual Core: M4 Core External Use 38

40 More on Processor Core Details ARM Cortex -M4 Real-Time Control Processor Operating at 1:1 clock ratio compared to platform Core frequencies = MHz 3-stage pipeline provides 1.25 DMIPS per MHz performance Includes single precision FPU, DSP & SIMD ISA extensions 16K code and 16K system caches with 32-byte cache line size 64 Kbytes of tightly-coupled memory split equally across TCM{L,U} Modified Harvard 64-bit AHB system bus interface 64-bit AHB backdoor port to TCMs CoreSight debug and trace system Nested Vector Interrupt Controller (NVIC) External Use 39

41 ARM Cortex-M4 Processor Pipeline External Use 40

42 Memory Map M4 core has a static 4GB linear memory map: Standard across all Cortex M cores Internal Private Peripheral Bus 0xFFFFFFFF 0xE INT SYS M4 Core CODE Internal/External RAM Internal/External Flash Peripherals 0x CODE ROM/RAM 0x External Use 41

43 Aliased Locations Often a subset of the full region e.g. QSPI Note that DRAM alias has an offset of 0x80_0000 M4 Alias 0x0080_0000 0x0FFF_FFFF 0x1000_0000-0x17FF_FFFF 0x1800_0000-0x1EFF_FFFF 0x1F00_0000-0x1F07_FFFF Memory Map Address 0x8080_0000 0xDFFF_FFFF 0x2000_0000-0x2FFF_FFFF 0x3000_0000-0x3EFF_FFFF 0x3F00_0000-0x3F07_FFFF Region Descriptor External DDR QSPI0 FlexBus OCRAM SysRAM0 and 1 External Use 42

44 M4 Local Memory Controller TCM SRAM blocks are 32KB each. RAM and Cache are 64bits Wide and provide zero wait state accesses External Use 43

45 Dual Core: Launching M4 External Use 44

46 Dual Core Example Create linker file to put M4 code at specific location 0x3f Also use linker file to define specific start address 0x3f In A5 projects settings, linker configuration pulls in M4 binary at specific location 0x3f In A5 code, set SRC->GPR2 to M4 execution start address 0x3f In A5 code, enable M4 clock: CCM->CCOWR = 0x15a5a Compile M4 project as flat binary Compile A5 project (which includes M4 code) and load into memory External Use 45

47 Dual Core Example Continued BootROM boots A5 core code A5 core configures clocks, DDR, and other basic init A5 core enables M4 clock A5 code continues M4 Code Starts External Use 46

48 Example 4: Dual Core Use secondary M4 core to execute the algorithm1() function in parallel Move the function to different memory locations and compare execution time External Use 47

49 M4 Cache External Use 48

Cache basics Cache is a fast local memory that contains a copy of the slower main memory Caches operate on two

adjacent locations (e.g. Sequential code/array).

code loop) To minimize the quantity of control information stored, the spatial locality property is used to

50 Cache basics Cache is a fast local memory that contains a copy of the slower main memory Caches operate on two principles of locality: Spatial locality An access to one location is likely to be followed by accesses from adjacent locations (e.g. Sequential code/array). Temporal locality An access to an area of memory is likely to be repeated within a short time period (e.g. code loop) To minimize the quantity of control information stored, the spatial locality property is used to group several locations together under the same tag. This logical block is commonly known as a cache line. Not all memory regions are suitable for caching Eg peripherals External Use 49

51 Cache terminology Line = smallest loadable unit of cache Index = part of memory address which is used to find the address in cache Way = subdivision of cache; all ways are same size Set = a group of lines with same index from different ways Tag = identifies main memory address of associated line M4 Code Cache: 16KB System Cache: 16KB Line Size: 32Bytes Ways: 2 External Use 50

52 Cache Modes Memory map divided into sections with a cache attribute: Attribute: Cache Write Miss Cache Write Hit Non-Cache Bus N/A Write Through Bus Cache and Bus Write Back Read-to-write Cache Example: Location Address Cache Attribute 0x4000_0000 0x4006_FFFF 0x3F00_0000 0x3F03_FFFF 0x0800_0000 0x0FFF_FFFF IPS0 - Peripherals OCRAM SysRAM0 DDR Alias Non-Cache Write Back Write Through External Use 51

53 Cache Potential Issues If another master accessed a cached location E.g. DMA, A5 If location could have been cached then perform a push operation to write modified cache lines back to bus External Use 52

54 M4 Cache Initialisation Cache is disabled by default. Steps to initialise: Invalidate both ways: LMEM_PxCCR[INVW1 and INVW0] Start invalidate using: LMEM_PxCCR[GO] Wait until bit is cleared Enable Cache using: LMEM_PCCR[ENCACHE] External Use 53

55 Example 5: Cache Enable Code and/or System Cache on the M4 core. Move the function to different memory locations and compare execution time External Use 54

56 Example 6: Revisiting Example 1 We can now apply the learning from Example 2-5 to our initial code. Open Example 6 and note A5 run time Try to perform further optimisations External Use 55

57 Freescale Semiconductor, Inc. External Use

Understanding Vybrid Architecture

Freescale Semiconductor, Inc. Application Note Document Number: AN4947 Rev. 0, 07/2014 Understanding Vybrid Architecture by Jiri Kotzian and Rastislav Pavlanin Vybrid controller solutions are built on