Effective System Design with ARM System IP
|
|
- Leon Tate
- 6 years ago
- Views:
Transcription
1 Effective System Design with ARM System IP Mentor Technical Forum 2009 Serge Poublan Product Marketing Manager ARM 1
2 Higher level of integration WiFi Platform OS Graphic 13 days standby Bluetooth MP3 Camera Flash MB DDR H.264 Skype 2
3 Processors are evolving, e.g. MP World-class market-proven technology 20+ processors for every application 200+ silicon partners 500+ licenses 15Bu shipped ARMv5 ARM968E-S ARM946E-S ARMv6 x1-4 ARM966E-S ARMv7 Cortex ARM1176JZ(F)-S ARM1156T2(F)-S ARM1136J(F)-S ARM1026EJ-S ARM926EJ-S ARM11 MPCore Cortex-A8 Cortex-R4 x1-4 Cortex-A9 Cortex-R4F ARM7EJ-S SC200 ARMv4 ARM7TDMI(S) ARM920T SC100 ARM922T Cortex-M3 Cortex-M1 SC300 Cortex-M0 3
4 ARM Mali GPU - Scalable Performance to over 1G Pixel/s Visual complexity Mali -400 MP Mali -200 Mali -55 Web Browsing Flash Lite Java Gaming Next Generation Navigation Mobile Gaming 3D Navigation Flash 10 TV HD UI Video Post Processing HD 3D Gaming Console 3D Gaming 2D/3D Presentations HD Video Post Processing Screen resolution 4
5 Higher Mobile Device Resolution Requirements of next generation Mobile platform - Increasing bandwidth requirements simply to refresh the display - Ignoring Fill rate, Input Vertex Data and Texture bandwidth 1080p x p x1080 WSVGA 1024x600 WXGA 1280x800 Display Refresh Bandwidth MB/s WVGA 800x p60, 1920x1080, 60fps p30, 1920x1080, 30fps 237 QVGA 320x240 VGA 640x p, 1280x720, 30fps 105 WVGA, 800x480, 30fps 44 VGA, 640x480, 30fps
6 Example SoC Mobile Platform CPU L2 CPU Cache L2CC L2CC Media Media Graphic Graphic Video Video DMA DMA LCD LCD 64 or 128 Bandwidth requirement Latency requirement Dynamic Dynamic Memory SDRAM Memory Controller Controller Static Static Memory Memory Interrupt Interrupt Controller Controller AMBA Interconnect LPDDR2 NAND Flash UART0 UART1 SPI WDT Timer0 Timer1 RTC GPIO 6
7 Example SoC Mobile Platform CPU L2 CPU Cache L2CC L2CC Media Media Graphic Graphic Video Video DMA DMA LCD LCD 64 or 128 AMBA Interconnect Dynamic Dynamic Memory SDRAM Memory Controller Controller Static Static Memory Memory Interrupt Interrupt Controller Controller LPDDR2 NAND Flash Digital Highway 7
8 ARM Design Flow for Digital Highway Design Your Intelligent Digital Highway Configure and connect your RTL AMBA Designer Verification & performance exploration in simulation AVIP Improve your software CoreSight 8
9 AMBA Ecosystem : The on-chip infrastructure is critical to system performance Increased focus on processor memory performance Different types of processors have different requirements ARM has grown the AMBA architecture eco-system to help accelerate SoC design: 70+ Connected Community partners have AMBA compatible products 10+ AMBA specification downloads a day the de facto standard is of course the ARM bus architecture, AMBA. Ron Wilson, EETimes 9
10 Design to Minimise Latency Each path must be designed to minimise the inherent pipeline latency Round trip memory latency Processor sub-system AXI Interconnect Dynamic Mem DDR2 PHY DDR2 SDRAM Address format and arbitration DDR2 SDRAM CAS latency De-skew and capture Data FIFO and bus interface Next generation AXI Interconnect halves the interconnect latency Masters which issue multiple AXI requests effectively hide latency PrimeCell Cache Controllers Trade an increase in minimum latency for dramatically reduced average latency 10
11 Design to Maximise Throughput Effective on-chip Quality of Service depends on the cooperation of the interconnect and memory controller Support for multiple outstanding requests The best use of memory pages by scanning the list of requests Controlling the order of queued transactions to Meet maximum latency targets Ensure throughput-dependent processors are well serviced Provide low latency paths 11
12 ARM Level2 Cache Controllers CPU CPU L2 L2 Cache Cache Media Media Graphic Graphic Video Video DMA DMA LCD LCD 64 or 128 AMBA Interconnect Dynamic Dynamic Memory SDRAM Memory Controller Controller Static Static Memory Memory Interrupt Interrupt Controller Controller LPDDR2 NAND Flash Digital Highway 12
13 L2CC Increases Processor Performance 512K L2 256K L2 128K L2 No L2 +104% +102% +74% Benchmark : MPEG4 decode System : ARM PrimeXsys Platform for ARM1136J-S CPU : 400MHz ARM1136J-S 16K I & D caches Memory : 100MHz 32 bit SDRAM L2 cache : L K unified L2 cache MPEG4 Decode on ARM1136EJ-S Relative performance Web Page Render Time as a function of L2 Cache Size L2 Cache Size (KB) First Time Subsequent Benchmark: Linux + Mozilla (5 html pages from I-Bench looped 4 times) CPU: Cortex-A8 (speed, L1 cache), L2 part of Cortex-A8 Results may vary for system configuration and web content Speed Up Compared to 0K L2 13
14 L2CC Increases System Performance Reduced System Power Consumption External memory access ~10x more energy than on-chip External memory accesses reduced with L2 cache Enables use of lower-power and lower-cost memory sub-system E.g. 16-bit instead of 32-bit external interface Or LPDDR instead of DDR2 Reduced On-Chip traffic & contention Only cache misses propagated to the interconnect Improve overall system performances Provide more bandwidth to others SoC components 14
15 ARM AMBA Interconnect Cortex Cortex A8 A8 L2CC L2CC Media Media Graphic Graphic Video Video DMA DMA LCD LCD 64 or 128 NIC-301 Dynamic Dynamic Memory SDRAM Memory Controller Controller Static Static Memory Memory Interrupt Interrupt Controller Controller LPDDR2 NAND Flash Digital Highway 15
16 AMBA Interconnect (NIC-301) Low latency communication for ARM CPUs High bandwidth for ARM Graphics and Video Supporting: AXI, AHB & APB Data widths from 32- to 128-bit Supporting both synchronous & GALS implementations Quality of service Configurable through AMBA Designer For minimum area & maximum frequency 16
17 Optimise your Interconnect Topology Real-time masters Real-time masters Cortex A9 Freq F Fx2.5 Cortex A9 RAM SMC DMC Fx2.5 Low bandwidth peripherals High connectivity & increasing numbers of IP cores does not scale with a single interconnect RAM SMC DMC Fx2.5 Low bandwidth peripherals Use properties of the traffic to influence the topology 17
18 Topology Optimisation with ARM Interconnect Cortex Cortex L2CC L2CC Neon Neon Graphic Graphic Video Video DMA DMA LCD LCD 64 or 128 NIC MHz Low Latency Interconnect NIC MHz Dynamic Dynamic Memory SDRAM Memory Controller Controller Static Static Memory Memory Interrupt Interrupt Controller Controller LPDDR2 NAND Flash 18
19 ARM Memory Controllers Cortex Cortex L2CC L2CC Neon Neon Graphic Graphic Video Video DMA DMA LCD LCD 64 or 128 Low Latency Interconnect DMC-34x DMC-34x SDRA M SMC-35x SMC-35x Interrupt Interrupt Controller Controller LPDDR2 NAND Flash 19
20 ARM Memory Controllers Synthesizable, Configurable soft cores Wide range of memory types, silicon processes & target applications AXI Dynamic Memory Controllers for SDR, DDR, LPDDR, DDR2 and LPDDR2 (DMC-34x) Over 20 licensees to date AXI Static Memory Controllers for NOR Flash, NAND Flash and SRAM (SMC-35x) Over 40 licensees to date AHB Memory Controllers for Dynamic and Static Memories (PL24x) Over 60 licensees to date 20
21 ARM Design Flow for Digital Highway Design Your Intelligent Digital Highway Configure and connect your RTL AMBA Designer Verification & performance exploration in simulation AVIP Improve your software CoreSight 21
22 What is AMBA Designer? Topolology Configure Cross-configure Stitch & Check 22
23 What is AMBA Designer? Topolology Configure Interface checking on: Signal widths Signal direction Interface properties Valid response types Interleave depth Cross-configure Stitch & Check (Export as individual signals) 23
24 ARM Design Flow for Digital Highway Design Your Intelligent Digital Highway Configure and connect your RTL AMBA Designer Verification & performance exploration in simulation AVIP Improve your software CoreSight 24
25 AVIP Features for RTL Simulation Functional IEEE 1800 SystemVerilog Testbench Verification For Verification ers, AVIP is a set of System Verilog modules that enable faster and higher quality verification of AXI based IP. Performance Exploration For SoC architects, HW and Verification ers. AXI based SoC performance can be explored and verified. 25 Directed Prof. Vectors Data AXI Master User VIP AXI Master AXI Slave Interface AXI Master Interface UUT User (Block or Sub-system) AXI Slave Interface AXI Master Interface AXI Slave AXI Monitor User IP Prof. Data
26 AVIP Features for RTL Simulation Protocol Checkers OVL and SVA assertion libraries provided for AXI protocol checking. IEEE 1800 SystemVerilog Testbench AXI Master User VIP AXI Master AXI Protocol Coverage Channel level, transaction level and sequence level predefined coverage points for AXI protocol coverage. 26 AXI Slave Interface AXI Master Interface UUT User (Block or Sub-system) AXI Slave Interface AXI Master Interface AXI Slave AXI Monitor User IP
27 AMBA Designer + AVIP: RTL Design Flow To optimise interconnect and memory architecture ARM recommends the following flow: Configuration Set the correct parameters and check 27 the components Integration Assemble the sub-system and statically check the design Simulation Run test scenarios to check usage modes Analysis Check results and loop back Configuration Configuration Integration Integration Simulation Simulation Analysis Analysis
28 Fabric Design Tools: What is AVIP? IEEE 1800 SystemVerilog Testbench AXI Slave Interface AXI Master Interface AXI Slave AXI Master User VIP UUT User (Block or Sub-system) AXI Slave Interface AXI Master 28 AXI Master Interface AXI Monitor User IP
29 Fabric Design Tools: What is AVIP? 29 It enables System Exploration at RTL level TTT = Time to tweak = 20s TTS = Time to simulate = 5 mins
30 System Exploration Methods SoC, static Spreadsheet Analysis Block-level, Internal bus, RTL simulation RTL simulation, AVIP, User VIP Industry standards VIP SoC, Real Stimulus, external I/F Acceleration/Emulation VIP, Logic Tiles, SW Real-time Behavior Silicon/Applications 30
31 Iteration time vs Realism LOW mins/hrs Cycle time days/wks mths/yrs HIGH AVIP Internal bus simulation Mathematical formula, not dynamic Statistical or recorded traffic profiles SoC + s/w Emulation/proto Adding S/W, external I/F with realistic scenarios Silicon + Appl CoreSight Observe actual behaviour LOW Realistic behaviour mins/hrs Spreadsheet Static analysis HIGH AVIP: the iteration time of a spreadsheet with the accuracy approaching RTL simulation 31
32 ARM Design Flow for Digital Highway Design Your Intelligent Digital Highway Configure and connect your RTL AMBA Designer Verification & performance exploration in simulation AVIP Improve your software CoreSight 32
33 Improve the Performance of Your SoC Analyzing real silicon performance enables you to confidently improve the next design If you want to find out how a car really performs, drive it CoreSight Design Kit & Performance Profiling Provide accurate, real-time telemetry from your system Essential tools for delivering system performance improvements Your SoC may be optimized, but is the software? ARM Profiler analyzes system performance, enabling optimization via Profile Driven Compilation 33
34 CoreSight Debug & Trace The Debug & Trace Architecture for the Digital World Open Standard available on Optimise software productivity on your multi-core SoC SW Debug SW Performance Optimisation SoC Performance optimisation Visibility and trace of the whole SoC ARM trace and performance sources (ETM, PTM, Interconnect) Leverage CoreSight architecture for YOUR IP 34
35 ARM Digital Highway ARM Digital Highway technology delivers to YOU Key Soft IP and Physical IP elements The de-facto communication standard Tools to analyze and optimize your system design before committing to silicon AVIP Solution to debug and optimise once your silicon has been manufactured Faster time to revenue through reducing design effort and ensuring quality of results 35
The Challenges of System Design. Raising Performance and Reducing Power Consumption
The Challenges of System Design Raising Performance and Reducing Power Consumption 1 Agenda The key challenges Visibility for software optimisation Efficiency for improved PPA 2 Product Challenge - Software
More informationGrowth outside Cell Phone Applications
ARM Introduction Growth outside Cell Phone Applications ~1B units shipped into non-mobile applications Embedded segment now accounts for 13% of ARM shipments Automotive, microcontroller and smartcards
More informationBuilding High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink. Robert Kaye
Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink Robert Kaye 1 Agenda Once upon a time ARM designed systems Compute trends Bringing it all together with CoreLink 400
More informationPerformance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models. Jason Andrews
Performance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models Jason Andrews Agenda System Performance Analysis IP Configuration System Creation Methodology: Create,
More informationOptimizing ARM SoC s with Carbon Performance Analysis Kits. ARM Technical Symposia, Fall 2014 Andy Ladd
Optimizing ARM SoC s with Carbon Performance Analysis Kits ARM Technical Symposia, Fall 2014 Andy Ladd Evolving System Requirements Processor Advances big.little Multicore Unicore DSP Cortex -R7 Block
More informationGetting the Most out of Advanced ARM IP. ARM Technology Symposia November 2013
Getting the Most out of Advanced ARM IP ARM Technology Symposia November 2013 Evolving System Requirements Processor Advances big.little Multicore Unicore DSP Cortex -R7 Block are now Sub-Systems Cortex
More informationExploring System Coherency and Maximizing Performance of Mobile Memory Systems
Exploring System Coherency and Maximizing Performance of Mobile Memory Systems Shanghai: William Orme, Strategic Marketing Manager of SSG Beijing & Shenzhen: Mayank Sharma, Product Manager of SSG ARM Tech
More informationAHB monitor. Monitor. AHB bridge. Expansion AHB ports M1, M2, and S. AHB bridge. AHB bridge. Configuration. Smart card reader SSP (PL022)
The ARM RealView Versatile family of development boards provide a feature rich prototyping system for system-on-chip designs. This family includes the first development board to support both the ARM926EJ-S
More informationModeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces
Modeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces Li Chen, Staff AE Cadence China Agenda Performance Challenges Current Approaches Traffic Profiles Intro Traffic Profiles Implementation
More informationMulti-core microcontroller design with Cortex-M processors and CoreSight SoC
Multi-core microcontroller design with Cortex-M processors and CoreSight SoC Joseph Yiu, ARM Ian Johnson, ARM January 2013 Abstract: While the majority of Cortex -M processor-based microcontrollers are
More informationAnalyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components
Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components By William Orme, Strategic Marketing Manager, ARM Ltd. and Nick Heaton, Senior Solutions Architect, Cadence Finding
More informationCMP Conference 20 th January Director of Business Development EMEA
CMP Conference 20 th January 2011 eric.lalardie@arm.com Director of Business Development EMEA +33 6 07 83 09 60 1 1 Unparalleled Applicability ARM Cortex Advanced Processors Architectural innovation, compatibility
More informationSYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS
SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS Embedded System System Set of components needed to perform a function Hardware + software +. Embedded Main function not computing Usually not autonomous
More informationBuilding blocks for 64-bit Systems Development of System IP in ARM
Building blocks for 64-bit Systems Development of System IP in ARM Research seminar @ University of York January 2015 Stuart Kenny stuart.kenny@arm.com 1 2 64-bit Mobile Devices The Mobile Consumer Expects
More informationCopyright 2016 Xilinx
Zynq Architecture Zynq Vivado 2015.4 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: Identify the basic building
More informationThe ARM Cortex-A9 Processors
The ARM Cortex-A9 Processors This whitepaper describes the details of the latest high performance processor design within the common ARM Cortex applications profile ARM Cortex-A9 MPCore processor: A multicore
More informationSoC Platforms and CPU Cores
SoC Platforms and CPU Cores COE838: Systems on Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University
More informationContents of this presentation: Some words about the ARM company
The architecture of the ARM cores Contents of this presentation: Some words about the ARM company The ARM's Core Families and their benefits Explanation of the ARM architecture Architecture details, features
More informationZynq-7000 All Programmable SoC Product Overview
Zynq-7000 All Programmable SoC Product Overview The SW, HW and IO Programmable Platform August 2012 Copyright 2012 2009 Xilinx Introducing the Zynq -7000 All Programmable SoC Breakthrough Processing Platform
More informationCoreTile Express for Cortex-A5
CoreTile Express for Cortex-A5 For the Versatile Express Family The Versatile Express family development boards provide an excellent environment for prototyping the next generation of system-on-chip designs.
More informationNegotiating the Maze Getting the most out of memory systems today and tomorrow. Robert Kaye
Negotiating the Maze Getting the most out of memory systems today and tomorrow Robert Kaye 1 System on Chip Memory Systems Systems use external memory Large address space Low cost-per-bit Large interface
More informationARM Connected Community Technical Symposium Reaching High Performance System Design Using AMBA Fabric IP
ARM Connected Community Technical Symposium Reaching High Performance System Design Using AMBA Fabric IP Tim Mace Senior Technical Marketing Manager Fabric IP BU, ARM 1 What is Fabric IP? Fabric IP is:
More informationDesign Choices for FPGA-based SoCs When Adding a SATA Storage }
U4 U7 U7 Q D U5 Q D Design Choices for FPGA-based SoCs When Adding a SATA Storage } Lorenz Kolb & Endric Schubert, Missing Link Electronics Rudolf Usselmann, ASICS World Services Motivation for SATA Storage
More informationProduct Technical Brief S3C2413 Rev 2.2, Apr. 2006
Product Technical Brief Rev 2.2, Apr. 2006 Overview SAMSUNG's is a Derivative product of S3C2410A. is designed to provide hand-held devices and general applications with cost-effective, low-power, and
More informationYafit Snir Arindam Guha Cadence Design Systems, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces
Yafit Snir Arindam Guha, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and
More informationARM Processors for Embedded Applications
ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or
More informationDesigning with ALTERA SoC Hardware
Designing with ALTERA SoC Hardware Course Description This course provides all theoretical and practical know-how to design ALTERA SoC devices under Quartus II software. The course combines 60% theory
More information3D Graphics in Future Mobile Devices. Steve Steele, ARM
3D Graphics in Future Mobile Devices Steve Steele, ARM Market Trends Mobile Computing Market Growth Volume in millions Mobile Computing Market Trends 1600 Smart Mobile Device Shipments (Smartphones and
More informationHardware Software Bring-Up Solutions for ARM v7/v8-based Designs. August 2015
Hardware Software Bring-Up Solutions for ARM v7/v8-based Designs August 2015 SPMI USB 2.0 SLIMbus RFFE LPDDR 2 LPDDR 3 emmc 4.5 UFS SD 3.0 SD 4.0 UFS Bare Metal Software DSP Software Bare Metal Software
More informationMultimedia in Mobile Phones. Architectures and Trends Lund
Multimedia in Mobile Phones Architectures and Trends Lund 091124 Presentation Henrik Ohlsson Contact: henrik.h.ohlsson@stericsson.com Working with multimedia hardware (graphics and displays) at ST- Ericsson
More informationNS115 System Emulation Based on Cadence Palladium XP
NS115 System Emulation Based on Cadence Palladium XP wangpeng 新岸线 NUFRONT Agenda Background and Challenges Porting ASIC to Palladium XP Software Environment Co Verification and Power Analysis Summary Background
More informationSPEAr: an HW/SW reconfigurable multi processor architecture
Welcome to the «SPEAr Age» Structured Processor Enhanced Architecture SPEAr: an HW/SW reconfigurable multi processor architecture COMPUTER PERIPHERAL GROUP Outline Economics of Moore s law and market view
More informationHotChips An innovative HD video and digital image processor for low-cost digital entertainment products. Deepu Talla.
HotChips 2007 An innovative HD video and digital image processor for low-cost digital entertainment products Deepu Talla Texas Instruments 1 Salient features of the SoC HD video encode and decode using
More informationChapter 6 Storage and Other I/O Topics
Department of Electr rical Eng ineering, Chapter 6 Storage and Other I/O Topics 王振傑 (Chen-Chieh Wang) ccwang@mail.ee.ncku.edu.tw ncku edu Feng-Chia Unive ersity Outline 6.1 Introduction 6.2 Dependability,
More informationARM s IP and OSCI TLM 2.0
ARM s IP and OSCI TLM 2.0 Deploying Implementations of IP at the Programmer s View abstraction level via RealView System Generator ESL Marketing and Engineering System Design Division ARM Q108 1 Contents
More informationProduct Technical Brief S3C2416 May 2008
Product Technical Brief S3C2416 May 2008 Overview SAMSUNG's S3C2416 is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation
More informationThe Use Of Virtual Platforms In MP-SoC Design. Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006
The Use Of Virtual Platforms In MP-SoC Design Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006 1 MPSoC Is MP SoC design happening? Why? Consumer Electronics Complexity Cost of ASIC Increased SW Content
More informationSoftware Driven Verification at SoC Level. Perspec System Verifier Overview
Software Driven Verification at SoC Level Perspec System Verifier Overview June 2015 IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to
More informationCreating hybrid FPGA/virtual platform prototypes
Creating hybrid FPGA/virtual platform prototypes Know how to use the PCIe-over-Cabling interface in its HAPS-60-based system to create a new class of hybrid prototypes. By Troy Scott Product Marketing
More informationARM instruction sets and CPUs for wide-ranging applications
ARM instruction sets and CPUs for wide-ranging applications Chris Turner Director, CPU technology marketing ARM Tech Forum Taipei July 4 th 2017 ARM computing is everywhere #1 shipping GPU in the world
More informationVeloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics
Veloce2 the Enterprise Verification Platform Simon Chen Emulation Business Development Director Mentor Graphics Agenda Emulation Use Modes Veloce Overview ARM case study Conclusion 2 Veloce Emulation Use
More informationTest and Verification Solutions. ARM Based SOC Design and Verification
Test and Verification Solutions ARM Based SOC Design and Verification 7 July 2008 1 7 July 2008 14 March 2 Agenda System Verification Challenges ARM SoC DV Methodology ARM SoC Test bench Construction Conclusion
More informationHi Hsiao-Lung Chan, Ph.D. Dept Electrical Engineering Chang Gung University, Taiwan
Processors Hi Hsiao-Lung Chan, Ph.D. Dept Electrical Engineering Chang Gung University, Taiwan chanhl@maili.cgu.edu.twcgu General-purpose p processor Control unit Controllerr Control/ status Datapath ALU
More informationSoftware Defined Modem A commercial platform for wireless handsets
Software Defined Modem A commercial platform for wireless handsets Charles F Sturman VP Marketing June 22 nd ~ 24 th Brussels charles.stuman@cognovo.com www.cognovo.com Agenda SDM Separating hardware from
More informationProduct Technical Brief S3C2412 Rev 2.2, Apr. 2006
Product Technical Brief S3C2412 Rev 2.2, Apr. 2006 Overview SAMSUNG's S3C2412 is a Derivative product of S3C2410A. S3C2412 is designed to provide hand-held devices and general applications with cost-effective,
More informationFujitsu SOC Fujitsu Microelectronics America, Inc.
Fujitsu SOC 1 Overview Fujitsu SOC The Fujitsu Advantage Fujitsu Solution Platform IPWare Library Example of SOC Engagement Model Methodology and Tools 2 SDRAM Raptor AHB IP Controller Flas h DM A Controller
More informationFPGA Adaptive Software Debug and Performance Analysis
white paper Intel Adaptive Software Debug and Performance Analysis Authors Javier Orensanz Director of Product Management, System Design Division ARM Stefano Zammattio Product Manager Intel Corporation
More informationSoC FPGAs. Your User-Customizable System on Chip Altera Corporation Public
SoC FPGAs Your User-Customizable System on Chip Embedded Developers Needs Low High Increase system performance Reduce system power Reduce board size Reduce system cost 2 Providing the Best of Both Worlds
More informationECE 471 Embedded Systems Lecture 2
ECE 471 Embedded Systems Lecture 2 Vince Weaver http://www.eece.maine.edu/~vweaver vincent.weaver@maine.edu 3 September 2015 Announcements HW#1 will be posted today, due next Thursday. I will send out
More informationIntelop. *As new IP blocks become available, please contact the factory for the latest updated info.
A FPGA based development platform as part of an EDK is available to target intelop provided IPs or other standard IPs. The platform with Virtex-4 FX12 Evaluation Kit provides a complete hardware environment
More informationVerification Futures Nick Heaton, Distinguished Engineer, Cadence Design Systems
Verification Futures 2016 Nick Heaton, Distinguished Engineer, Cadence Systems Agenda Update on Challenges presented in 2015, namely Scalability of the verification engines The rise of Use-Case Driven
More informationValidation Strategies with pre-silicon platforms
Validation Strategies with pre-silicon platforms Shantanu Ganguly Synopsys Inc April 10 2014 2014 Synopsys. All rights reserved. 1 Agenda Market Trends Emulation HW Considerations Emulation Scenarios Debug
More informationIt's not about the core, it s about the system
It's not about the core, it s about the system Gajinder Panesar, CTO, UltraSoC gajinder.panesar@ultrasoc.com RISC-V Workshop 18 19 July 2018 Chennai, India Overview Architecture overview Example Scenarios
More informationSoC Design Lecture 11: SoC Bus Architectures. Shaahin Hessabi Department of Computer Engineering Sharif University of Technology
SoC Design Lecture 11: SoC Bus Architectures Shaahin Hessabi Department of Computer Engineering Sharif University of Technology On-Chip bus topologies Shared bus: Several masters and slaves connected to
More informationECE 471 Embedded Systems Lecture 3
ECE 471 Embedded Systems Lecture 3 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 10 September 2018 Announcements New classroom: Stevens 365 HW#1 was posted, due Friday Reminder:
More informationNew STM32 F7 Series. World s 1 st to market, ARM Cortex -M7 based 32-bit MCU
New STM32 F7 Series World s 1 st to market, ARM Cortex -M7 based 32-bit MCU 7 Keys of STM32 F7 series 2 1 2 3 4 5 6 7 First. ST is first to sample a fully functional Cortex-M7 based 32-bit MCU : STM32
More informationThe Bifrost GPU architecture and the ARM Mali-G71 GPU
The Bifrost GPU architecture and the ARM Mali-G71 GPU Jem Davies ARM Fellow and VP of Technology Hot Chips 28 Aug 2016 Introduction to ARM Soft IP ARM licenses Soft IP cores (amongst other things) to our
More informationOptimizing Cache Coherent Subsystem Architecture for Heterogeneous Multicore SoCs
Optimizing Cache Coherent Subsystem Architecture for Heterogeneous Multicore SoCs Niu Feng Technical Specialist, ARM Tech Symposia 2016 Agenda Introduction Challenges: Optimizing cache coherent subsystem
More informationIMPROVES. Initial Investment is Low Compared to SoC Performance and Cost Benefits
NOC INTERCONNECT IMPROVES SOC ECONO CONOMICS Initial Investment is Low Compared to SoC Performance and Cost Benefits A s systems on chip (SoCs) have interconnect, along with its configuration, verification,
More informationAsynchronous on-chip Communication: Explorations on the Intel PXA27x Peripheral Bus
Asynchronous on-chip Communication: Explorations on the Intel PXA27x Peripheral Bus Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan John Bainbridge, John R. Mawer, David L. Jackson, Andrew
More informationJazelle. The ARM Architecture. NeON. Thumb
ARM Processor Guide ARM is the industry's leading provider of 32-bit embedded RISC microprocessors. ARM processors are licensed by the majority of the word's leading semiconductor manufacturers, who together
More informationAMBA Protocol for ALU
International Journal of Emerging Engineering Research and Technology Volume 2, Issue 5, August 2014, PP 51-59 ISSN 2349-4395 (Print) & ISSN 2349-4409 (Online) AMBA Protocol for ALU K Swetha Student, Dept
More informationOverview of Development Tools for the ARM Cortex -A8 Processor George Milne March 2006
Overview of Development Tools for the ARM Cortex -A8 Processor George Milne March 2006 Introduction ARM launched the Cortex-A8 CPU in October 2005, for consumer products requiring power efficient multi-media
More informationCannon Mountain Dr Longmont, CO LS6410 Hardware Design Perspective
LS6410 Hardware Design Perspective 1. S3C6410 Introduction The S3C6410X is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, lowpower capabilities, high performance Application
More informationEach Milliwatt Matters
Each Milliwatt Matters Ultra High Efficiency Application Processors Govind Wathan Product Manager, CPG ARM Tech Symposia China 2015 November 2015 Ultra High Efficiency Processors Used in Diverse Markets
More informationDevelopment of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications
Session 8D-2 Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi,
More informationZynq Architecture, PS (ARM) and PL
, PS (ARM) and PL Joint ICTP-IAEA School on Hybrid Reconfigurable Devices for Scientific Instrumentation Trieste, 1-5 June 2015 Fernando Rincón Fernando.rincon@uclm.es 1 Contents Zynq All Programmable
More informationDesign Techniques for Implementing an 800MHz ARM v5 Core for Foundry-Based SoC Integration. Faraday Technology Corp.
Design Techniques for Implementing an 800MHz ARM v5 Core for Foundry-Based SoC Integration Faraday Technology Corp. Table of Contents 1 2 3 4 Faraday & FA626TE Overview Why We Need an 800MHz ARM v5 Core
More informationPlace Your Logo Here. K. Charles Janac
Place Your Logo Here K. Charles Janac President and CEO Arteris is the Leading Network on Chip IP Provider Multiple Traffic Classes Low Low cost cost Control Control CPU DSP DMA Multiple Interconnect Types
More informationDesigning, developing, debugging ARM Cortex-A and Cortex-M heterogeneous multi-processor systems
Designing, developing, debugging ARM and heterogeneous multi-processor systems Kinjal Dave Senior Product Manager, ARM ARM Tech Symposia India December 7 th 2016 Topics Introduction System design Software
More informationProduct Technical Brief S3C2440X Series Rev 2.0, Oct. 2003
Product Technical Brief S3C2440X Series Rev 2.0, Oct. 2003 S3C2440X is a derivative product of Samsung s S3C24XXX family of microprocessors for mobile communication market. The S3C2440X s main enhancement
More informationECE 471 Embedded Systems Lecture 2
ECE 471 Embedded Systems Lecture 2 Vince Weaver http://www.eece.maine.edu/ vweaver vincent.weaver@maine.edu 4 September 2014 Announcements HW#1 will be posted tomorrow (Friday), due next Thursday Working
More informationTechniques for Optimizing Performance and Energy Consumption: Results of a Case Study on an ARM9 Platform
Techniques for Optimizing Performance and Energy Consumption: Results of a Case Study on an ARM9 Platform BL Standard IC s, PL Microcontrollers October 2007 Outline LPC3180 Description What makes this
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP General Description The Digital Blocks LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to a 4K and
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP -UHD General Description The Digital Blocks -UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect
More informationMobile & IoT Market Trends and Memory Requirements
Mobile & IoT Market Trends and Memory Requirements JEDEC Mobile & IOT Forum Daniel Heo ARM Segment Marketing Copyright ARM 2016 Outline Wearable & IoT Market Opportunities Challenges in Wearables & IoT
More informationModular ARM System Design
An ARM Approved Training Partner for more than 7 years, Doulos has delivered ARM training in more than half of the world's top ten semiconductor companies. Doulos is the only ARM Approved Training partner
More informationFPGA Entering the Era of the All Programmable SoC
FPGA Entering the Era of the All Programmable SoC Ivo Bolsens, Senior Vice President & CTO Page 1 Moore s Law: The Technology Pipeline Page 2 Industry Debates on Cost Page 3 Design Cost Estimated Chip
More informationSQLoC: Using SQL database for performance analysis of an ARM v8 SoC
SQLoC: Using SQL database for performance analysis of an ARM v8 SoC Gordon Allan and Avidan Efody Mentor Graphics Agenda The performance analysis problem Run time & design time configuration Use cases
More informationA 1-GHz Configurable Processor Core MeP-h1
A 1-GHz Configurable Processor Core MeP-h1 Takashi Miyamori, Takanori Tamai, and Masato Uchiyama SoC Research & Development Center, TOSHIBA Corporation Outline Background Pipeline Structure Bus Interface
More informationAnalyze system performance using IWB. Interconnect Workbench Dave Huang
Analyze system performance using IWB Interconnect Workbench Dave Huang Perf_analysis@126.com 1 Information Personal peech of personal experience I am on behalf on myself Interconnects Are at the Heart
More informationWill Everything Start To Look Like An SoC?
Will Everything Start To Look Like An SoC? Vikas Gautam, Synopsys Verification Futures Conference 2013 Bangalore, India March 2013 Synopsys 2012 1 SystemVerilog Inherits the Earth e erm SV urm AVM 1.0/2.0/3.0
More informationMobile & IoT Market Trends and Memory Requirements
Mobile & IoT Market Trends and Memory Requirements JEDEC Mobile & IOT Forum Copyright 2016 [ARM Inc.] Outline Wearable & IoT Market Opportunity Challenges in Wearables & IoT Market ARM technology tackles
More informationIntroduction CHAPTER IN THIS CHAPTER
CHAPTER Introduction 1 IN THIS CHAPTER What Is the ARM Cortex-M3 Processor?... 1 Background of ARM and ARM Architecture... 2 Instruction Set Development... 7 The Thumb-2 Technology and Instruction Set
More informationARMed for Automotive. Table of Contents. SHARP and ARM Automotive Segments SHARP Target Applications SHARP Devices SHARP Support Network Summary
ARMed for Automotive Gunter Wagschal Table of Contents SHARP and ARM Automotive Segments SHARP Target Applications SHARP Devices SHARP Support Network Summary 1 SHARP and ARM 1993 - SHARP becomes the third
More informationCopyright 2014 Xilinx
IP Integrator and Embedded System Design Flow Zynq Vivado 2014.2 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able
More informationARM Mali -400 MP. The Scalable Multicore Graphics Processing Unit. Under embargo until June 2 nd, 2008
ARM Mali -400 MP The Scalable Multicore Graphics Processing Unit 1 Agenda Market drivers: consumer and technology changes ARM technology and graphics expertise ARM launches pioneering Mali-400 MP GPU Mali-400
More informationMYC-C7Z010/20 CPU Module
MYC-C7Z010/20 CPU Module - 667MHz Xilinx XC7Z010/20 Dual-core ARM Cortex-A9 Processor with Xilinx 7-series FPGA logic - 1GB DDR3 SDRAM (2 x 512MB, 32-bit), 4GB emmc, 32MB QSPI Flash - On-board Gigabit
More informationS2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
More informationIntegrating CPU and GPU, The ARM Methodology. Edvard Sørgård, Senior Principal Graphics Architect, ARM Ian Rickards, Senior Product Manager, ARM
Integrating CPU and GPU, The ARM Methodology Edvard Sørgård, Senior Principal Graphics Architect, ARM Ian Rickards, Senior Product Manager, ARM The ARM Business Model Global leader in the development of
More informationThe Cortex-A15 Verification Story
The Cortex-A15 Verification Story Bill Greene Micah McDaniel December 7, 2011 1 2 WHAT IS CORTEX-A15? Cortex-A15: Next Generation Leadership Cortex-A class multi-processor 40bit physical addressing (1TB)
More informationDesigning with NXP i.mx8m SoC
Designing with NXP i.mx8m SoC Course Description Designing with NXP i.mx8m SoC is a 3 days deep dive training to the latest NXP application processor family. The first part of the course starts by overviewing
More informationMali-400 MP: A Scalable GPU for Mobile Devices Tom Olson
Mali-400 MP: A Scalable GPU for Mobile Devices Tom Olson Director, Graphics Research, ARM Outline ARM and Mobile Graphics Design Constraints for Mobile GPUs Mali Architecture Overview Multicore Scaling
More informationCombining Arm & RISC-V in Heterogeneous Designs
Combining Arm & RISC-V in Heterogeneous Designs Gajinder Panesar, CTO, UltraSoC gajinder.panesar@ultrasoc.com RISC-V Summit 3 5 December 2018 Santa Clara, USA Problem statement Deterministic multi-core
More informationIntroduction to Sitara AM437x Processors
Introduction to Sitara AM437x Processors AM437x: Highly integrated, scalable platform with enhanced industrial communications and security AM4376 AM4378 Software Key Features AM4372 AM4377 High-performance
More information100M Gate Designs in FPGAs
100M Gate Designs in FPGAs Fact or Fiction? NMI FPGA Network 11 th October 2016 Jonathan Meadowcroft, Cadence Design Systems Why in the world, would I do that? ASIC replacement? Probably not! Cost prohibitive
More informationKeyStone C665x Multicore SoC
KeyStone Multicore SoC Architecture KeyStone C6655/57: Device Features C66x C6655: One C66x DSP Core at 1.0 or 1.25 GHz C6657: Two C66x DSP Cores at 0.85, 1.0, or 1.25 GHz Fixed and Floating Point Operations
More informationHardware Design. MicroBlaze 7.1. This material exempt per Department of Commerce license exception TSU Xilinx, Inc. All Rights Reserved
Hardware Design MicroBlaze 7.1 This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: List the MicroBlaze 7.1 Features List
More informationBuilding Ultra-Low Power Wearable SoCs
Building Ultra-Low Power Wearable SoCs 1 Wearable noun An item that can be worn adjective Easy to wear, suitable for wearing 2 Wearable Opportunity: Fastest Growing Market Segment Projected Growth from
More informationEvolving IP configurability and the need for intelligent IP configuration
Evolving IP configurability and the need for intelligent IP configuration Mayank Sharma Product Manager ARM Tech Symposia India December 7 th 2016 Increasing IP integration costs per node $140 $120 $M
More information