Design Choices for FPGA-based SoCs When Adding a SATA Storage }
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1 U4 U7 U7 Q D U5 Q D Design Choices for FPGA-based SoCs When Adding a SATA Storage } Lorenz Kolb & Endric Schubert, Missing Link Electronics Rudolf Usselmann, ASICS World Services
2 Motivation for SATA Storage for FPGA based SoCs ARM Cortex A9MP CPUs: fast enough to run rich OS and software Wide range of applications require I/O and signal processing flexibility Data-Logging Test & Measurement Advanced Driver Assist Systems (ADAS) Telematics Machine Visioning Broadcasting Applications FPGA based SoC a flexible and cost efficient alternative to embedded PCs Leave Your PC Behind! Altera SoC Xilinx ZYNQ 27 February
3 Storage Solutions for FPGA based SoCs FPGA Design Requirements Flexibility USB Thumbdrives Compact Flash SD Cards SSD USB 2.0 OTG built-in into most devices Consumer driven, plenty of devices available 3 rd party IP core with parallel I/O; needs many FPGA pins Less often used, past it s prime SDIO built-in into most devices Consumer driven, plenty of devices available Capacity Typ. 16 GB Typ. 64 GB Typ. 64 GB >256 GB 3 rd party IP core, needs Gigabit transceivers Consumer driven, plenty of devices available, future proof Performance 30 MB/s 133 MB/s < 100 MB/s > 400 MB/s Design Cost No extra cost Extra cost of 3 rd party IP core, needs extra FPGA resources No extra cost Extra cost of 3rd party SATA AHCI IP core, needs extra FPGA resources 27 February
4 Trends for Solid State Drives 27 February
5 SATA Backgrounder Standards Body Official naming In-official naming Netto-Datarate Serial ATA 1.5 Gbit/s SATA I 150 MB/s Serial ATA 3.0 Gbit/s, SATA Revision 2.x SATA II, SATA MB/s Serial ATA 6.0 Gbit/s, SATA Revision 3.x SATA III, SATA MB/s Performance Aspects Bandwidth (MB per second) read vs. write, sequential vs. random access, compression or not IOPs (I/O operations per second) Defined by Flash cell types, host and device controller 27 February
6 SATA Protocol By default, one Frame Information Structure (FIS) packet gets transferred after the other using standard Direct Memory Access (DMA). With Native Command Queuing (NCQ), FIS packets can be transferred in an interleaving fashion using First-Party DMA (FPDMA). 27 February
7 Importance of FPDMA / NCQ Transfer Speed (IOPS) Transfer Speed (MB/s) Queue Size Queue Size 27 February
8 SATA Functionality Layers Functionality Description Design Aspect Application software development GNU/Linux Operating System Custom Device Driver SATA AHCI IP Core Built-in FPGA high-speed Gigabit Transceivers 27 February
9 Architecture Option 1: Built-in PL330 DMA Controller Full functionality but very limited performance without hardware support for NCQ Scatter-Gather support needs software work for Linux Processing System I/O MUX 2x SPI 2x I2C 2x CAN 2x UART GPIO 2x SDIO 2x USB 2x GigE Static Memory Controller Quad-SPI, NAND, NOR AMBA Switches Cortex -A9 MPCore MIO 32/32 KB I/D Caches Dynamic Memory Controller DDR3, DDR2, LPDDR2 ARM CoreSight Multi-core & Trace Debug NEON / FPU Engine 512 KB L2 Cache Timer Counters AMBA Switches NEON / FPU Engine Cortex -A9 MPCore 32/32 KB I/D Caches Snoop Control Unit (SCU) 256 KB On-Chip Memory General Interrupt Controller DMA Configuration AMBA AMBA Switches Switches ACP Programmable Logic: System Gates, DSP, RAM Shadow Register CRC Checker SATA HCI Transport FIS Construct Link FIS Decomp CRC Generate Scrambler Descrambler 8b/10b Encoder OOB Phy 8b/10b Decoder Speed Negotiate 27 February
10 Architecture Option 2: 3 rd Party Scatter-Gather DMA Controller Significantly better performance, but does not max out SSD! SSDs internal structure demands NCQ for full R/W performance Processing System I/O MUX 2x SPI 2x I2C 2x CAN 2x UART GPIO 2x SDIO 2x USB 2x GigE Static Memory Controller Quad-SPI, NAND, NOR AMBA Switches Cortex -A9 MPCore MIO 32/32 KB I/D Caches Dynamic Memory Controller DDR3, DDR2, LPDDR2 ARM CoreSight Multi-core & Trace Debug NEON / FPU Engine 512 KB L2 Cache Timer Counters AMBA Switches NEON / FPU Engine Cortex -A9 MPCore 32/32 KB I/D Caches Snoop Control Unit (SCU) 256 KB On-Chip Memory General Interrupt Controller DMA Configuration AMBA AMBA Switches Switches ACP Programmable Logic: System Gates, DSP, RAM Shadow Register CRC Checker Scrambler SATA HCI DMA Scatter-Gather DMA Transport FIS Construct Link FIS Decomp CRC Generate Descrambler 8b/10b Encoder OOB Phy 8b/10b Decoder Speed Negotiate 27 February
11 Architecture Option 3: 3 rd Party FPDMA Controller with NCQ Close to max out SSD! Processing System 2x SPI Static Memory Controller Quad-SPI, NAND, NOR AMBA Switches Dynamic Memory Controller DDR3, DDR2, LPDDR2 AMBA Switches Programmable Logic: System Gates, DSP, RAM Depending on application, bottleneck is in software (IOPS) I/O MUX 2x I2C 2x CAN 2x UART GPIO 2x SDIO ARM CoreSight Multi-core & Trace Debug NEON / FPU Engine Cortex -A9 MPCore MIO 32/32 KB I/D Caches 512 KB L2 Cache Timer Counters NEON / FPU Engine Cortex -A9 MPCore 32/32 KB I/D Caches Snoop Control Unit (SCU) 256 KB On-Chip Memory ACP NCQ SATA HCI FPDMA Transport SGDMA This can be caused by too many IRQs 2x USB 2x GigE General Interrupt Controller DMA Configuration AMBA AMBA Switches Switches Shadow Register CRC Checker Scrambler FIS Construct Link FIS Decomp CRC Generate Descrambler 8b/10b Encoder OOB Phy 8b/10b Decoder Speed Negotiate 27 February
12 Additional Architecture Options Command Completion Coalescense (CCC) to reduce interrupt and command completion overhead in heavily loaded systems [Serial ATA AHCI 1.3] Frees up CPU Increases #IOPs è Functionality of 3 rd party SATA AHCI IP core Striping over multiple SATA links into multiple SSDs (a.k.a. RAID-0) Software-RAID will not work due to CPU load è Extra functionality in 3 rd party SATA AHCI IP core 27 February
13 Conclusion Building performance storage solutions for FPGA-based SoCs is more than an IP core! Requires a fine-tuned micro-architecture properly integrated into the software system. Benefits of pre-validated FPGA subsystems. è See us at Xilinx booth Hall 1/ February
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