SNJB College of Engineering Department of Computer Engineering

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Lynne Oliver
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1 contains three basic blocks of its operational logic. a. Timing block b. Control block c. Program command control block d. All of d above 2. Which block generates the internal timings and external control signals. a. Bus interface unit b. Execution unit c. Timing and control block of the above 3. Each of 4 DMA channels of 8237 has bit current address register. a. 16 b. 32 c. 64 d register holds the current memory address a. Current address register b. Current word register of the above 5. register holds the no of data byte transfers to be carried out a. Current word register b. Count segment c. Only a d. Both 6. These maintain an original copy of respective initial current register and current word register before incrementing or decrementing a. Mode register b. Base address and base word count registers c. Only b d. Both 7. register controls the complete operation of 8237 a. Code register b. Count register c. Command register of the above 8. Command register is bit a. 16 b. 32

2 c. 8 d Command register is programmed by and cleared by. a. CPU, reset b. ALU c. BIU of the above 10. In mode register bits and determine which of the 4 channels mode register are to be written a. 0 and 1 b. 2 and 3 c. 1 and 0 of the above 11. Bits and indicate the type of DMA transfer a. 0 and 1 b. 2 and 3 c. 1 and 0 of the above 12. Bit indicates whether address incremented or address decremented mode is selected a. 0 b. 5 c. 3 d register is nonmaskable and subject to prioritization by the priority resolving network of 8237 a. Request register b. Command register c. Mode register d. Both b and c 14. register holds data during memory memory data transfer a. Temporary register b. Command register c. Mode register of the above 15. register keeps the track of all DMA channel pending requests and the status of terminal counts a. Temporary register b. Command register c. Mode register d. Status register 16. bits are set if channels request services a. D4-D7

3 b. D0-D3 c. None of the above 17. signal is required for deriving the internal timings requiredfpr circuit operations a. GND b. CLK c. READY d. RESET 18. High on this input line clears the command, status, request and temporary register a. RESET b. CLK c. READY d. none 19. this active- high input is used to match the read or write speed of 8237 with slow memories or i/o devices a. READY b. RESET c. CLK 20. Signal used to indicate that cpu has relinquished the control of the bus, as a response to bus request a. HLDA b. READY c. RESET d. CLK 21. DREQo has priority a. Highest b. Lowest c. None of these 22. DREQ3 has priority a. Lowest b. Highest c. None 23. Data bus is lines used to transfer data to /from I/O or memory a. Unidirectional b. Bidirectional c. None 24. An output pin used to request te control of the system bus from cpu a. HRQ b. HOLD c. HLDA

4 d. CLK 25. An active low bidirectional pin used to indicate the completion of DMA operation a. HRQ b. HOLD c. EOP d. CLK operates in 2 cycles a. Idle, passive b. Idle, active c. Passive, active d. Both b and c 27. are actual working states of DMA operation in which the actual data transfer is carried out a. S0,S1,S2,S3 b. S1,S2,S3,S4 c. S0,S1 d. S2,S3 28. pin is used to disable other bus drivers during DMA transfer a. AEN b. HRQ c. HLDA d. HOLD 29. This output line is used to strobe the upper address byte generated by 8237, in master mode into, an external latch a. ADSTB b. AEN c. READY d. HLDA 30. In single transfer mode the device transfers only byte per second a. 1 b. 2 c. 4 d In this mode, 8237 is activated by DEREQ to continue the transfer until a block of data is transferred a. Demand mode b. Block transfer mode c. Cascade mode 32. In this mode more than one 8237 can be connected together.

5 a. Block transfer mode b. Cascade mode c. Demand mode d. All of the above 33. The transfer of a block of data from one set of memory address to another one is done using mode a. Memory to Memory transfer b. Demand mode c. Block transfer mode d. Cascade mode can be connected together to provide more than four DMA channels a. 1 b. More than Channel 0 current address register acts as a pointer a. Source b. Destination of these 36. Channel 1 current address register acts as a pointer a. Source b. Destination c. None of these carries out three basic transfers namelya. Write transfer b. Read transfer c. Verify transfer d. All of the above 38. There exists an flip-flop in 8237 also which is called first/last flip flop a. External b. Internal c. Slave 39. Output of these flip flop decides whether the byte of selected 16-bit register will be read or written a. First/last flip-flop b. Internal c. External

6 40. Selected register means register a. Current address register b. Current word count register 41. By clearing the first/last flip-flop the will address the higher or lower byte in appropriate sequence a. BIU b. Execution unit c. CPU d. Control unit 42. Mask set register when set, may the DMA cannels so that DMA requests are not entertained a. Enabled b. Disabled c. Reset 43. command will clear the bits of mask register individually or collectively a. Mask set register b. Clear mask register c. Clear register 44. To enable the DMA channels register clears the bits of mask register a. Mask register b. Clear register c. Clear mask register 45. All internal registers of 8237 are cleared using this command a. Clear mask register b. Mask register c. Clear first/last flip-flop d. Master clear command 46. Master clear command clears integral register, while all the bits of mask register are a. Reset b. Set c. Enabled 47. DMA controller disables all the DMA channels and enters an cycle a. Idle b. Wait

7 c. Ready 48. In transfers, the 8237 works in the same way as read or write transfer but does not generate any control signal a. Read transfer b. Write transfer d. Verify 49. In transfer the 8237 reads from an I/O device and writes to the memory a. Read transfer b. Write transfer d. Verify 50. In transfer the 8237 reads from the memory and writes to an I/O device a. Read transfer b. Write transfer d. Verify

The 8237 DMA Controller: -

The 8237 DMA Controller: - The 8237 is the LSI controller IC that is widely used to implement the direct memory access (DMA) function in 8088 and 8086 based microcomputer systems. It is available in 40-pin