4Mbit, 512KX8 5V Flash Memory (Monolithic)

Transcription

1 4Mbit, 512KX8 5V Flash Memory (Monolithic) Features 5V Programming, 5V±10% Supply TTL Compatible Inputs and CMOS Outputs Access Times: 90, 120 and 150ns Low Vcc Write Inhibit 3.2v 8 Equal Size Sectors of 64K Bytes Each Low Power Consumption Ceramic Package 32 pin 0.6" DIP Industrial and Military Screening Embedded Program/Erase Algorithms 1,000,000 Erase/Program Cycles Product Description The MEF5128N5 is a 4Megabit 5V flash memory MCM, assembled in multilayered cofired ceramic package, designed for low noise and better ground bounce. The MCM is based on "29F040" die. Flowcharts of programming, byte write, block erase and other specifications are identical to "29F040" specifications. Block Diagram December, 2003 Rev. A 1 OF 22

2 Pin Names Pin Name Pin Function A0 A18 Address Inputs D0 D7 Data Inputs/Outputs CE# Chip Enable WE# Write Enable OE# Output Enable GND Ground VCC Power (+5V ±10%) Note: # Symbol means "Active Low" Signal Pin Configuration (Top View) 1 A18 VCC 32 2 A16 WE# 31 3 A15 A A12 A A7 A A6 A A5 A A4 A A3 OE# A2 A A1 CE# A0 D D0 D D1 D D2 D GND D3 17 December, 2003 Rev. A 2 OF 22

3 Absolute Maximum Ratings MEF5128XXXXXXN5 Item Supply Voltage Relative to GND (1) Voltage On Any Pin Except A9 (2) A9 (2) Storage Temperature Output Short Circuit Current (3) Rating -2 to +7.0V -2 to +7.0V -2 to +14.0V -65 C to +150 C 200mA Notes: (1) Minimum D.C Voltage on any input is -0.5V, may undershoot to GND-2.0V for periods <20ns Maximum D.C Voltage on any output is Vcc +0.5V, may overshoot to Vcc +2.0V for periods < 20ns (2) Minimum D.C Voltage on A9 is -0.5V, may undershoot to -2.0V for periods < 20ns Maximum D.C Voltage on A9 is +13.5V, may overshoot to +14.0V for periods < 20ns (3) No more than one output shorted at a time for periods < 1second Recommended Operating Conditions Parameter Symbol Min Max Unit Supply Voltage VCC V Input High Voltage VIH 2.2 VCC +0.5 V Input Low Voltage VIL V Operating (Military) TA C Temperature (Industrial) C December, 2003 Rev. A 3 OF 22

4 Erase and Programming Performance MEF5128XXXXXXN5 Parameter Min Typ Max Unit Comments Sector Erase Time 1.0(1) 8 sec Excludes 00H Programming prior to Erasure Chip Erase Time 8(1) 64 sec Byte Programming Time 7 300(2) µs Chip Programming Time 3.6(1) 10.8 sec Excludes 00H Programming prior to Erasure Excludes System-level Overhead Excludes System-level Overhead Notes: (1) 25 C, 5V VCC, 1,000,000 cycles (2) When programming a "1" over a "0", the Embedded Algorithms allow for 48 ms byte program time Capacitance (TA = +25 C, VIN = 0, f = 1.0 MHz) Description Symbol Limits Unit OE# Capacitance COE 15 pf Write Enable Capacitance CWE 15 pf Chip Enable Capacitance CCE 15 pf D0 to D31 Capacitance CI/O 15 pf A0 to A18 Capacitance CAD 15 pf Note: These parameters are guaranteed by design but not tested. December, 2003 Rev. A 4 OF 22

5 DC Characteristics (TTL Compatible) MEF5128XXXXXXN5 Parameter Symbol Min Max Unit Test Condition Input Load Current ILI ±1.0 µa Vcc= Max, VIN=GND to Vcc A9 Input Load Current ILIT 50 µa Vcc= Max, A9 = 12.5V Output Leakage Current ILO ±1.0 µa Vcc= Max, VOUT=GND to Vcc Vcc Active Current (1) ICC1 30 ma CE# = VIL, OE# = VIH Vcc Active Current (2)(3) ICC2 40 ma CE# = VIL, OE# = VIH Vcc Stand by Current ICC3 1.0 ma Vcc= Max, CE# =OE# =VIH Input Low Level VIL V Input High Level VIH 2.0 Vcc+0.5 V Voltage for Autoselect and Sector Protect VID V Vcc = 5.0V Output Low Voltage VOL 0.45 V IOL = 12mA,Vcc = Min Output High Voltage VOH 2.4 V IOH = -2.5mA,Vcc = Min Low Vcc Lock-Out Voltage VLKO V Notes: (1) The Icc current listed includes both the DC operating current and the frequency dependent component (at 6 MHz) The frequency component typically is less than 2mA/MHz, with OE# at VIH (2) Icc active while Embedded Algorithm (program or erase) is in progress (3) Not 100% tested December, 2003 Rev. A 5 OF 22

6 Bus Operation Table Legend: L = VIL, H = VIH, X = Don't Care Operation CE# OE# WE# A0 A1 A6 A9 I/O Auto-Select Manufacturer Code (1) L L H L L L VID Code Auto-Select Device Code (1) L L H H L L VID Code Read (3) L L H A0 A1 A6 A9 Dout Standby H X X X X X X High Z Output Disable L H H X X X X High Z Write L H L AO A1 A6 A9 Din Enable Sector Protect L VID L X X X VID X Verify Sector Protect (2) L L H L H L VID Code Notes: (1) Manufacturer and device codes may also be accessed via a command register write sequence. Refer to sector address and to sector protection verify Autoselect codes tables (2) Refer to the section on Sector Protection (3) WE# can be VIL if OE# is VIL, OE# at VIH initiates the write operation December, 2003 Rev. A 6 OF 22

7 Command Definitions Command Sequence Read/Reset Bus Write Cycles Req`d First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 RA RD Reset H AAH 2AAAH 55H 5555H FOH XXXH FOH Autoselect H AAH 2AAAH 55H 5555H 90H Byte Program H AAH 2AAAH 55H 5555H AOH PA Data Chip Erase H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H Sector Erase Suspend Sector Erase Resume Erase can be suspended during sector erase with Addr (don't care), Data (BOH) Erase can be resumed after suspend with Addr (don`t care), Data (30H) Notes: 1. Address bits A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state. 2. Address bits A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA). 4. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# pulse. SA = Address of the sector to be erased. The combination of A18, A17 and A16 will uniquely select any sector. 5. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of WE#. Sector Address Table A18 A17 A16 Address Range SA H-0FFFFH SA H-1FFFFH SA H-2FFFFH SA H-3FFFFH SA H-4FFFFH SA H-5FFFFH SA H-6FFFFH SA H-7FFFFH December, 2003 Rev. A 7 OF 22

8 AC Characteristics Read Only Operations Parameter Symbol 90ns 120ns 150ns Limits Unit (1) (1) (1) Read Cycle Time (3) TRC Min ns Address to Output Delay (4) TACC Max ns Chip Enable to Output Delay (5) TCE Max ns Output Enable to Output Delay TOE Max ns Chip Enable to Output High Z (2)(3) TDF Max ns Output Enable to Output High Z (2)(3) TDF Max ns Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First TOH Min ns Notes: (1) Test Conditions: Output Load... 1 TTL gate and 100 pf Input rise and fall times.. 20ns Input pulse levels V to 2.4V Timing measurement reference level: Input and 2.0V Output and 2.0V (2) Output driver disable time (3) Not 100% tested (4) Test Setup: CE# = OE#=VIL (5) Test Setup: OE#=VIL December, 2003 Rev. A 8 OF 22

9 AC Characteristics (Cont.) Write/Erase/Program Operations MEF5128XXXXXXN5 Parameter Symbol 90ns 120ns 150ns Limits Unit Write Cycle Time TWC Min ns Address Setup Time TAS Min ns Address Hold Time TAH Min ns Data Setup Time TDS Min ns Data Hold Time TDH Min ns Output Enable Setup Time TOES Min ns Output Enable Read TOEH Min ns Hold Time Toggle and Data Polling Min ns Read Recover Time Before Write TGHWL Min ns CE# Setup Time TCS Min ns CE# Hold Time TCH Min ns Write Pulse Width TWP Min ns Write Pulse Width TWPH Min ns Byte Programming Operation TWHWH Min µs Erase Operation TWHWH Min Max VCC Set Up Time TVCS Min µs Voltage Transition Time* TVLHT Max µs Write Pulse Width* TWPP Min µs OE# Setup Time to WE# Active* TOESP Min µs CE# Setup Time to WE# Active* TCSP Min µs (*) - See protect/unprotected waveforms sec sec December, 2003 Rev. A 9 OF 22

10 AC Characteristics Write/Erase/Program Operations (Alternate CE# Controlled Writes) Parameter Symbol 90ns 120ns 150ns Limits Unit Write Cycle Time TWC Min ns Address Setup Time TAS Min ns Address Hold Time TAH Min ns Data Setup Time TDS Min ns Data Hold Time TDH Min ns Output Enable Setup Time TOES Min ns Output Enable Read TOEH Min ns Hold Time Toggle and Data Polling Min ns Read Recover Time Before Write TGHEL Min ns WE# Setup Time TWS Min ns WE# Hold Time TWH Min ns CE# Pulse Width TCP Min ns CE# Pulse Width High TCPH Min ns Byte Programming Operation TWHWH Min µs Erase Operation TWHWH Min Max Vcc Setup Time TVCS Min µs sec sec December, 2003 Rev. A 10 OF 22

11 Timing Waveforms General Definitions and Notes 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the data written to the device. 4. Dout is the output of the data written to the device. 5. Timing indicates last two bus cycles of four bus cycle sequence. Timing Waveforms for Read Operation December, 2003 Rev. A 11 OF 22

12 Timing Waveforms for Program Operation Timing Waveforms for Chip/Sector Erase Operations December, 2003 Rev. A 12 OF 22

13 Timing Waveforms for Data Polling during Embedded Algorithm Operations Timing Waveforms for Toggle Bit During Embedded Algorithm Operations December, 2003 Rev. A 13 OF 22

14 Timing Waveforms for Program Operation (Alternate CE# Controlled) Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the data written to the device. 4. Dout is the output of the data written to the device. 5. Timing indicates last two bus cycles of four bus cycle sequence. December, 2003 Rev. A 14 OF 22

15 Sector Protection The 29F040 features hardware sector protection which will disable both program and erase operations to an individual sector or any group of sectors. To activate this mode, the programming equipment must force VID on control pin OE# and address pin A9. The sector addresses should be set using higher address lines A18, A17 and A16. The protection mechanism begins on the falling edge of the WE# pulse and is terminated with the rising edge of the same. It is also possible to verify if a sector is protected during the sector protection operation. This is done by setting A6=CE#=OE#=VIL and WE#=VIH (A9 remains high at VID). Reading the device at address location XXX2H, where the higher order addresses (A18, A17 and A16) define a particular sector, will produce 01H at data outputs (DQO-DQ7) for a protected sector. Sector Protection Verify Autoselect Codes Type A18 A17 A16 A6 A1 A0 DQ7 DQ0 Code (HEX) Sector Protection Sector Addresses VIL VIH VIL 01H (1) Note: (1) Outputs 01H at Protected sector Addresses December, 2003 Rev. A 15 OF 22

16 Sector Protection Waveforms MEF5128XXXXXXN5 SAx = Sector Address for Initial Sector SAy = Sector Address for Next Sector December, 2003 Rev. A 16 OF 22

17 Sector Protection Algorithm MEF5128XXXXXXN5 December, 2003 Rev. A 17 OF 22

18 Sector Unprotect The 29F040 also features a sector unprotect mode, so that a protected sector may be unprotected to incorporate any changes in the code. All sectors should be protected prior to unprotecting any sector. To activate this mode, the programming equipment must force VID on control pins OE#, CE# and address pin A9. The address pins A6, A16, and A12 should be set to VIH. The unprotection mechanism begins on the falling edge of the WE# pulse and is terminated with the rising edge of the same. It is also possible to determinate if a sector is unprotected in the system by writing the Autoselect command and A6 is set at VIH. Performing a read operation at address location XXX2H, where the higher order addresses (A18, A17, and A16) define a particular sector address, will produce 00H at data outputs (DQ0 DQ7) for an unprotected sector. December, 2003 Rev. A 18 OF 22

19 Sector Unprotect Waveforms MEF5128XXXXXXN5 December, 2003 Rev. A 19 OF 22

20 Sector Unprotect Algorithm MEF5128XXXXXXN5 December, 2003 Rev. A 20 OF 22

21 Outline Drawing for 32-Pin Ceramic DIP (D) Outline Drawing for Thin 32-Pin Ceramic DIP (D1) December, 2003 Rev. A 21 OF 22

22 Ordering Information (Standard Military Screened Products*) Model Number Speed Package MEF5128D090MN5 90ns CDIP32 MEF5128D120MN5 120ns CDIP32 MEF5128D150MN5 150ns CDIP32 MEF5128D1090MN5 90ns Thin CDIP32 MEF5128D1120MN5 120ns Thin CDIP32 MEF5128D1150MN5 150ns Thin CDIP32 (*) - Contact Elisra for additional designs Part Number Breakdown December, 2003 Rev. A 22 OF 22