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1 Laboratory Embedded System Application C 2010 Spring Semester ROMs, Non-volatile and Flash Memories ELPL Naehyuck Chang Dept. of EECS/CSE Seoul National University
2 Revisit Previous Issues DRAM Bitlines Bitline (BL) is driven by the cell Bitline inversion (BLB) is not driven (reference) 2
3 Types of Memory Arrays 3
4 Magnetic Core Memory Non-volatile main memory 4
5 Diode ROM Wang 144-T Scientific Calculator 5
6 Read-Only Memory Cells BL BL BL WL 1 WL V DD WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2 6
7 MOS OR ROM Pulling up with NMOS transistors is not a good idea BL[0] BL[1] BL[2] BL[3] WL[0] VDD WL [1] WL [2] VDD WL [3] Vbias Pull-down loads 7
8 MOS NOR ROM Default wordline value is low Pseudo NOS setup with PMOS pull-ups V DD Pull-up devices WL[0] GND WL[1] WL[2] GND WL[3] BL [0] BL[1] 8 BL[2] BL [3]
9 MOS NOR ROM Equivalent Transient Model for a MOS NOR ROM Word line parasitics Wire capacitance and gate capacitance Wire resistance (polysilicon) Bit line parasitics Resistance is not dominant (metal) Drain and gate-drain capacitance VDD BL WL Rword Cbit Cword 9
10 MOS NOR ROM MOS NOR ROM Layout Programming using the active layer only Cell (9.5λ x 7λ) Polysilicon Metal1 Diffusion Metal1 on diffusion 10
11 MOS NOR ROM MOS NOR ROM Layout Programming using the contact layer only Cell (11λ x 7λ) Polysilicon Metal 1 Diffusion Metal1 on diffusion 11
12 MOS NAND ROM All word lines high by default with exception of selected row V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] 12
13 MOS NAND ROM Equivalent Transient Model for MOS NAND ROM Word line parasitics Similar to NOR ROM Bit line parasitics Resistance of cascaded transistors dominates Drain/source and complete gate capacitance V DD BL Rbit C L WL Rword Cbit Cword 13
14 MOS NAND ROM MOS NAND ROM Layout Programming using the metal1 layer only Cell (8λ x 7λ) No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion 14
15 MOS NAND ROM MOS NAND ROM Layout Programming using implants only Cell (5λ x 6λ) Polysilicon Threshold-altering implant Metal1 on Diffusion 15
16 Precharged MOS NOR ROM PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design f pre V DD Precharge devices WL [0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] 16
17 Non-Volatile Memory History MRAM, Phase Change, Polymer 2000 s Ferro-electric 1988 Nitride Storage 2002 MLC NOR Flash 1995 NOR Flash 1988 EPROM 1971 NAND Flash 1985 AND, DiNOR Flash 1990 s MLC NAND Flash 1996 Bipolar ROMS/PROMS Late 60 s EEPROM MLC = Multi-Level Cell
18 Floating Gate Transistor Tunnel Oxide POLY2 CONTROL GATE POLY1 FLOATING GATE CG FG D N+ SOURCE N+ DRAIN P-WELL Deep N-Well P-Substrate S Stacked gate NMOS transistor Poly1 floating gate for charge storage Poly2 control gate for accessing the transistor Tunnel-oxide for gate oxide Oxide-nitride-oxide (ONO) for the inter poly dielectric Source/drain junctions optimized for program/erase/leakage 18
19 Floating Gate Transistor Programming = Electrons Stored on the FG = High Vt Erasing = Remove electrons from the FG = Low Vt Threshold Voltage shift = ΔQFG/CCG Stored Electrons I ds 1 0 Erased 1 Programmed 0 V cg 19
20 UV EPROM Programming flowchart 20
21 UV EPROM UV version and OTP version Package and window difference 21
22 UV EPROM To erase a chip, it is removed from its socket on the system board and placed in EPROM erasure equipment to expose it to UV radiation for minutes 22
23 Hot Electron Effect NOR flash programming Channel hot electron programming - gate voltage inverts channel; drain voltage accelerates electrons towards drain; gate voltage pulls them to the floating gate In lucky electron model, electron crosses channel without collision, gaining > 3.2eV, hits Si atom, bounces over barrier Program Time ~ ms Program current ~ 50 ma/cell 0V 10V N + N + + P-Well Program 0V 5V Ec Ev Substrate Lucky Electron Channel 23 Floating Gate Ec Ev Vt (V) Vgate = 10V 1.E-07 1.E-06 1.E-05 1.E-04 Time (s) Vd=3.0V Vd=3.25V Vd=3.5V Vd=3.75V Vd=4.0V
24 Fowler Nordheim Tunneling (FN-t) NAND flash programming Tunnel programming from channel by biasing the top gate positive with respect to the ground Program Time ~ 300 µs Program current ~ displacement plus tunneling current Low current allows large parallelism 20V 0V 0V Ec Ev Channel Floating Gate N + N + P-well Ec 0 -Program Ev Y. S. Yim, et al. IEDM
25 Characteristics of NVM Devices 25
26 Comparison with NAND and NOR Flash NOR and NAND operations 26
27 Comparison with NAND and NOR Flash Cell array architecture 27
28 Comparison with NAND and NOR Flash Basic program operation of a NOR flash Basic read operation of a NOR flash 28
29 Comparison with NAND and NOR Flash NOR Direct access to bitline little parasitic resistance Cell current directly discharges bitline capacitance Fast initial random read access NAND Indirect access to bitline parasitic resistance from neighbor cells Cell current indirectly discharges bitline capacitance through large resistor Slow initial access Both have wide read Page access NOR: fast transistor = high read performance NAND: architected for lowest cost = slow transistors = low read performance 29
30 Comparison with NAND and NOR Flash Cell size NAND ~5λ2 NOR ~10λ2 Both capable of multi-level cells NOR read latency = 10 s of nsec NAND read latency = 1-10 s of µsec 30
31 Comparison with NAND and NOR Flash Applications Data storage for digital cameras, MP3 players, USB drive, etc.) Code storage for PDA, cell phones, etc. Pros and cons NOR XIP (execution-in-place) and high price NAND low price and shadow RAM requirement 31
32 Comparison with NAND and NOR Flash Required pinouts 32
33 Comparison with NAND and NOR Flash Performance comparison 33
34 Comparison with NAND and NOR Flash Summary of characteristics 34
35 More About NAND Flash Market size 35
36 More About NAND Flash Market share by products 36
37 More About NAND Flash NAND flash architecture 37
38 More About NAND Flash Command cycle 38
39 More About NAND Flash Command and address cycles 39
40 More About NAND Flash Erase cycle 40
41 More About NAND Flash Program command 41
42 Multi-Level-Cell (MLC) Flash Same cell holds digital information of more than one bit Use sophisticated circuit to store a controlled amount of charge Use complex sensing mechanism to sense four levels of Vth Noise immunity reduced Scalability reduced I ds V cg 42
43 Multi-Level-Cell (MLC) Flash SLC Take advantage of the threshold voltage difference between the erased and programmed states of the single-level-cell case Two levels = 1 bit/cell Four levels = 2 bits/cell In general: n bits/cell = log2 (#levels) Need additional reference cells for program/ read One read reference cell for 1 bit/cell Three read reference cells for 2bits/cell N-1 reference cells for n bits/cell Corresponding reference cells for program 43
44 Multi-Level-Cell (MLC) Flash SLC MLC Take advantage of the threshold voltage difference between the erased and programmed states of the single-level-cell case Two levels = 1 bit/cell Four levels = 2 bits/cell In general: n bits/cell = log2 (#levels) Need additional reference cells for program/ read One read reference cell for 1 bit/cell Three read reference cells for 2bits/cell N-1 reference cells for n bits/cell Corresponding reference cells for program Count R1 P1 R2 P2 R3 P3
45 Multi-Level-Cell (MLC) Flash Why do MLC? Cost Effectively cuts cell area per bit in half Provides the same cost improvement from an array area perspective as a litho generation Three key MLC considerations Precise charge placement (Programming) Cell programming must be accurately controlled, which requires a detailed understanding of cell physics, voltage control and timing Precision voltage generation for stable wordline and drain voltage Precise charge sensing (Read) MLC read operation is an analog to digital conversion of the charge stored in the cell Device and capacitance matching, collapsing sources of variation, precision wordline and drain voltage generation, Low current sensing Stable charge storage Leakage rate needs to be less than one electron per day 44
46 Multi-Level-Cell (MLC) Flash SLC and MLC performance difference 45
47 OneNAND Architecture Add three SRAM blocks instead of data registers Add SRAM interface for the random access to the SRAM blocks 46
48 OneNAND Buffer RAM 47
49 OneNAND Applications Aiming at elimination of a NOR flash for booting Necessary boot code is provided by the buffer RAM with XIP Preserving the shadowing scheme 48
50 FTL (Flash Translation Layer) A software layer emulating standard block device interface Read/Write Features Sector mapping Garbage collection Power-off recovery Bad block management Wear-leveling Error correction code (ECC) 49
51 FTL (Flash Translation Layer) Garbage collection is performed when a virtual block is full, or the number of free pages in the whole device is lower than a specified threshold value The virtual blocks meeting the conditions are selected for erasure The valid physical pages are copied into a free area The selected physical blocks are erased 50
52 FTL (Flash Translation Layer) Wear leveling Expected NAND flash lifetime If the application writes at 3 Kbyte/s Wear Leveling extends the lifetime of NAND flash devices because it ensures that even if an application writes to the same virtual blocks over and over again, the program/erase cycles will be distributed evenly over the NAND flash memory Block Aging Table (BAT) to remember which blocks have been erased in a selected period of time Dynamic Wear Leveling Static Wear Leveling 51
53 FTL (Flash Translation Layer) Wear leveling Dynamic Wear Leveling New data is programmed to the free blocks, among the ones used to store user data, that have had the fewest write/erase cycles Static Wear Leveling Storing long-lived data (for example, code) are involved and their content is copied to another block so that the original block can be used for more frequently-changed data Triggered when the difference between the maximum and the minimum number of write/erase cycles per block reaches a specific threshold With this particular technique, the mean age of physical NAND blocks is maintained constant 52
54 FTL (Flash Translation Layer) Bad block management (BBM) 53
55 FTL (Flash Translation Layer) Bad block management (BBM) Skip block method Creates the Bad Block Table and when the target address corresponds to a Bad Block address, the data is stored in the next good block, skipping the Bad Block Reserved block method Replaced by good blocks by re-directing the Flash Translation Layer to a known good block 54
56 Modern Nonvolatile Memory Devices 55
57 Modern Nonvolatile Memory Devices MRAM and FRAM technology forecast 56
58 Modern Nonvolatile Memory Devices FRAM (Ferroelectric RAM) FRAM is a random access memory similar in construction to DRAM Uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility B GND W 57
59 Modern Nonvolatile Memory Devices FRAM hysteresis curve Binary state 0 Positive electric field Positive polarization Binary state 1 Negative electric field Negative polarization 58
60 Modern Nonvolatile Memory Devices PRAM (Phase Change RAM) PRAM uses the unique behavior of chalcogenide glass Chalcogenide glass can be switched between two states, crystalline and amorphous, wit the application of heat B W GND 59
61 Modern Nonvolatile Memory Devices Chalcogenide material Chalcogenide is the general class of switching media in CD-RW and DVD-RW Laser beam energy is used to control the switching between crystalline and amorphous phase Low energy laser beam to read 60
62 Modern Nonvolatile Memory Devices MRAM (Magnetoresistive RAM) Data is not stored as electric charge or current flows, but by magnetic storage elements The elements are formed from two ferromagnetic plates Each of plates can hold a magnetic filed, separated by a thin insulating layer B W GND 61
63 Modern Nonvolatile Memory Devices MRAM (Magnetoresistive RAM) Parallel magnetization Low R Anti-parallel magnetization High R Ferromagnetic film Thin insulator Ferromagnetic film 62
64 Modern Nonvolatile Memory Devices Comparisons of major silicon memories DRAM SRAM NAND NOR FRAM PRAM Cell size Latency Data rate Low Vcc Non-volatility X X O O O O Endurance High density best worst 6 63
65 NV Memory Future 64
66 NV Memory Future 65
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