Embedded Memory Alternatives

Transcription

1 EE241 - Spring 2005 Advanced Digital Integrated Circuits Lecture 26: Embedded Memory - Flash Slides Courtesy of Randy McKee, TI Embedded Memory Alternatives Courtesy Randy McKee, TI 2 1

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3 5 SRAM 3

4 90 nm SRAM cell sizes 7 The art of making small cells 8 4

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6 SRAM Yield Limitations Read Stability Cell can flip due to increase in the 0 storage node above the trip voltage of the other inverter during a read. Hold Stability Data retention current not able to compensate the leakage currents. Access Time Time required to produce a pre-specified V between the bit lines is higher than the maximum tolerable limit. Write Stability 1 Storage node may not be reduced below the trip point of the other inverter before WL is discharged. Mukhopadhyay et al, Read Stability F1( VL) = V F2( V L S = F2( V S) = V L L + c L S + c S) F1( VL) Bhavnagarwala et al, 2001 F1( VL) F2( VL SNM) = 0 VL VL 12 6

7 Hold Stability Similar to Read Stability analysis without access transistor. PR must provide enough leakage to compensate for leakage in NMOS pull-down and access transistors. 13 Read Access Must provide V between the bit lines within maximum tolerable time limit. Limited to floating bit-line implementation with voltage sensing amplifiers. Sum BL currents and integrate. T ACCESS = VDD VBL, R VMIN VDD C dv IBL, L BL, L BL, L = VDD VBL, R VDD C dv IBL, R BL, R BL, R Mukhopadhyay et al,

8 Write Stability Need V WRITE < V TRIP for writability. T WRITE VTRIP = VDD I in( R CR( VR) dvr )( VR) Iout( R) ( VR) < T WL for write stability. Mukhopadhyay et al,

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10 19 Some stacked solutions (TI) 20 10

11 21 Semiconductor Memory Trends From [Itoh01] 22 11

12 Trends in Memory Cell Area From [Itoh01] 23 Flash Memory Slides adapted from Ken Takeuchi, Toshiba 12

13 Flash EEPROM Control gate Floating gate erasure n + source programming p- substrate Thin tunneling oxide n + drain Many other options 25 Basic Operations in a NOR Flash Memory Erase 26 13

14 Basic Operations in a NOR Flash Memory Write 27 Basic Operations in a NOR Flash Memory Read 28 14

15 History of Flash Memories PRESENT SanDisk-type SanDisk-type FLASH MEMORY Invention NANDtype ACEEtype X AND-type NAND-type AND-type File- Storage NOR-type NOR-type Split-gate-type X SST-type SST-type Code- Storage DiNOR-type DiNOR-type 29 Flash Memory Comparison - Code vs File Storage - Code Storage Applications Program storage for - Cellular Phone -DVD -Set TOP Box BIOS for - PC and peripherals Performance Important : High speed random access Byte programming Acceptable : Slow programming Slow erasing Type of Flash memory NOR Intel / Sharp AMD / Fujitsu / Toshiba DINOR Mitsubishi File Storage Small form factor card for - Digital Still Camera - Silicon Audio - PDA... etc Mass storage as - Silicon Disk Drive Important : High speed programming High speed erasing High speed serial read Acceptable : Slow random access NAND Toshiba / Samsung AND Hitachi SanDisk: NOR 30 15

16 Requirements for File Storage Memory Low Bit Cost <$.2/MByte High Density >256MByte High Speed Programming >6MByte/sec and Erasing <3msec/block High Speed Serial Read Low Power Consumption Good Program/Erase Endurance >1 million cycles 31 Cell Array Comparison NOR SanDisk AND NAND Bit line(metal) Bit line /Source line(metal) Word line(poly) Contact Erase gate(poly) Word line(poly) Word line(poly) Word line(poly) Source line (Diff. Layer) Sub Bit line (Diff. Layer) 10F 2 Unit Cell Unit Cell Unit Cell 9F 2 Unit Cell 8F 2 4F 2 Source line (Diff. Layer) Source line (Diff. Layer) Simplest wiring Smallest area 32 16

17 NAND Cell Array (Top view) Select transistor Word lines Active area STI Bit line contact Source line contact 33 NAND Cell Array (Cross sectional view) Word line A A A Bit line A Word line Select gate Source line 34 17

18 Cell Size Shrink by Self-Aligned STI LOCOS_NAND LOCOS_NAND :: 6F 6F+ 2 2 Floating Gate 3 Word Line STI_NAND STI_NAND :: 4F 4F+ 2 2 F Current F 35 NAND Cell Array (Cross sectional view) 2 nd floating gate Word line 1 st floating gate B B Word line STI Si B B 36 18

19 NAND Cell Trend NOR-type Cell NAND-type Cell (Contactless) Self-Aligned STI Cell Self-Aligned STI Cell + Multi Level Cell 3.5F 2F 2F 2F 3F 3F Cell Size 10-11F 2 6-7F 2 4-5F F 2 Isolation LOCOS LOCOS SA-STI SA-STI 2F 2F Floating Gate Control Gate Floating Gate Control Gate LOCOS STI 37 NAND Flash Cell Size Trend 10 LOCOS SA-STI MLC 1 SA-STI Cell Size ( um 2 ) Control Gate Tunnel Oxide Floating Gate ONO LOCOS WSi 0.25um Multi Level Cell 0.1 Control Gate Floating Gate Tunnel Oxide ONO STI WSi 0.175um 0.13um 0.10um 0.01 Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan- Jan Start of Mass Production 38 19

20 That s all Folks Thanks for the fun semester. See you next Monday 39 20