Single, dual, or triple gate functions in small footprint packages
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- Clifton Doyle
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1 PicoGate Logic portfolio Single, dual, or triple gate functions in small footprint packages The PicoGate portfolio comprises single-, dual-, and triple-gate functions in small 5-, 6-, 8- or 10-pin leaded packages. Compared to traditional quad-gate solutions, PicoGate allows you to select just the number of functions that you need. You can easily create intricate line layout patterns while saving up to 85% board space. KEY FEATURES Very small footprint 0.95 mm, 0.65 mm and 0.5 mm pitch options Fully specified (-40 to +125 C) AEC-Q100 options Pb-free, RoHS and dark green compliant BENEFITS Simplified board layout Low power consumption APPLICATIONS Space constrained applications Consumer Portable Industrial Automotive The PicoGate packages house the same logic families as the larger SO, TSSOP & DQFN packages. Whereas the 74LVC08 is a quad 2-input AND gate the 74LVC1G08 PicoGate is a single 2-input AND gate. These packages allow the use of single gates rather than using one gate of a quad. As well as reducing the complexity of board layout, PicoGate devices are ideal glue logic to implement last minute feature additions and improve time-to-market. Their small size and lower-power consumption makes them ideal for portable electronic devices. PicoGate packages are available with 0.95 mm, 0.65 mm and 0.5 mm pin pitch.
2 PICOGATE PORTFOLIO The PicoGate portfolio is very broad and includes analog switches, buffers/inverters/drivers, bus switches, counters, decoders, flip-flops, gates, multiplexers/demultiplexers, latches, level shifters and Schmitt-trigger devices. R ON (W) f (-3dB) (MHz) Analog switches 74AHC1G66 single-pole, single-throw analog switch ~125 74AHCT1G66 single-pole, single-throw analog switch; TTL enabled ~125 74HC1G66 single-pole, single-throw analog switch ~125 74HCT1G66 single-pole, single-throw analog switch; TTL enabled ~125 74HC2G66 dual single-pole, single-throw analog switch ~125 74HCT2G66 dual single-pole, single-throw analog switch; TTL enabled ~125 74LVC1G53 single-pole, double-throw analog switch ~125 74LVC1G66 single-pole, single-throw analog switch ~125 74LVC1G384 single-pole, single-throw analog switch ~125 74LVC1G3157 single-pole, double-throw analog switch ~125 74LVC2G53 single-pole, double-throw analog switch ~125 74LVC2G66 dual single-pole, single-throw analog switch ~125 74LVCV2G66 Bus switches dual single-pole, single-throw analog switch; overvoltage tolerant ~125 74CBTLV1G125 single bus switch ~125 CBT3306 dual bus switch ~85 CBTD3306 dual bus switch level translator ~85 Buffers/inverters/drivers 74AHC1GU04 single inverter; unbuffered ± ~125 74AHC3GU04 triple inverter; unbuffered ± ~125 74AHC1G04 single inverter ± ~125 74AHCT1G04 single inverter; TTL enabled ± ~125 74AHC1G07 single buffer; open-drain ~125 74AHC1G17 single buffer Schmitt-trigger ± ~125 74AHCT1G17 single buffer Schmitt-trigger; TTL enabled ± ~125 74AHC1G125 single buffer/line driver (3-state) ± ~125 74AHCT1G125 single buffer/line driver; TTL enabled (3-state) ± ~125 74AHC1G126 single buffer/line driver (3-state) ± ~125 74AHCT1G126 single buffer/line driver; TTL enabled (3-state) ± ~125 74AHC2G125 dual buffer/line driver (3-state) ± ~125 74AHCT2G125 dual buffer/line driver; TTL enabled (3-state) ± ~125 74AHC2G126 dual buffer/line driver (3-state) ± ~125 74AHCT2G126 dual buffer/line driver; TTL enabled (3-state) ± ~125
3 74AHC2G241 dual buffer/line driver (3-state) ± ~125 74AHCT2G241 dual buffer/line driver; TTL enabled (3-state) ± ~125 74AHC3G04 triple inverter ± ~125 74AHCT3G04 triple inverter; TTL enabled ± ~125 74AUP1G04 single inverter ± ~125 74AUP1G06 single inverter; open-drain ~125 74AUP1G07 single buffer; open-drain ~125 74AUP1G14 single inverter; Schmitt-trigger ± ~125 74AUP1G34 single buffer ± ~125 74AUP1G125 single buffer/line driver (3-state) ± ~125 74AUP1G126 single buffer/line driver (3-state) ± ~125 74AUP1G240 single inverter/line driver (3-state) ± ~125 74AUP1GU04 single inverter; unbuffered ± ~125 74AUP2G04 dual inverter ± ~125 74AUP2G06 dual inverter; open-drain ~125 74AUP2G07 dual buffer; open-drain ~125 74AUP2G14 dual inverter; Schmitt-trigger ± ~125 74AUP2G34 dual buffer ± ~125 74AUP2G125 dual buffer/line driver (3-state) ± ~125 74AUP2G126 dual buffer/line driver (3-state) ± ~125 74AUP2G240 dual inverter/line driver (3-state) ± ~125 74AUP2G241 dual buffer/line driver (3-state) ± ~125 74AUP2GU04 dual inverter; unbuffered ± ~125 74AUP3G04 triple inverter ± ~125 74AUP3G07 triple buffer; open-drain ~125 74AUP3G34 triple buffer ± ~125 74HC1GU04 single inverter; unbuffered ± ~125 74HC2GU04 dual inverter; unbuffered ± ~125 74HC3GU04 triple inverter; unbuffered ± ~125 74HC1G04 single inverter ± ~125 74HCT1G04 single inverter; TTL enabled ± ~125 74HC1G125 single buffer/line driver (3-state) ± ~125 74HCT1G125 single buffer/line driver; TTL enabled (3-state) ± ~125 74HC1G126 single buffer/line driver (3-state) ± ~125 74HCT1G126 single buffer/line driver; TTL enabled (3-state) ± ~125 74HC2G04 dual inverter ± ~125 74HCT2G04 dual inverter; TTL enabled ± ~125 74HC2G34 dual buffer ± ~125 74HCT2G34 dual buffer; TTL enabled ± ~125 74HC2G125 dual buffer/line driver (3-state) ± ~125 74HCT2G125 dual buffer/line driver; TTL enabled (3-state) ± ~125 74HC3G04 triple inverter ± ~125 74HCT3G04 triple inverter; TTL enabled ± ~125 74HC3G06 triple inverter; open-drain ~125 74HCT3G06 triple inverter; open-drain; TTL enabled ~125
4 74HC3G07 triple buffer; open-drain ~125 74HCT3G07 triple buffer; open-drain; TTL enabled ~125 74HC3G34 triple buffer ± ~125 74HCT3G34 triple buffer; TTL enabled ± ~125 74LVC1G04 single inverter ± ~125 74LVC1G06 single inverter; open-drain ~125 74LVC1G07 single buffer; open-drain ~125 74LVC1G34 single buffer ± ~125 74LVC1G125 single buffer/line driver (3-state) ± ~125 74LVC1G126 single buffer/line driver (3-state) ± ~125 74LVC1GU04 single inverter; unbuffered ± ~125 74LVC2G04 dual inverter ± ~125 74LVC2G06 dual inverter; open-drain ~125 74LVC2G07 dual buffer; open-drain ~125 74LVC2G34 dual buffer ± ~125 74LVC2G125 dual buffer/line driver (3-state) ± ~125 74LVC2G126 dual buffer/line driver (3-state) ± ~125 74LVC2G240 dual inverter/line driver (3-state) ± ~125 74LVC2G241 dual buffer/line driver (3-state) ± ~125 74LVC2GU04 dual inverter; unbuffered ± ~125 74LVC3G04 triple inverter ± ~125 74LVC3G06 triple inverter; open-drain ~125 74LVC3G07 triple buffer; open-drain ~125 74LVC3G34 triple buffer ± ~125 74LVC3GU04 triple inverter; unbuffered ± ~125 XC7SET04 single inverter; TTL enabled ± ~125 XC7SET125 single buffer/line driver; TTL enabled (3-state) ± ~125 XC7SH04 single inverter ± ~125 XC7SH125 single buffer/line driver (3-state) ± ~125 XC7SHU04 single inverter; unbuffered ± ~125 XC7WH126 dual buffer/line driver (3-state) ± ~125 Counters/frequency dividers 74HC6323A 74HCT6323A Decoders/demultiplexers programmable ripple counter with oscillator (3-state) programmable ripple counter with oscillator (3-state); TTL enabled ± ~ ± ~125 74AUP1G18 1-to-2 demultiplexer (3-state) ± ~125 74AUP1G19 1-to-2 decoder/demultiplexer ± ~125 74LVC1G18 1-to-2 demultiplexer (3-state) ± ~125 74LVC1G19 1-to-2 decoder/demultiplexer ± ~125 Multiplexers 74AUP1G157 single 2-input multiplexer ± ~125 74AUP1G158 single 2-input multiplexer; inverting ± ~125 74AUP2G157 single 2-input multiplexer ± ~125 74LVC1G157 single 2-input multiplexer ± ~125
5 Flip-flops 74AHC1G79 single D-type flip-flop; positive-edge trigger ± ~125 74AHCT1G79 74AUP1G74 single D-type flip-flop; positive-edge trigger; TTL enabled single D-type flip-flop with set and reset; positive-edge trigger ± ~ ± ~125 74AUP1G79 single D-type flip-flop; positive-edge trigger ± ~125 74AUP1G80 single D-type flip-flop; positive-edge trigger ± ~125 74AUP1G175 74AUP1G374 single D flip-flop with reset; positive-edge trigger single D-type flip-flop; positive-edge trigger (3-state) ± ~ ± ~125 74AUP2G79 dual D-type flip-flop; positive-edge trigger ± ~125 74AUP2G80 dual D-type flip-flop; positive-edge trigger ± ~125 74LVC1G74 single D-type flip-flop with set and reset; positive-edge trigger ± ~125 74LVC1G79 single D-type flip-flop; positive-edge trigger ± ~125 74LVC1G80 single D-type flip-flop; positive-edge trigger ± ~125 74LVC1G175 74LVC2G74 Gates single D flip-flop with reset; positive-edge trigger single D-type flip-flop with set and reset; positive-edge trigger ± ~ ± ~125 74AHC1G09 single 2-input AND gate; open-drain ± ~125 74AHC1G00 single 2-input NAND gate ± ~125 74AHCT1G00 single 2-input NAND gate; TTL enabled ± ~125 74AHC1G02 single 2-input NOR gate ± ~125 74AHCT1G02 single 2-input NOR gate; TTL enabled ± ~125 74AHC1G08 single 2-input AND gate ± ~125 74AHCT1G08 single 2-input AND gate; TTL enabled ± ~125 74AHC1G32 single 2-input OR gate ± ~125 74AHCT1G32 single 2-input OR gate; TTL enabled ± ~125 74AHC1G86 2-input EXCLUSIVE-OR gate ± ~125 74AHCT1G86 2-input EXCLUSIVE-OR gate; TTL enabled ± ~125 74AHC2G00 dual 2-input NAND gate ± ~125 74AHCT2G00 dual 2-input NAND gate; TTL enabled ± ~125 74AHC2G08 dual 2-input AND gate ± ~125 74AHCT2G08 dual 2-Input AND gate; TTL enabled ± ~125 74AHC2G32 dual 2-input OR gate ± ~125 74AHCT2G32 dual 2-input OR gate; TTL enabled ± ~125 74AUP1G00 single 2-input NAND gate ± ~125 74AUP1G02 single 2-input NOR gate ± ~125 74AUP1G08 single 2-input AND gate ± ~125 74AUP1G09 single 2-input AND gate; open-drain ~125 74AUP1G11 single 3-input AND gate ± ~125 74AUP1G32 single 2-input OR gate ± ~125 74AUP1G38 single 2-input NAND gate; open-drain ~125 74AUP1G57 configurable gate; Schmitt trigger ± ~125
6 74AUP1G58 configurable gate; Schmitt trigger ± ~125 74AUP1G86 single 2-input EXCLUSIVE-OR gate ± ~125 74AUP1G97 configurable gate; Schmitt trigger ± ~125 74AUP1G98 configurable gate; Schmitt trigger ± ~125 74AUP1G332 single 3-input OR gate ± ~125 74AUP1G386 single 3-input EXCLUSIVE-OR gate ± ~125 74AUP1G885 dual function gate ± ~125 74AUP1G0832 single 3-input AND-OR gate ± ~125 74AUP1G3208 single 3-input OR-AND gate ± ~125 74AUP1T57 configurable gate with voltage level translation V ± ~125 74AUP1T58 configurable gate with voltage level translation V ± ~125 74AUP1T97 configurable gate with voltage level translation V ± ~125 74AUP1T98 configurable gate with voltage level translation V ± ~125 74AUP1Z04 crystal driver with enable and internal resistor ± ~125 74AUP1Z125 crystal driver with enable and internal resistor (3-state) ± ~125 74AUP2G00 dual 2-input NAND gate ± ~125 74AUP2G02 dual 2-input NOR gate ± ~125 74AUP2G08 dual 2-input AND gate ± ~125 74AUP2G32 dual 2-input OR gate ± ~125 74AUP2G38 dual 2-input NAND gate; open-drain ~125 74AUP2G57 dual PCB configurable multiple function gate ± ~125 74AUP2G86 dual 2-input EXCLUSIVE-OR gate ± ~125 74AUP2G0604 inverter with open-drain and inverter ± ~125 74AUP2G3404 buffer and inverter ± ~125 74AUP2G3407 buffer and buffer with open-drain ± ~125 74AUP3G0434 dual inverter and single buffer ± ~125 74AUP3G3404 dual buffer and single inverter ± ~125 74HC1G00 single 2-input NAND gate ± ~125 74HCT1G00 single 2-input NAND gate; TTL enabled ± ~125 74HC1G02 single 2-input NOR gate ± ~125 74HCT1G02 single 2-input NOR gate; TTL enabled ± ~125 74HC1G08 single 2-input AND gate ± ~125 74HCT1G08 single 2-input AND gate; TTL enabled ± ~125 74HC1G32 single 2-input OR gate ± ~125 74HCT1G32 single 2-input OR gate; TTL enabled ± ~125 74HC1G86 single 2-input EXCLUSIVE-OR gate ± ~125 74HCT1G86 single 2-input EXCLUSIVE-OR gate; TTL enabled ± ~125 74HC2G00 dual 2-input NAND gate ± ~125 74HCT2G00 dual 2-input NAND gate; TTL enabled ± ~125 74HC2G02 dual 2-input NOR gate ± ~125 74HCT2G02 dual 2-input NOR gate; TTL enabled ± ~125 74HC2G08 dual 2-input AND gate ± ~125 74HCT2G08 dual 2-Input AND gate; TTL enabled ± ~125
7 74HC2G32 dual 2-input OR gate ± ~125 74HCT2G32 dual 2-input OR gate; TTL enabled ± ~125 74HC2G86 dual 2-input EXCLUSIVE-OR gate ± ~125 74HCT2G86 dual 2-input EXCLUSIVE-OR gate; TTL enabled ± ~125 74LVC1G00 single 2-input NAND gate ± ~125 74LVC1G02 single 2-input NOR gate ± ~125 74LVC1G08 single 2-input AND gate ± ~125 74LVC1G10 single 3-input NAND gate ± ~125 74LVC1G11 single 3-input AND gate ± ~125 74LVC1G27 single 3-input NOR gate ± ~125 74LVC1G32 single 2-input OR gate ± ~125 74LVC1G38 single 2-input NAND gate; open-drain ~125 74LVC1G57 configurable gate; Schmitt trigger ± ~125 74LVC1G58 configurable gate; Schmitt trigger ± ~125 74LVC1G86 single 2-input EXCLUSIVE-OR gate ± ~125 74LVC1G97 configurable gate; Schmitt trigger ± ~125 74LVC1G98 configurable gate; Schmitt trigger ± ~125 74LVC1G99 configurable gate; Schmitt trigger ± ~125 74LVC1G332 single 3-input OR gate ± ~125 74LVC1G386 single 3-Input EXCLUSIVE-OR gate ± ~125 74LVC1GX04 crystal driver ± ~125 74LVC2G00 dual 2-input NAND gate ± ~125 74LVC2G02 dual 2-input NOR gate ± ~125 74LVC2G08 dual 2-input AND gate ± ~125 74LVC2G32 dual 2-input OR gate ± ~125 74LVC2G38 dual 2-input NAND gate; open-drain ~125 74LVC2G86 dual 2-input EXCLUSIVE-OR gate ± ~125 XC7SET02 single 2-input NOR gate; TTL enabled ± ~125 XC7SET08 single 2-input AND gate; TTL enabled ± ~125 XC7SET32 single 2-input OR gate; TTL enabled ± ~125 XC7SET86 single 2-input EXCLUSIVE-OR gate; TTL enabled ± ~125 XC7SH02 single 2-input NOR gate ± ~125 XC7SH08 single 2-input AND gate ± ~125 XC7SH32 single 2-input OR gate ± ~125 XC7SH86 single 2-input EXCLUSIVE-OR gate ± ~125 Latches/registered drivers 74AUP1G373 single D-type transparent latch (3-state) ± ~125 Level shifters/translators 74AUP1T34 single dual supply translating buffer ± ~125 74AUP1T45 74AVC1T45 74AVC2T45 single dual-supply voltage level translating single dual-supply voltage level translating dual-bit dual-supply voltage level translating ± ~ ± ~ ± ~125
8 74AVCH1T45 74AVCH2T45 74AXP1T57 74LVC1T45 74LVCH1T45 74LVC2T45 74LVCH2T45 Multivibrators single dual-supply voltage translating transceiver with bus hold (3-state) dual-bit dual-supply voltage translating transceiver with bus hold (3-state) single dual supply voltage level translating configurable multifunction gate single dual-supply voltage level translating single dual-supply voltage translating transceiver with bus hold (3-state) dual-bit dual-supply voltage level translating dual-bit dual-supply voltage level translating transceiver with bus hold (3-state) ± ~ ± ~ ± ~ ± ~ ± ~ ± ~ ± ~125 74LVC1G123 single retriggerable monostable multivibrator ± ~125 Schmitt-triggers 74AHC1G14 single inverter Schmitt-trigger ± ~125 74AHCT1G14 single inverter Schmitt-trigger; TTL enabled ± ~125 74AHC1G17 single buffer Schmitt-trigger ± ~125 74AHCT1G17 single buffer Schmitt-trigger; TTL enabled ± ~125 74AHC3G14 triple inverter Schmitt-trigger ± ~125 74AHCT3G14 triple inverter Schmitt-trigger; TTL enabled ± ~125 74AUP1G14 single inverter; Schmitt-trigger ± ~125 74AUP1G17 single buffer Schmitt-trigger ± ~125 74AUP1G132 single 2-input NAND gate Schmitt-trigger ± ~125 74AUP2G14 dual inverter; Schmitt-trigger ± ~125 74AUP2G17 dual buffer Schmitt-trigger ± ~125 74AUP2G132 dual 2-input NAND gate Schmitt-trigger ± ~125 74HC1G14 single inverter Schmitt-trigger ± ~125 74HCT1G14 single inverter Schmitt-trigger; TTL enabled ± ~125 74HC2G14 dual inverter Schmitt-trigger ± ~125 74HCT2G14 dual inverter Schmitt-trigger; TTL enabled ± ~125 74HC2G17 dual buffer Schmitt-trigger ± ~125 74HCT2G17 dual buffer Schmitt-trigger; TTL enabled ± ~125 74HC3G14 triple inverter Schmitt-trigger ± ~125 74HCT3G14 triple inverter Schmitt-trigger; TTL enabled ± ~125 74LVC1G14 single inverter Schmitt-trigger ± ~125 74LVC1G17 single buffer Schmitt-trigger ± ~125 74LVC2G14 dual inverter Schmitt-trigger ± ~125 74LVC2G17 dual buffer Schmitt-trigger ± ~125 74LVC3G14 triple inverter Schmitt-trigger ± ~125 74LVC3G17 triple buffer Schmitt-trigger ± ~125 XC7SET14 single inverter Schmitt-trigger; TTL enabled ± ~125 XC7SH14 single inverter Schmitt-trigger ± ~125 XC7WH14 triple inverter Schmitt-trigger ± ~125 XC7WT14 triple inverter Schmitt-trigger; TTL enabled ± ~125
9 PICOGATE PACKAGES The PicoGate packages include TSOP and TSSOP 5 and 6 pin variants, SO, TSSOP and VSSOP 8 pin variants as well as TSSOP 10. Package suffix GW GV GW GV D DP PW DC DP TSSOP5 TSOP5 TSSOP6 TSOP6 SO8 TSSOP8 TSSOP8 VSSOP8 TSSOP10 Package SOT353-1 SOT753 SOT363 SOT457 SOT96-1 SOT505-2 SOT530-1 SOT765-1 SOT552 Width (mm) Length (mm) Height (mm) Pitch (mm) For more information about our PicoGate family visit For information about AEC-Q100 compliant devices visit NXP Semiconductors, B.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Date of release: November 2015 Document order number: Published in the USA
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