NVIDIA Tegra T20-H-A2 Application Processor TSMC 40 nm Low Power CMOS Process

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1 NVIDIA Tegra T20-H-A2 Application Processor TSMC 40 nm Low Power CMOS Process Structural Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

2 Structural Analysis Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. SAR JMRK Revision 1 Published: November 16, 2010

3 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream Product, Package, and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pad 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Peripheral Transistors 3.8 Poly Resistor 3.9 Isolation 3.10 Wells and Substrate 4 6T SRAM Cell Analysis 4.1 Overview 4.2 Plan-View Analysis 4.3 Cross-Sectional Analysis (Perpendicular to Bitline) 5 10T Dual-Port SRAM Cell Analysis 5.1 Overview 5.2 Plan-View Analysis 6 ROM Cell Analysis 7 Materials Analysis 7.1 Overview 7.2 TEM-EDS and EELS Analyses of the Dielectrics 7.3 Poly and Source Drain Silicide TEM-EDS 7.4 TEM-EDS of the Metallization

4 Structural Analysis 8 Critical Dimensions 8.1 Horizontal Dimensions 8.2 Vertical Dimensions 9 References 10 Statement of Measurement Uncertainty and Scope Variation About Chipworks

5 Overview Overview 1.1 List of Figures 2 Device Overview Toshiba AC100-10Z Netbook Toshiba AC100-10Z Netbook Top Toshiba AC100-10Z Netbook Bottom Inside the Toshiba AC100-10Z Netbook Main Circuit Board Toshiba AC100-10Z Main Circuit Board in Detail Tegra T20-H-A2 Package Top Tegra T20-H-A2 Package Bottom Tegra T20-H-A2 Package X-Ray Overview Plan View Tegra T20-H-A2 Package X-Ray in Detail Plan View Tegra T20-H-A2 Die Photograph Die Markings Annotated Die Photograph Poly Die Analysis Locations Die Corner A Die Corner B Die Corner C Die Corner D Minimum Pitch Flip-Chip Solder Bump Pads Flip-Chip Solder Bump Pad in Detail Metal 8 Dummy Structures Metal 7 Dummy Structures Metal 6 Dummy Structures Metal 5 and Metal 4 Dummy Structures Metal 4 and Metal 3 Dummy Structures Metal 3 and Metal 2 Dummy Structures Metal 2 and Metal 1 Dummy Structures Poly and Substrate Diffusion Dummy Structures Logic Cell Poly and Orientation Standard Logic Plan-View Image of Minimum Contacted Standard Logic Gate Pitch 3 Process Analysis Tegra T20-H-A2 General View Die Thickness and Edge Die Seal and Cutout Left Edge Die Seal Right Edge Die Seal Au Bump on Bond Pad Overview Au Bump on Bond Pad Right Edge Bond Pad Edge in Detail Passivation on Metal 9 SEM Passivation on Metal 9 TEM

6 Overview ILD 8 Detail TEM ILD 7 SEM ILD 6 and ILD 5 SEM ILD 6 TEM ILD 5 TEM ILD 4 TEM ILD 3 TEM ILD 2 TEM ILD 1 TEM PMD TEM Minimum Pitch Metal 9 Optical Plan View Metal 9 SEM Metal 9 ARC TEM Metal 9 Barrier Layer TEM Minimum Pitch Metal 8 TEM Metal 8 Liner TEM Minimum Pitch Metal 7 TEM Metal 7 Liner TEM Minimum Pitch Metal 6 TEM Metal 6 Liner TEM Minimum Pitch Metal 5 TEM Metal 5 Liner TEM Minimum Pitch Metal 4 SEM Metal 4 TEM Minimum Pitch Metal 3 TEM Metal 3 Liner TEM Minimum Pitch Metal 2 TEM Minimum Pitch Metal 1 TEM Metal 1 Liner TEM Minimum Pitch Via 8 SEM Via 8 Detail TEM Minimum Pitch Via 7 SEM Via 7 in Detail SEM Minimum Pitch Via 6s Minimum Pitch Via 5s Minimum Pitch Via 4s Minimum Pitch Via 3s TEM Minimum Pitch Via 2s TEM Minimum Pitch Via 1s TEM Minimum Pitch Contacts to Diffusion SEM Top of Contact to Diffusion TEM Bottom of Contact to Diffusion TEM Contact to Poly TEM Minimum Contacted Logic Gate Pitch TEM Contacted SRAM Gate Pitch TEM

7 Overview Minimum Gate Length Logic Transistor TEM Typical Logic Transistor TEM Right Edge of a Wide Gate Transistor TEM Logic Transistor ONO Lattice Image Peripheral Transistor and Source/Drain Contact TEM Peripheral Transistor Contact to Gate Spacing TEM Right Edge of Peripheral Transistor Gate TEM Peripheral Transistor Gate Oxide TEM Unsilicided Poly Resistor TEM Right Edge of Unsilicided Poly Resistor TEM Poly Over STI STI Edge Minimum Width STI Logic Minimum Width STI SRAM Electron Beam Diffraction Pattern Channel Region Logic Region N-Well 1 and P-well SCM Logic Region P-Well in Detail SCM Logic Region N-Well 2 in Detail SCM SRP Peripheral P-Well N-Well and P-Well Logic Region SIMS 4 6T SRAM Cell Analysis T SRAM T SRAM Block at Metal T SRAM Block at Metal T SRAM at Metal T SRAM at Metal T SRAM at Poly T SRAM at Diffusion TEM SRAM Perpendicular to Bitline TEM T3 (T4) PMOS Pull-Up Transistors TEM NMOS T1 Access and T2 Pull-Down Transistors TEM SRAM Gate Oxide 5 10T Dual-Port SRAM Cell Analysis T SRAM Block at Metal T SRAM Block at Metal T SRAM at Via T SRAM at Metal T SRAM at Poly 6 ROM Cell Analysis ROM Memory Block Overview ROM Memory SEM Plan View ROM Memory SEM Cross Section 7 Materials Analysis Passivation 1 TEM-EDS

8 Overview Passivation 2 TEM-EDS Metal 9 ARC TEM-EDS ILDs 4-2, 5-2, 6-2, 7-2, 7-4, and 8-2 TEM-EDS ILD 7-3 and 8-1 TEM-EDS ILDs 1-1, 2-1, 3-1, 4-1, 5-1, 6-1, and 7-1 TEM-EDS ILDs 2-3, 3-3, and 4-3 TEM-EDS ILD 6-2 TEM-EDS ILDs 1-3, 2-1, 2-2, and 2-3 EELS ILDs 1-1, 1-2, and 1-3 EELS PMD 3 TEM-EDS PMD 2 TEM-EDS PMD 1 TEM-EDS PMD 1, PMD 2, and PMD 3 EELS Contact Etch Stop Layer TEM-EDS MOS Gate Silicide Metal 9 Body TEM-EDS Ta-Based Metal 9 Barrier, Metal 8, and Metal 1 Liner TEM-EDS Metal 1 Cu Body TEM-EDS Contact Liner TEM-EDS

9 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Functional Block Sizes Die and Bond Pad Sizes 3 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor Horizontal Dimensions Transistor and Silicide Vertical Dimensions STI Measured Dimensions Die Thickness and Well Depths 4 6T SRAM Cell Analysis T SRAM Dimensions 8 Critical Dimensions Die and Bond Pads Metallization Horizontal Dimensions Via and Contact Dimensions Transistor Horizontal Dimensions Horizontal STI Dimensions T SRAM Cell Dimensions Dielectric Vertical Dimensions Metallization Vertical Dimensions Transistor and Silicide Vertical Dimensions Vertical STI Dimensions Die and Well Vertical Dimensions

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