COMPUTER ENGINEERING PROGRAM

Size: px
Start display at page:

Download "COMPUTER ENGINEERING PROGRAM"

Transcription

1 COMPUTER ENGINEERING PROGRAM California Polytechnic State University CPE 169 Experiment 1 Introduction to Basic Logic and the Digilent Development Board Learning Objectives 1. CPE 169 Hardware and Software To become familiar with the courseware and laboratory procedures 2. Introduction to a Digital System To become familiar with analyzing a digital system Introduction and Overview The Digilent Nexys2 development board is your primary hardware platform throughout CPE 169. Your overall objective in this experiment is to become familiar with and comfortable using this board and some of the associated software tools. A more thorough and in-depth description of the development board is presented in later experiments though your strongly encouraged to peruse the reference manual associated with the development board (located on the course website). You ll also become more familiar with the software as the quarter progresses. Figure 1 shows the Nexys2 development board, with arrows pointing out some of the more interesting features. Figure 1: The Nexys 2 board with pertinent parts indicated. 1/29/

2 The development board can be considered a complete digital system. The board contains various devices that act as inputs and other devices that act as outputs. For this experiment, several inputs and outputs are not used so they are omitted from the discussion at this point. The set of external inputs to the development board that you ll work with in this experiment include four push-buttons and eight slide switches. The external outputs that you ll work with are the eight light emitting diodes (LEDs) and two of the four 7- segment displays. Figure 2 shows a high-level black-box diagram of the digital system on the development board as you ll use it in this experiment. Figure 2: System-level black-box diagram of the development board for this experiment. Figure 2 shows notation that is used throughout CPE 169 and in digital design in general. In Figure 2, the arrows entering the box are used to indicate input signals while the arrows leaving the box are used to indicate output signals. The slashes across the signal lines indicate that there is more than one signal associated with the single line in the diagram. The number of signals represented by the line is indicated with the number near the slash. The notation used in Figure 2 provides a quick method to indicate that the system contains four buttons, eight switches, eight LEDs, and eight display segments. Any one of these related groups of signals is referred to as a bus, or possibly more appropriately, a bundle. The heart of the development board is a type of programmable logic device known as a fieldprogrammable gate array (FPGA). All you need to know about this device for this experiment is the fact that the device is programmable. This means that you can change the relationship between the input and output devices on the development board by downloading special files to the FPGA. In this experiment, you ll be downloading different circuit descriptions to the FPGA and analyzing the input and output characteristics of the downloaded circuit using the buttons, switches, LEDs, and 7-segment displays on the development board. The procedure to download files into the FPGA is listed in the following procedure portion of this experiment. Procedures Procedure Overview: There are two main procedures associated with this experiment. Both procedures involve the downloading of configuration files to the development board. Each configuration alters the relationship between the input and output devices shown in Figure 2. Your task in this experiment is to download each of the configurations to the FPGA in order to analyze and describe those relationships. The first procedure consists mainly of a demonstration of the capabilities of the development board. The second procedure requires that you analyze five different configurations on the development board. The FPGA input/output relationships in these configurations start out relatively simple but become more complex as you proceed through the configurations. Instructions to Prepare Development Board for Configuration: 1. Configure the jumpers on the development board to allow for programming the FPGA via the USB port, and to provide the proper power supply to the expansion connectors for later experiments. a. JP7 Power Select: Jumper on "USB" pins (across 2 bottom-most pins) b. JP9 Mode: Jumper on "JTAG" (across left-most 2 pins) c. JP1, JP2, JP3, JP5: Jumper on 3V3 (across middle & bottom pins) 1/29/

3 2. Connect the USB adapter cable supplied with your development board between the female USB port cable on the Laboratory PC and the mini USB connector on the development board 3. Apply power to the Development Board and verify that power is ON. a. The Nexys2 Board has its own POWER switch (located in the upper left corner of the board) which must be switched ON. b. A red LED labeled LD2V5 POWER is lit when power is on. 4. Provide the device ID and serial number for your development board to the Digilent USB programming tools. a. From the Windows Start Menu, select All Programs Digilent Adept USB Administrator. A new Digilent USB Administrator window should appear. b. Click on the numbers that appear in the window to reveal the Details. c. From the Windows Start Menu, select All Programs Digilent Adept ExPort. A new Digilent ExPort window should appear. d. Select Edit Configure Communications Modules A new Communication Modules window should appear. e. If the Serial number for your development board (found in the Digilent USB Administrator window) does not appear in the Select/ID column of the Communication Modules window, then: a. In the Communication Modules window, select Add Module USB b. In the Add Module window: 1. Click on your development board s serial number in the Connected Modules field. 2. Type in a name to uniquely identify your development board in the Device Name field. (The name is arbitrary, so use a name you will recognize as your own when you return to the lab in the future.) 3. Click on Add, and Done. c. In the Communication Modules window, select Save, and Close. f. Close the USB Administrator window. Instructions to Configure FPGA: There are several FPGA configuration files listed under Experiment 1 on the laboratory website (the ones with the.bit file extension). These files provide a description of a circuit that you ll download to the FPGA to program its internal circuitry. The procedure to download a file to the FPGA using the Digilent USB tools is listed below. Be sure to first verify that the development board is powered up and the appropriate programming cable is connected to the board. 1. Download the FPGA configuration files for this experiment (.bit files for the Nexys Board) listed on the class website to your PC desktop. 2. If the Digilent ExPort tool is not already open, then from the Windows Start Menu, select All Programs Digilent Adept ExPort. 3. In the Digilent ExPort window, make sure that the box marked Auto-Detect USB is checked. If not, click on the box until a check mark appears. 4. In the Digilent ExPort window, click on the Initialize Chain radio button. Two devices should appear in the window; one marked FPGA and one marked ROM. These are the two programmable devices on the development board. The FPGA contains the digital logic circuitry that you will be configuring and testing. The ROM device provides a place to store the FPGA configuration for automatic reprogramming when the development board is powered on. 5. Next to the FPGA device, click on the Browse.. button. 6. In the window that appears, browse to the Desktop and select one of the configuration (.bit) files you previously stored, and click on Open. (NOTE: A Warning message may appear with some 1/29/

4 undecipherable gibberish about CCLK and JTAG. Just click Yes to clear the message). The name of the configuration file you selected should now appear next to the FPGA device. 7. Right-click on the FPGA device in the diagram and click on the Program Device option in the pull-down menu that appears. (Or alternatively, just click on the Program Chain button.) 8. If the programming was successful, "Programming complete Succeeded" will appear in a new Programming window. Click on the OK button. In addition, the yellow DONE indicator (LD- D) will light when programming is completed. 9. The FPGA can be reprogrammed with a different configuration file at any time. To do so, repeat Steps 5 8 above. Procedure 1: Development Board Demonstration and Analysis Configuration Overview: The configuration for this procedure was designed to provide a demonstration of some of the capabilities of the development board. More specifically, this circuit demonstrates some typical applications for the 7-segment displays and relatively interesting visual events relating to the buttons and LEDs. It is your task to use various combinations of button presses to perform different functions on the development board and provided a description of the results. 1. Configure the development board with the demonstration configuration file: nexys2_demo.bit. 2. Set the eight switches (SW7 SW0) on the board to your choice of Up/Down pattern, other than all Up (HIGH) or all Down (LOW). 3. On the development board, simultaneously press two, one, or no buttons and describe the response observed on the board. Assemble your results from this step into tabular form (put your results in a table) and include it in your lab report. [HINT: Since there are four buttons, your table should have no more than 16 entries. However, since you only need to test for at most two simultaneous button presses, your table does not require listing all 16 possible combinations of pressed and nonpressed buttons.] Use the table format shown in the example in Table 1. Indicate a button that is pressed for a particular result using an "X" in its column in the table. Leave the table entries blank for any switches that are not pressed for a particular display result. Use button names in your table that match their designations on the development board. Be sure to also include a system-level black-box diagram of the digital system you are testing in your lab report. BTN3 BTN2 BTN1 BTN0 Description of Development Board Display Results X Development board explodes violently X Lab partner passes out X Alien beings take control of development board Table 1: Example table and headings for the results of Procedure 1. 1/29/

5 Procedure 2: Development Board LED Analysis Configuration Overview: Each of the configuration files allows the LEDs (outputs) on the development board to be driven by actuating a single or some combination of buttons or switches (inputs). These five files are used on different levels where the higher levels indicate that more complex input conditions are required to light an LED. For each level, you are to find the input combination or combinations that turns on each of the LEDs. Your mission is to find and list what those relationships are. There are eight LEDs so you ll need to find eight relationships for each level. To help you with this daunting task, certain guidelines are provided for you and are listed in Table 2. Level Number of Inputs per LED Input Combination Description Number of Combinations that turn on each LED 1 1 either one button or one switch one button and one switch one button and one switch one button and two switches two buttons and two switches? Table 2: Guidelines for configuration file analysis. Development Board LED Analysis: 1. Configure the development board with the configuration file nexys2_level1.bit. 2. Using Table 2 as a guideline, determine what input settings (combinations of switches and buttons) are required to turn on each of the eight LEDs (outputs). Consider a button to be on when pressed and off when not pressed. Consider a switch to be on when in the up position and off when in the down position. 3. Assemble your results (the switch/button combinations that turn on each of the LEDs) in tabular form. Be sure to include a system-level black-box diagram of the digital system you are testing in your lab report. 4. Repeat the previous steps for levels 2-5. The configuration files are named according to the level you are executing (i.e., nexys2_level2.bit, nexys2_level3.bit, etc.). NOTE: Level 3 requires that you find two different combinations of switches and buttons that make each LED light up. You must list both possibilities. NOTE: Level 5 is somewhat complex. If you can figure out how to individually turn on each of the eight LEDs using the Level 5 configuration file without assistance from an instructor or other students, you will receive an A in CPE 169 and will not be required to perform any more of the experiments. (However, be sure to ask the instructor for the secret approach to dealing with this level before becoming too frustrated!) 1/29/

6 Questions 1. In Procedure 1, your testing consisted of pressing different combinations of the four buttons. How many unique button combinations would have been possible given the four buttons if all combinations were allowed (with 4, 3, 2, 1 or no buttons pressed)? 2. With the four buttons used in Procedure 1, how many unique button combinations were possible under each of the following specific conditions? Briefly state the method you used to answer this question. a. only one button pressed b. only two buttons pressed c. only two or three buttons pressed 3. The Level-4 combinations were relatively complicated. Describe your strategy for figuring out the input combinations without losing your sanity. 4. Familiarize yourself with the basic operation of the Nexys2 development board by reading the first few sections of the Nexys2 Reference Manual (Overview, Functional Description, FPGA and Platform Flash Configuration), available on the class website. Is the FPGA used in this experiment on the Nexys2 board considered to be a volatile or a non-volatile device? Describe the difference between these two device types. 5. What oscillation frequency is used for the primary system timing clock oscillator on the Nexys2 board? 6. The FPGA used in this experiment is considered to be a re-configurable device. How many different circuit configurations were used in this experiment? 7. In terms of inputs, outputs, digital systems, components on the Development Board, and the files you downloaded to the board; completely describe exactly what you did in this experiment in your own words. What exactly did you download to your board? Where did this downloaded information reside on the board once downloaded? What happened as a result of downloading this information (what did it accomplish or change)? What were the inputs to your digital systems? What were the outputs? By manipulating the buttons and switches on the board, what exactly were you providing to the system? What makes the devices you tested a digital system? 8. Despite the fact that there are 7-segment displays on the development board, there are eight signals used to drive the displays (see Figure 2). Briefly describe why the 7-segment display has eight signals. 1/29/

COMPUTER ENGINEERING PROGRAM

COMPUTER ENGINEERING PROGRAM COMPUTER ENGINEERING PROGRAM California Polytechnic State University CPE 169 Experiment 1 Introduction to Basic Logic and the Digilent Development Board Learning Objectives 1. CPE 169 Hardware and Software

More information

ECE 4305 Computer Architecture Lab #1

ECE 4305 Computer Architecture Lab #1 ECE 4305 Computer Architecture Lab #1 The objective of this lab is for students to familiarize with the FPGA prototyping system board (Nexys-2) and the Xilinx software development environment that will

More information

EE 1315: DIGITAL LOGIC LAB EE Dept, UMD

EE 1315: DIGITAL LOGIC LAB EE Dept, UMD EXPERIMENT # 7: Basic Latches EE 1315: DIGITAL LOGIC LAB EE Dept, UMD Latches are primitive memory elements of sequential circuits that are used in building simple noise filtering circuits and flip-flops.

More information

Revision: January 28, Henley Court Pullman, WA (509) Voice and Fax

Revision: January 28, Henley Court Pullman, WA (509) Voice and Fax Lab Project 2: Board Verification and Basic Logic Circuits Revision: January 28, 2012 1300 Henley Court Pullman, WA 99163 (509) 334 6306 Voice and Fax STUDENT I am submitting my own work, and I understand

More information

EE 1315 DIGITAL LOGIC LAB EE Dept, UMD

EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EXPERIMENT # 1: Logic building blocks The main objective of this experiment is to let you familiarize with the lab equipment and learn about the operation of the

More information

Nexys 2/3 board tutorial (Decoder, ISE 13.2) Jim Duckworth, August 2011, WPI. (updated March 2012 to include Nexys2 board)

Nexys 2/3 board tutorial (Decoder, ISE 13.2) Jim Duckworth, August 2011, WPI. (updated March 2012 to include Nexys2 board) Nexys 2/3 board tutorial (Decoder, ISE 13.2) Jim Duckworth, August 2011, WPI. (updated March 2012 to include Nexys2 board) Note: you will need the Xilinx ISE Webpack installed on your computer (or you

More information

Xilinx Tutorial Basic Walk-through

Xilinx Tutorial Basic Walk-through Introduction to Digital Logic Design with FPGA s: Digital logic circuits form the basis of all digital electronic devices. FPGAs (Field Programmable Gate Array) are large programmable digital electronic

More information

Configuring the Xilinx Spartan-6 LX9 MicroBoard

Configuring the Xilinx Spartan-6 LX9 MicroBoard Configuring the Xilinx Spartan-6 LX9 MicroBoard Version 1.3 Table of Contents Table of Contents... 2 Table of Figures... 3 Revision History... 4 Overview... 5 Configuration and Programming via the on-board

More information

CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2011

CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2011 CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2011 GENERAL DEVELOPMENT CYCLE WITH FPGAS FOR A NEW CHIP 1. Introduction A digital product is developed as a new (digital) chip or as a new printed circuit

More information

Circuit design with configurable devices (FPGA)

Circuit design with configurable devices (FPGA) 1 Material Circuit design with configurable devices (FPGA) Computer with Xilinx's ISE software installed. Digilent's Basys2 prototype board and documentation. Sample design files (lab kit). Files and documents

More information

To practice combinational logic on Logisim and Xilinx ISE tools. ...

To practice combinational logic on Logisim and Xilinx ISE tools. ... ENGG1203: Introduction to Electrical and Electronic Engineering Second Semester, 2017 18 Lab 1 Objective: To practice combinational logic on Logisim and Xilinx ISE tools. 1 Find your lab partner You will

More information

Exercise 1: Introduction to Digital Circuits EE214 Fall 2014

Exercise 1: Introduction to Digital Circuits EE214 Fall 2014 Exercise 1: Introduction to Digital Circuits EE214 Fall 2014 I am submitting my own work in this exercise, and I am aware of the penalties for cheating that will be assessed if I submit work for credit

More information

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 150 Spring 2000

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 150 Spring 2000 University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS 150 Spring 2000 Lab #8: EPROMs This lab is to be completed with a project partner.

More information

XILINX WebPack -- testing with Nexys2 boards at USC (EE201L)

XILINX WebPack -- testing with Nexys2 boards at USC (EE201L) XILINX WebPack -- testing with Nexys2 boards at USC (EE201L) Gandhi Puvvada 1 Before you start: 1.1 We assume that you have installed WebPACK on your desktop or laptop already. We assume that you have

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip NIOS CPU Based Embedded Computer System on Programmable Chip 1 Lab Objectives EE8205: Embedded Computer Systems NIOS-II SoPC: PART-I This lab has been constructed to introduce the development of dedicated

More information

LABORATORY # 6 * L A B M A N U A L. Datapath Components - Adders

LABORATORY # 6 * L A B M A N U A L. Datapath Components - Adders Department of Electrical Engineering University of California Riverside Laboratory #6 EE 120 A LABORATORY # 6 * L A B M A N U A L Datapath Components - Adders * EE and CE students must attempt also to

More information

Nexys 2 board tutorial (Decoder, ISE 12.2) Jim Duckworth, August 2010, WPI. Digilent Adept Programming Steps added by Zoe (Zhu Fu)

Nexys 2 board tutorial (Decoder, ISE 12.2) Jim Duckworth, August 2010, WPI. Digilent Adept Programming Steps added by Zoe (Zhu Fu) Nexys 2 board tutorial (Decoder, ISE 12.2) Jim Duckworth, August 2010, WPI. Digilent Adept Programming Steps added by Zoe (Zhu Fu) Note: you will need the Xlinx ISE Webpack installed on your compuer (or

More information

The Alarm System: The alarm system to be designed has the following inputs.

The Alarm System: The alarm system to be designed has the following inputs. 1 Introduction In this lab you will use the Xilinx CAD tools to complete the design of a simple home alarm system containing sensors for that indicate whether the Windows, Door, and Garage are secure.

More information

Getting started with the Xilinx Project Navigator and the Digilent BASYS 2 board.

Getting started with the Xilinx Project Navigator and the Digilent BASYS 2 board. Getting started with the Xilinx Project Navigator and the Digilent BASYS 2 board. This lab is based on: Xilinx Project Navigator, Release Version 14.6 Digilent Adept System Rev 2.7, Runtime Rev 2.16 Digilent

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip 1 Objectives NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems This lab has been constructed to introduce the development of dedicated embedded system based

More information

Mercury Baseboard Reference Manual

Mercury Baseboard Reference Manual Mercury Baseboard Reference Manual www.micro-nova.com OVERVIEW The Baseboard is a great addition to the Mercury Module, providing a host of on-board components that can be used to design and test a wide

More information

PRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory.

PRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory. PRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory. 1.0 Objectives In this lab you will get familiar with the concept of using the

More information

CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND:

CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Getting familiar with DE2 board installation, properties, usage.

More information

Revision: 11/30/ E Main Suite D Pullman, WA (509) Voice and Fax

Revision: 11/30/ E Main Suite D Pullman, WA (509) Voice and Fax Digilent Adept Suite User s Manual Revision: 11/30/06 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview To install the Digilent Adept Suite, open the Adept Setup file and follow

More information

Digilab 2 XL Reference Manual

Digilab 2 XL Reference Manual 125 SE High Street Pullman, WA 99163 (509) 334 6306 (Voice and Fax) www.digilentinc.com PRELIMINARY Digilab 2 XL Reference Manual Revision: May 7, 2002 Overview The Digilab 2 XL (D2XL) development board

More information

Revision: February 19, E Main Suite D Pullman, WA (509) Voice and Fax. Switching Power Supplies 3V3 1V2 2V5 1V8

Revision: February 19, E Main Suite D Pullman, WA (509) Voice and Fax. Switching Power Supplies 3V3 1V2 2V5 1V8 Nexys Board Reference Manual Revision: February 19, 2007 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview s Nexys circuit board is an integrated circuit development platform based

More information

Xilinx Vivado/SDK Tutorial

Xilinx Vivado/SDK Tutorial Xilinx Vivado/SDK Tutorial (Laboratory Session 1, EDAN15) Flavius.Gruian@cs.lth.se March 21, 2017 This tutorial shows you how to create and run a simple MicroBlaze-based system on a Digilent Nexys-4 prototyping

More information

FPGA Discovery-III XC3S200 Board Manual

FPGA Discovery-III XC3S200 Board Manual FPGA Discovery-III XC3S200 Board Manual 77/9 SOI LADPRAO 1, LADPRAO ROAD, JOMPOL, JATUJAK DISTRICT, BANGKOK THAILAND 10900 TEL. 66(0)2939-2084 FAX.66(0)2939-2084 http://www.ailogictechnology.com 1 FPGA

More information

University of Hawaii EE 361L. Getting Started with Spartan 3E Digilent Basys2 Board. Lab 4.1

University of Hawaii EE 361L. Getting Started with Spartan 3E Digilent Basys2 Board. Lab 4.1 University of Hawaii EE 361L Getting Started with Spartan 3E Digilent Basys2 Board Lab 4.1 I. Test Basys2 Board Attach the Basys2 board to the PC or laptop with the USB connector. Make sure the blue jumper

More information

Revision: 5/7/ E Main Suite D Pullman, WA (509) Voice and Fax. Power jack 5-9VDC. Serial Port. Parallel Port

Revision: 5/7/ E Main Suite D Pullman, WA (509) Voice and Fax. Power jack 5-9VDC. Serial Port. Parallel Port Digilent Digilab 2 Reference Manual www.digilentinc.com Revision: 5/7/02 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Digilab 2 development board (the D2) features the

More information

Digilab 2E Reference Manual

Digilab 2E Reference Manual Digilent 2E System Board Reference Manual www.digilentinc.com Revision: February 8, 2005 246 East Main Pullman, WA 99163 (509) 334 6306 Voice and Fax Digilab 2E Reference Manual Overview The Digilab 2E

More information

Digilab 2 Reference Manual

Digilab 2 Reference Manual 125 SE High Street Pullman, WA 99163 (509) 334 6306 (Voice and Fax) www.digilentinc.com PRELIMINARY Digilab 2 Reference Manual Revision: November 19, 2001 Overview The Digilab 2 (D2) development board

More information

Altera EP4CE6 Mini Board. Hardware User's Guide

Altera EP4CE6 Mini Board. Hardware User's Guide Altera Hardware User's Guide 1. Introduction Thank you for choosing the! is a compact FPGA board which is designed based on device. It's a low-cost and easy-to-use platform for learning Altera's Cyclone

More information

Pre-Laboratory #Boolean Expressions ECE 332

Pre-Laboratory #Boolean Expressions ECE 332 Name: G Number: Pre-Laboratory #Boolean Expressions ECE 332 1 Introduction This pre-lab is divided into two parts. In part one you will build a circuit for providing inputs to your CPLD board on your breadboard.

More information

USB-COMi-TB USB to Industrial Single RS-422 / 485 Adapter Manual. Specifications and Features

USB-COMi-TB USB to Industrial Single RS-422 / 485 Adapter Manual. Specifications and Features USB-COMi-TB USB to Industrial Single RS-422 / 485 Adapter Manual The USB-COMi-TB USB-to-Industrial Single RS-422/485 Adapter is designed to make industrial communication port expansion quick and simple.

More information

MDP Based Face Detection Demonstration User Guide

MDP Based Face Detection Demonstration User Guide FPGA-UG-02047 Version 1.0 May 2018 Contents Acronyms in This Document... 3 1. Introduction... 4 2. Functional Description... 4 3. Demo Setup... 5 4. Programming the Face Detection Demo... 7 5. Running

More information

ARM programmer and daughter board EB Technical datasheet

ARM programmer and daughter board EB Technical datasheet ARM programmer and daughter board EB185-00-1 Technical datasheet Contents 1 About this document...2 2 General information...3 3 Description...3 4 Board layout...4 5 Testing this product...5 6 Circuit description...7

More information

Revision: May 11, E Main Suite D Pullman, WA (509) Voice and Fax LED. Doc: page 1 of 6

Revision: May 11, E Main Suite D Pullman, WA (509) Voice and Fax LED. Doc: page 1 of 6 Digilent XC2-XL System Board Reference Manual www.digilentinc.com Revision: May 11, 2004 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Digilent XC2-XL System Board (the

More information

Corona (MAXREFDES12#) Nexys 3 Quick Start Guide

Corona (MAXREFDES12#) Nexys 3 Quick Start Guide Corona (MAXREFDES12#) Nexys 3 Quick Start Guide Rev 0; 4/13 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product.

More information

A B A+B

A B A+B ECE 25 Lab 2 One-bit adder Design Introduction The goal of this lab is to design a one-bit adder using programmable logic on the BASYS board. Due to the limitations of the chips we have in stock, we need

More information

Programmable Logic Design I

Programmable Logic Design I Programmable Logic Design I Introduction In labs 11 and 12 you built simple logic circuits on breadboards using TTL logic circuits on 7400 series chips. This process is simple and easy for small circuits.

More information

and 32 bit for 32 bit. If you don t pay attention to this, there will be unexpected behavior in the ISE software and thing may not work properly!

and 32 bit for 32 bit. If you don t pay attention to this, there will be unexpected behavior in the ISE software and thing may not work properly! This tutorial will show you how to: Part I: Set up a new project in ISE 14.7 Part II: Implement a function using Schematics Part III: Simulate the schematic circuit using ISim Part IV: Constraint, Synthesize,

More information

Opal Kelly. XEM6002 User s Manual

Opal Kelly. XEM6002 User s Manual Opal Kelly XEM6002 User s Manual A business-card sized (3.5 x 2.0 ) semiconductor evaluation platform featuring the Xilinx Spartan-6 FPGA and four Pmod TM connectors. The XEM6002 is a small, business-card

More information

EMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 7: VHDL and DE2 Board. Name: Date:

EMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 7: VHDL and DE2 Board. Name: Date: EXPERIMENT # 7: VHDL and DE2 Board Name: Date: Equipment/Parts Needed: Quartus II R Web Edition V9.1 SP2 software by Altera Corporation USB drive to save your files Objective: Learn how to create and modify

More information

EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09

EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09 EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09 Lab Description Today s lab will introduce you to the Xilinx Integrated Software Environment (ISE)

More information

ELEC 204 Digital System Design LABORATORY MANUAL

ELEC 204 Digital System Design LABORATORY MANUAL ELEC 204 Digital System Design LABORATORY MANUAL : Introductory Tutorial For Xilinx ISE Foundation v10.1 & Implementing XOR Gate College of Engineering Koç University Important Note: In order to effectively

More information

ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado

ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University Prof. Sunil P Khatri (Lab exercise created and tested by Ramu Endluri, He Zhou, Andrew Douglass

More information

Tutorial for Altera DE1 and Quartus II

Tutorial for Altera DE1 and Quartus II Tutorial for Altera DE1 and Quartus II Qin-Zhong Ye December, 2013 This tutorial teaches you the basic steps to use Quartus II version 13.0 to program Altera s FPGA, Cyclone II EP2C20 on the Development

More information

NEXYS4DRR board tutorial

NEXYS4DRR board tutorial NEXYS4DRR board tutorial (VHDL Decoder design using Vivado 2015.1) Note: you will need the Xilinx Vivado Webpack version installed on your computer (or you can use the department systems). This tutorial

More information

ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado

ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University Prof. Sunil P. Khatri Lab exercise created and tested by: Abbas Fairouz, Ramu Endluri, He Zhou,

More information

Name EGR 2131 Lab #6 Number Representation and Arithmetic Circuits

Name EGR 2131 Lab #6 Number Representation and Arithmetic Circuits Name EGR 2131 Lab #6 Number Representation and Arithmetic Circuits Equipment and Components Quartus software and Altera DE2-115 board PART 1: Number Representation in Microsoft Calculator. First, let s

More information

Tutorial on Quartus II Introduction Using Verilog Code

Tutorial on Quartus II Introduction Using Verilog Code Tutorial on Quartus II Introduction Using Verilog Code (Version 15) 1 Introduction This tutorial presents an introduction to the Quartus II CAD system. It gives a general overview of a typical CAD flow

More information

Programmable Logic Design I

Programmable Logic Design I Programmable Logic Design I Read through each section completely before starting so that you have the benefit of all the directions. Put on a grounded wrist strap (cf. Getting Started) before touching

More information

CONTENTS BIGAVR2 KEY FEATURES 4 CONNECTING THE SYSTEM 5 INTRODUCTION 6

CONTENTS BIGAVR2 KEY FEATURES 4 CONNECTING THE SYSTEM 5 INTRODUCTION 6 CONTENTS BIGAVR2 KEY FEATURES 4 CONNECTING THE SYSTEM 5 INTRODUCTION 6 Switches 7 Jumpers 8 MCU Sockets 9 Power Supply 11 On-board USB 2.0 Programmer 12 Oscillator 14 LEDs 15 Reset Circuit 17 Push-buttons

More information

Typical applications where a CPLD may be the best design approach:

Typical applications where a CPLD may be the best design approach: By: Carlos Barberis, dba Bartek Technologies Description of Bartek s CPLD1 development board. For some of us CPLD s are familiar devices and for others just another acronym in the electronic device industry.

More information

ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University

ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University Prof. Sunil P Khatri (Lab exercise created and tested by Ramu Endluri, He Zhou, Andrew Douglass

More information

475 Electronics for physicists Introduction to FPGA programming

475 Electronics for physicists Introduction to FPGA programming 475 Electronics for physicists Introduction to FPGA programming Andrej Seljak, Gary Varner Department of Physics University of Hawaii at Manoa November 18, 2015 Abstract Digital circuits based on binary

More information

Introduction to Nexys 2 board - Detour Signal Lab

Introduction to Nexys 2 board - Detour Signal Lab 1. Synopsis: Introduction to Nexys 2 board - This lab introduces the use of Field Programmable Gate Arrays (FPGA). This lab introduces the Digilent Nexys 2 board and demonstrate FPGA design flow through

More information

This 4-port RS-422/485 Adapter is provided with an external switching power adapter in the package.

This 4-port RS-422/485 Adapter is provided with an external switching power adapter in the package. USB-4COMi-M USB to Quad RS-422/485 to Serial Adapter Manual The USB to Industrial Quad RS-422/485 Adapter is designed to make industrial communication port expansion quick and simple. Connecting to a USB

More information

EE 231 Fall EE 231 Lab 2

EE 231 Fall EE 231 Lab 2 EE 231 Lab 2 Introduction to Verilog HDL and Quartus In the previous lab you designed simple circuits using discrete chips. In this lab you will do the same but by programming the CPLD. At the end of the

More information

ECE 362 Lab Verification / Evaluation Form Experiment 3

ECE 362 Lab Verification / Evaluation Form Experiment 3 ECE 362 Lab Verification / Evaluation Form Experiment 3 Evaluation: IMPORTANT! You must complete this experiment during your scheduled lab perior. All work for this experiment must be demonstrated and

More information

SiliconBlue. SiliconBlue Technologies iceman65 Board. Programmable Solutions for Consumer Handheld. 7-MAY-2008 (v1.

SiliconBlue. SiliconBlue Technologies iceman65 Board. Programmable Solutions for Consumer Handheld. 7-MAY-2008 (v1. February 2008 1 SiliconBlue SiliconBlue Technologies iceman65 Board Programmable Solutions for Consumer Handheld 7-MAY-2008 (v1.1) February 2008 2 Agenda iceman65 Kit Programming Options More Information

More information

Lab - Install Windows 7 or Vista

Lab - Install Windows 7 or Vista Introduction In this lab, you will install the Windows 7 or Vista operating system. Recommended Equipment A computer with a blank hard disk drive Windows 7 or Vista installation DVD or USB flash drive

More information

Microcontroller Systems. ELET 3232 Topic 11: General Memory Interfacing

Microcontroller Systems. ELET 3232 Topic 11: General Memory Interfacing Microcontroller Systems ELET 3232 Topic 11: General Memory Interfacing 1 Objectives To become familiar with the concepts of memory expansion and the data and address bus To design embedded systems circuits

More information

Trouble shooting the DeskCNC controller:

Trouble shooting the DeskCNC controller: Checking for a functional card. 1) Unplug/Disconnect all connections to the I/O and step and direction pins/terminals. 2) Apply regulated 5vdc to the +5 and gnd terminals. CHECK FOR CORRECT POLARITY WITH

More information

SBS Software. Signals By Spreadsheet. Figure 1, SBS System Configuration

SBS Software. Signals By Spreadsheet. Figure 1, SBS System Configuration Figure 1, SBS System Configuration Internet (www.signalsbyspreadsheet.com) Interface Distributed Input/Output DIO Power Detectors Signals Positions In this guide, you will: Download (Initial Install for

More information

MDP Based Key Phrase Detection Demonstration User Guide

MDP Based Key Phrase Detection Demonstration User Guide MDP Based Key Phrase Detection Demonstration FPGA-UG-02048 Version 1.1 September 2018 Contents Acronyms in This Document... 3 1. Introduction... 4 2. Functional Description... 4 3. MDP Board Setup... 5

More information

Using Synplify Pro, ISE and ModelSim

Using Synplify Pro, ISE and ModelSim Using Synplify Pro, ISE and ModelSim VLSI Systems on Chip ET4 351 Rene van Leuken Huib Lincklaen Arriëns Rev. 1.2 The EDA programs that will be used are: For RTL synthesis: Synplicity Synplify Pro For

More information

Doc: page 1 of 8

Doc: page 1 of 8 Minicon Reference Manual Revision: February 9, 2009 Note: This document applies to REV C of the board. 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Minicon board is a

More information

CPLD/FPGA Development System

CPLD/FPGA Development System Chapter 1 CPLD/FPGA Development System As shown in Figure 1-1, CPLD (Complex Programmable Logic Device) and FPGA (Field-Programmable Gate Array) are the programmable logic devices (PLDs) whose internal

More information

Nios Embedded Processor Development Board

Nios Embedded Processor Development Board Nios Embedded Processor Development Board July 2003, ver. 2.2 Data Sheet Introduction Development Board Features Functional Overview This data sheet describes the features and functionality of the Nios

More information

PHYC 500: Introduction to LabView. Exercise 16 (v 1.2) Controlling hardware with DAQ device. M.P. Hasselbeck, University of New Mexico

PHYC 500: Introduction to LabView. Exercise 16 (v 1.2) Controlling hardware with DAQ device. M.P. Hasselbeck, University of New Mexico PHYC 500: Introduction to LabView M.P. Hasselbeck, University of New Mexico Exercise 16 (v 1.2) Controlling hardware with DAQ device This exercise has two parts. First, simulate a traffic light circuit

More information

Setup/Hold. Set Up time (t su ):

Setup/Hold. Set Up time (t su ): Lecture 10 Agenda Set Up time (t su ): Setup/Hold Minimum amount of time the data is to be held steady prior to the clock event Hold time (t h ): Minimum amount of time the data is to be held steady after

More information

into the EMU E4 Classic and E4 Platinum Samplers

into the EMU E4 Classic and E4 Platinum Samplers Installing the CF-CARD SCSI Card Reader/Writer Drive into the EMU E4 Classic and E4 Platinum Samplers Thank you for purchasing the CF-CARD Internal Card Reader Drive Installation Kit from SCSICardReaders.com.

More information

PHY 351/651 LABORATORY 1 Introduction to LabVIEW

PHY 351/651 LABORATORY 1 Introduction to LabVIEW PHY 351/651 LABORATORY 1 Introduction to LabVIEW Introduction Generally speaking, modern data acquisition systems include four basic stages 1 : o o A sensor (or transducer) circuit that transforms a physical

More information

Revision: February 26, E Main Suite D Pullman, WA (509) Voice and Fax

Revision: February 26, E Main Suite D Pullman, WA (509) Voice and Fax MCS File Creation with Xilinx ISE Tutorial Revision: February 26, 2010 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview This tutorial provides instruction for creating an.mcs

More information

Lab 0 Introduction to the MSP430F5529 Launchpad-based Lab Board and Code Composer Studio

Lab 0 Introduction to the MSP430F5529 Launchpad-based Lab Board and Code Composer Studio ECE2049 Embedded Computing in Engineering Design Lab 0 Introduction to the MSP430F5529 Launchpad-based Lab Board and Code Composer Studio In this lab, you will be introduced to the Code Composer Studio

More information

CHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8

CHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8 CONTENTS CHAPTER 1 Introduction of the tnano Board... 2 1.1 Features...2 1.2 About the KIT...4 1.3 Getting Help...4 CHAPTER 2 tnano Board Architecture... 5 2.1 Layout and Components...5 2.2 Block Diagram

More information

Tutorial on Quartus II Introduction Using Schematic Designs

Tutorial on Quartus II Introduction Using Schematic Designs Tutorial on Quartus II Introduction Using Schematic Designs (Version 15) 1 Introduction This tutorial presents an introduction to the Quartus II CAD system. It gives a general overview of a typical CAD

More information

8 Port USB to RS- 232/422/485 Octal Adapter. Product Manual. Coolgear, Inc. Version 1.1 April 2018 Model Number: USB-8COMi-RM.

8 Port USB to RS- 232/422/485 Octal Adapter. Product Manual. Coolgear, Inc. Version 1.1 April 2018 Model Number: USB-8COMi-RM. 8 Port USB to RS- 232/422/485 Octal Adapter Product Manual Coolgear, Inc. Version 1.1 April 2018 Model Number: USB-8COMi-RM 2 USB-8COMi-RM Product Manual Revision History Revision Date Author Comments

More information

Copyright 2011 R.S.R. Electronics, Inc. All rights reserved. 04/11. Ver. 1.0web

Copyright 2011 R.S.R. Electronics, Inc. All rights reserved. 04/11. Ver. 1.0web For XILINX WebPack Copyright 2011 R.S.R. Electronics, Inc. All rights reserved. 04/11 Ver. 1.0web 1 Table of Contents 1.0 INTRODUCTION...3 2.0 GENERAL DESCRIPTION...5 3.0 BRIEF DESCRIPTION Of PLDT-3 BOARD...6

More information

Arduino Micro Breadboard Laboratory Interface Processor (Micro BLIP) User Manual

Arduino Micro Breadboard Laboratory Interface Processor (Micro BLIP) User Manual Arduino Micro Breadboard Laboratory Interface Processor (Micro BLIP) MicroBLIP circuit board v2.0 Operating System v2.0.0 1/22/2019 User Manual 2 1 Setup and Operation 1.1 Introduction For the past ten

More information

Experiment # 4 Introduction to FPGAs - Detour Signal Lab

Experiment # 4 Introduction to FPGAs - Detour Signal Lab 1. Synopsis: Experiment # 4 Introduction to FPGAs - Detour Signal Lab This lab introduces the use of Field Programmable Gate Arrays (or FPGAs, for short) for prototyping of digital circuits. Through the

More information

Keep the work area free of clutter and clean. Food and drinks are not allowed in the work area.

Keep the work area free of clutter and clean. Food and drinks are not allowed in the work area. 29 Chapter 3 Computer Assembly Introduction This chapter addresses the process of the computer assembly process. The ability to successfully assemble a computer is a milestone for the PC Ttechnician. It

More information

JAZZ HARMONY User Manual

JAZZ HARMONY User Manual JAZZ HARMONY User Manual Copyright 2017 Imaging. All rights reserved. This manual and the software described herein are protected by copyright laws and international copyright treaties, as well as other

More information

EE 231 Fall Lab 1: Introduction to Verilog HDL and Altera IDE

EE 231 Fall Lab 1: Introduction to Verilog HDL and Altera IDE Lab 1: Introduction to Verilog HDL and Altera IDE Introduction In this lab you will design simple circuits by programming the Field-Programmable Gate Array (FPGA). At the end of the lab you should be able

More information

Module 003: Introduction to the Arduino/RedBoard

Module 003: Introduction to the Arduino/RedBoard Name/NetID: Points: /5 Module 003: Introduction to the Arduino/RedBoard Module Outline In this module you will be introduced to the microcontroller board included in your kit. You bought either An Arduino

More information

Finite State Machine Lab

Finite State Machine Lab Finite State Machine Module: Lab Procedures Goal: The goal of this experiment is to reinforce state machine concepts by having students design and implement a state machine using simple chips and a protoboard.

More information

JTAG-HS1 Programming Cable for Xilinx FPGAs. Overview. Revised January 22, 2015

JTAG-HS1 Programming Cable for Xilinx FPGAs. Overview. Revised January 22, 2015 1300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com JTAG-HS1 Programming Cable for Xilinx FPGAs Revised January 22, 2015 Overview The joint test action group (JTAG)-HS1 programming cable

More information

University of Florida EEL 3701 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Revision 0 12-Jun-16

University of Florida EEL 3701 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Revision 0 12-Jun-16 Page 1/14 Quartus Tutorial with Basic Graphical Gate Entry and Simulation Example Problem Given the logic equation Y = A*/B + /C, implement this equation using a two input AND gate, a two input OR gate

More information

Locktronics PICmicro getting started guide

Locktronics PICmicro getting started guide Page 2 getting started guide What you need to follow this course 2 Using the built-in programs 3 Create your own programs 4 Using Flowcode - your first program 5 A second program 7 A third program 8 Other

More information

Getting Started with STK200 Dragon

Getting Started with STK200 Dragon Getting Started with STK200 Dragon Introduction This guide is designed to get you up and running with main software and hardware. As you work through it, there could be lots of details you do not understand,

More information

Spartan -6 LX9 MicroBoard Web Connectivity On Ramp Tutorial

Spartan -6 LX9 MicroBoard Web Connectivity On Ramp Tutorial Spartan -6 LX9 MicroBoard Web Connectivity On Ramp Tutorial Version 13.2.01 Revision History Version Description Date 13.2.01 Initial release with support for ISE 13.2 tools Aug. 10, 2011 Page 2 of 30

More information

Tutorial: ISE 12.2 and the Spartan3e Board v August 2010

Tutorial: ISE 12.2 and the Spartan3e Board v August 2010 Tutorial: ISE 12.2 and the Spartan3e Board v12.2.1 August 2010 This tutorial will show you how to: Use a combination of schematics and Verilog to specify a design Simulate that design Define pin constraints

More information

AHA-1540C/1542C Installation Guide

AHA-1540C/1542C Installation Guide AHA-1540C/1542C Installation Guide 1 Getting Started This guide provides the steps required for basic installation of the AHA-1540C and AHA-1542C ISAto-SCSI Host Adapters. Procedures are the same for both

More information

My First FPGA for Altera DE2-115 Board

My First FPGA for Altera DE2-115 Board My First FPGA for Altera DE2-115 Board 數位電路實驗 TA: 吳柏辰 Author: Trumen Outline Complete Your Verilog Design Assign The Device Add a PLL Megafunction Assign the Pins Create a Default TimeQuest SDC File Compile

More information

Contents Getting Started GV-LPR Application Controls Installation Guidelines

Contents Getting Started GV-LPR Application Controls Installation Guidelines Table of Contents Getting Started 2 Check Package Contents...........................................2 Requirements....................................................2 Installations......................................................3

More information

EVDK Based Speed Sign Detection Demonstration User Guide

EVDK Based Speed Sign Detection Demonstration User Guide EVDK Based Speed Sign Detection Demonstration FPGA-UG-02049 Version 1.1 September 2018 Contents Acronyms in This Document... 4 1. Introduction... 5 2. Functional Description... 6 3. Demo Setup... 8 3.1.

More information

TEMIC 51T (Temic) EMULATION

TEMIC 51T (Temic) EMULATION Note: To use with frequencies above 40Mhz it will be required to use an emulator board that has been specially modified to obtain high frequency operation and will work only with the POD-51Temic. The EPROM

More information