XILINX WebPack -- testing with Nexys2 boards at USC (EE201L)

Transcription

1 XILINX WebPack -- testing with Nexys2 boards at USC (EE201L) Gandhi Puvvada 1 Before you start: 1.1 We assume that you have installed WebPACK on your desktop or laptop already. We assume that you have received from your TA a Nexys2-500 board and tested it using a bit file provided to you by following a procedure document (Addendum1_Nexys_2.pdf) provided to you.. 2 Download and save the test design files on your PC 2.1 Create the following directories: C:\xilinx_projects, C:\ModelSim_projects, and C:\Verilog The source verilog files and user constraint files (.v and.ucf) are held under C:\Verilog. It is good to hold a copy of the source files separately from the project directory for safe keeping purposes. 2.2 You are being given four zip files ( test_nexys2_verilog_verilog_file.zip, test_nexys2_verilog_bit_file.zip, test_nexys2_verilog_complete_project.zip, test_nexys2_verilog_ucf_file.zip). Download the zip files from the webpage specified on the BlackBoard into the directory C:\ on your PC. Make a directory called C:\BIT_files and extract test_nexys2_verilog_bit_file.zip in it. The test_nexys2_verilog.bit is deposited into C:\BIT_files. Make a subdirectory called test_nexys2_verilog under C:\Verilog. Move the two zip files, test_nexys2_verilog_verilog_file.zip and test_nexys2_verilog_verilog_file.zip to C:\Verilog\test_nexys2_verilog and extract to form C:\Verilog\test_nexys2_verilog\test_nexys2_verilog.v and C:\Verilog\test_nexys2_verilog\test_nexys2_verilog.ucf. Move the test_nexys2_verilog_complete_project.zip from C:\ to C:\xilinx_projects and then extract to form C:\xilinx_projects\test_nexys2_verilog directory. 3 Testing the WebPack: To hold your xilinx synthesis projects, you must have created a directory, called (say) C:\xilinx_projects under C:\ (or F:\xilinx_projects under F:\ if you plan to carry an USB memory stick with your project files so that you can work on your projects at home using your desktop PC as well as at school using the PCs in the labs. Then you can keep your source files in F:\Verilog). If you do not have patience to go through all the steps below to create a project and compile a test design, you can create the entire project directory by downloading test_nexys2_verilog_complete_project.zip and unzipping it under the C:\xilinx_projects directory. In fact we asked you to do that at the beginning of this handout thinking that you get too tired by this time. If you are not tired, then rename the project directory test_nexys2_verilog previously created and proceed. August 25, :55 am Xilinx WebPACK Installation 1 / 6 C Copyright 2008 Gandhi Puvvada

2 3.1 Invoke webpack by clicking on the Xilinx ISE 10.1 icon.. Or you can go through Start => Programs => Xilinx ISE Design Suite 10.1 => ISE => Project Navigator. 3.2 Create a new project (click on File => New Project). In the New Project Wizard - Create New Project dialog box, first make sure that the project location is C:\xilinx_projects\ (or F:\xilinx_projects ). Name the project test_nexys2_verilog (actually some arbitrary name). If you are working on our lab computers and if you are not using an USB memory stick, you may want to name the project with your short name as prefix, (for example, the student Mike would name it as Mike_test_nexys2_verilog). Finally when you are done, you can remove the project directory C:\xilinx_projects\Mike_test_nexys2_verilog. 3.3 The Device Properties dialog box comes up. Make sure the properties are selected as shown below. Pull-down August 25, :55 am Xilinx WebPACK Installation 2 / 6 C Copyright 2008 Gandhi Puvvada

3 3.4 Click Next in the create new source dialog box as we do NOT wish to create a new source file now. 3.5 In the Add Existing Sources dialog box, click on and point to the source files in the source files directory C:\Verilog\test_nexys2_verilog\. Note that we are copying the source files to the project directory in this process. Notice the button. Essentially we will have now two copies of the source files. Remember that it is a good idea to keep a copy of the source files safely away from the project directory. But at the same time, it is advantageous to keep a copy in the project directory so that the complete project directory along with the source files can be zipped and taken to another computer easily. The disadvantage of having two copies of the source files is that when you update one, you should not forget to update the other copy. August 25, :55 am Xilinx WebPACK Installation 3 / 6 C Copyright 2008 Gandhi Puvvada

4 3.6 Project Summary appears. Click Finish. 3.7 Notice the association of files. The choices are Implementation (for example.ucf files) or Simulation (a test bench) or All (core design file. the.v file). If you have a functional description of the core design, you usually will write a testbench. The test bench file should have file association with Simulation only. If needed, one can use the pull-down menu to correct the file association. The.ucf file provides association of the FPGA pins to the input/output ports in our design. Pull-down 3.8 Before you start synthesizing and/or implementing, it is important to select the TOP module (if it is not already selected (highlighted)); otherwise you will be synthesizing a lower module! In this project, of course, there is only one module, test_nexys2_verilog. 3.9 Double-click on (or right-click and select Run on) Synthesize-XST. It may be a good practice to expand the Synthesize-XST and run Check Syntax first. August 25, :55 am Xilinx WebPACK Installation 4 / 6 C Copyright 2008 Gandhi Puvvada

5 If the code is syntactically correct and is synthesizable, it will synthesize. A green check-mark or an yellow warning sign is displayed. Usually warnings can be ignored Now run "Implement Design". Unfortunately in this 10.1 release of ISE, our design fails. The error shown under the console tab is reproduced below. ERROR:Place: A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <BUFGP1/BUFG> is placed at site <BUFGMUX_X2Y10>. The IO component <Btn3> is placed at site <H13>. This will not allow the use of the fast path between the IO and the Clock buffer. If this suboptimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the.ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the.ucf file to override this clock rule. < NET "Btn3" CLOCK_DEDICATED_ROUTE = FALSE; > Since Digilent designed this board with Btn3 at not so good site, we can not do much about this. We can try not to use Btn3 in our designs. As suggested, we add the line "NET "Btn3" CLOCK_DEDICATED_ROUTE = FALSE; " to our.ucf file using a text editor such as notepad or wordpad. The test_nexys2_verilog.ucf file in test_nexys2_verilog_complete_project.zip is an edited file with the above line included at the bottom Rerun the implementation step. Just after editing the.ucf file: After rerun: 3.11 Right click on Generate Programming File and right-click on Properties. (The next few lines are important as many students quite often forget to do this). In the Process Properties dialog box, choose the Startup options category. Select the FPGA Start-Up Clock as JTAG Clock. Click OK. Basically the FPGA boards (used in our courses) use a programing mechanism called Boundary Scan programming mechanism which uses JTAG clock. So we need to select the JTAG Clock as stated above. August 25, :55 am Xilinx WebPACK Installation 5 / 6 C Copyright 2008 Gandhi Puvvada

6 3.12 Right click on Generate Programming File and run To configure the device (i.e. to download the.bit file into the FPGA) using Xilinx impact tool, we need to have a parallel port on our PC and a special parallel port to JTAG cable. Since most of our computers do not have parallel ports anymore, we ill not use this mechanism of downloading a.bit file. Instead we use the Adept tool as demonstrated in a separate file ( Addendum1_Nexys_2.pdf) Close the project and exit ISE Use Adept ExPort and download the bit file test_nexys2_verilog.bit and verify the board operation Now it is time to celebrate!!!! August 25, :55 am Xilinx WebPACK Installation 6 / 6 C Copyright 2008 Gandhi Puvvada