Setup/Hold. Set Up time (t su ):

Transcription

1 Lecture 10 Agenda

2 Set Up time (t su ): Setup/Hold Minimum amount of time the data is to be held steady prior to the clock event Hold time (t h ): Minimum amount of time the data is to be held steady after the clock event

3 Metastability Metastability in electronics is the ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium (between 1 and 0) or metastable state. Metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant for specified setup (t su ) and the hold (t h ) times. Metastability is dependent on FF gain bandwidths Metastable state State_0 State_1 D D Q Q clk clk D Q

4 Metastability- 4 possibilities clk D Q clk D Q clk D Q clk D Q

5 Mechanical Switches Most (except mercury) mechanical switches will bounce. Vdd Push Button out 1-20ms out

6 Why is bouncing a problem? Will cause metastibility if bounce occurs on a clock edge Vdd Push Button out D Q Q clk clk D Q Will record numerous events

7 What is a synchronizer? A circuit to reduce the possibility that an asynchronous signal cases metastability. A signal from the outside world or from another clock domain is asynchronous Since the signal is asynchronous it can change on a clock edge and cause metastability A synchronizer circuit assumes the signal is not bouncing

8 Eliminating Bounce with a Synchronizer Cycle time (i.e. clock period) must be > total bounce time get_rdid q1 D Q D Q get_rdid_debounce clk clk get_rdid q1 get_rdid_debounce

9 Eliminating Bounce with a Counter Increment a counter anytime async_in!= sync_out Clear the counter anytime async_in == sync_out When counter = MAX async_in =!sync_out Critical constraint: How long will bounce stay at: 0 for a low going input 1 for a high going input async_in 3ms 3ms 1ms 1ms sync_out

10 Eliminating Bounce with a Counter (cont.) 1ms 1ms async_ in counter clr cnt clr cnt clr cnt clr cnt=max clr cnt clr cnt clr cnt clr cnt=max clr sync_out For 10MHz clock and a 16-bit counter, input must be stable for 16 to detect a change max_ count 2 frequency ms

11 User Constraints File (UCF) Template UCF for the Spartan 3E Starter board is in the back of the Spartan 3E Starter Kit User Guide Most of the constraints in a UCF file associate a resource I/O with an FPGA pin Syntax is NET instance_name LOC= location <options>; Where instance_name is an I/O in your top level design location is a pin on the FPGA <options> are IOSTANDARD, PULLUP, etc.

12 Spartan-3E supported I/O standards Single Ended LVTTL - Low Voltage TTL (3.3V) LVCMOS - LOW Voltage CMOS (1.2V 3.3V) PCI - Peripheral Component Interface (3.3V) GTL Gunning Transceiver Interface HSTL High Speed Transceiver Logic (1.5V or 1.8V) SSTL3 Stub Series Terminated Logic (3.3V) SSTL2 Stub Series Terminated Logic (2.5V) SSTL18 - Stub Series Terminated Logic (1.8V) Differential LVDS Low Voltage Differential Signaling (350mV P-P) BLVDS Bus LVDS (350mV P-P, requires ext. resistor termination) LVPECL Low Voltage Positive Emitter Coupled Logic (850mV P-P) LDT - Lightning Data Transport (2.5V VCCIO) MINI_LVDS LVDSEXT - LVDS Extended ( mV P-P) RSDS - Reduced Swing Differential Signaling TMDS - Transition Minimized Differential Signaling PPDS - Point-to-Point Differential Signaling Source: Spartan-3 Generation FPGA User Guide

13 Single Ended/Differential

14 Benefits of Differential Signaling Ground Offset Tolerance The receiver only interprets the signal difference. Reference voltage is user controlled Allows for longer signal distances Gives twice the noise immunity of a single ended system Noise is most often common mode Allows for smaller signals EMI and crosstalk resistant with balanced lines Same amount of noise impressed on each signal. Minimization of Common Mode Noise EMI Radiation Opposing EM fields tend to cancel.

15 User Constraints File (UCF) For example FPGA pin C9 is connected to the on-board crystal oscillator To use the crystal need to specify: The net that connects to it (CCLK) The IO interface standard and voltage level (LVCMOS33) FPGA module rdid_master(input CCLK,...);... endmodule C9 Crystal

16 UCF syntax # Pin assignment for LEDs NET "LD7" LOC = "G1" ; # Bank = 3, Signal name = LD7 NET "LD6" LOC = "P4" ; # Bank = 2, Signal name = LD6 # Pin assignment for SWs NET "SW7" LOC = "N3"; # Bank = 2, Signal name = SW7 NET "SW6" LOC = "E2"; # Bank = 3, Signal name = SW6 # clock pin for Basys2 Board NET "mclk" LOC = "B8"; # Bank = 0, Signal name = MCLK LOC (LOCation) is defined by the BASYS2 PCB layout Net name is user defined # - Comment

17 BASYS2 Development Board Build programming file (bit stream) using Xilinx ISE Program via USB port using Digilent s Adept software Both are free Source: Digilent Basys2 Reference Manual

18 BASYS2 Development Board Board Powered via USB port Power switch ON when red LED lit Source: Digilent Basys2 Reference Manual

19 User I/O BASYS2 Development Board Four momentary switches Eight slide switches Eight LEDs Four digit, seven segment display Source: Digilent Basys2 Reference Manual

20 BASYS2 Development Board Download ISE WebPack: Download Digilent Adept System: Source: Digilent Basys2 Reference Manual

21 Xilinx ISE Start Xilinx 64 bit Project Naviagator Click on New Project.

22 Indicate device Xilinx ISE

23 Xilinx ISE Add ucf and Verilog module Project > Add Source

24 Xilinx ISE Edit ucf and Verilog as required

25 Xilinx ISE Specify FPGA Start up Clock Process > Process Properties > Startup Options

26 Xilinx ISE Create bit stream

27 Digilent Adept power up BASYS2 PCB, start Adept

28 Digilent Adept Indicate Config (bit stream) file

29 Program Power LED will flash Digilent Adept Slide switches should now control LEDs

30 Lab4 (40 points) Lab 4 Using Xilinx ISE Webpack and Digilent Adept, program FPGA to control each of the eight LEDs using the eight slide switches. Deliverables Verilog code UCF file Screen shots of ISE Demonstration of the LEDs/switches, either in person or via video.