Experiment # 4 Introduction to FPGAs - Detour Signal Lab

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1 1. Synopsis: Experiment # 4 Introduction to FPGAs - Detour Signal Lab This lab introduces the use of Field Programmable Gate Arrays (or FPGAs, for short) for prototyping of digital circuits. Through the design of a simple state machine for controlling the Detour Signal lights, this lab introduces the digilab experimental FPGA board and demonstrate FPGA design flow. The experimental FPGA board houses a Xilinx Spartan-2 FPGA along with various input and output devices like push buttons, light-emitting diodes and seven segment displays. This lab introduces how each of those input and output devices can be used in EE 201L designs. 2. Description of the Circuit: You all know the detour signal at road repair sites. It normally has four groups of lights - GL (stands for Group Left), G1, G2 and GR - controlled as shown to indicate detour to the right or detour to the left. Assume that we have a L/R switch to choose left or right signal. The state machine looks at this switch only when it is in the Idle state and then performs the required (left or right) sequence and comes back to Idle state. Idle State R1 State (G1 is ON) R12 State (G1, G2 are ON) R123 State (G1, G2, GR are ON) Idle State L1 State (G2 is ON) L12 State (G2, G1 are ON) GL G1 G2 GR In this lab we will implement the 7-state controller using D-flip flops in One-hot method. Fig 1: Four groups of LEDs in different states The state machine given below is almost complete. Some obvious state transition conditions have been intentionally left out. Complete the state diagram before proceeding. (Recall that an unconditional state transition can be labelled with 1 as the condition). L123 State (G2, G1, GL are ON) ~Reset L/R=0 R1 R12 R123 Idle L/R=1 L1 L12 L123 Fig 2: State diagram for the Detour Signal design ee201l_detour.fm [Revised: 2/4/08] 1/14

2 3. Introduction to the FPGA Board: An FPGA consists of an array of logic blocks connected via programmable interconnect. A typical FPGA contains anywhere from 64 to tens of thousands of logic blocks and an even greater number of flip-flops. Each configurable logic block (CLB) has one or more D-flip flops and some combinational logic such as muxes, etc. Each CLB is capable of performing a reasonably complex function such as implementing a full adders. Our objective in this lab is to understand how to use FPGAs and a more discussion on the architecture of FPGAs can be found in Addendum #2. Xilinx TM Inc. ( is one of the major FPGA vendors. We will be using the XC2S30 device from Xilinx s Spartan-2 family of FPGAs. It has approximately 30,000 gates organized in configurable logic blocks (or CLBs). The XC2S30 device used in this lab comes in a TQ144 package. ( TQ stands for Thin Quad while 144 represents the number of pins in the package) 3.1 FPGA Boards: Digilab D2XL + Digilab DIO1 Board Digilab D2XL TM board from Digilent Inc. ( is the mother board for the Digilent s FPGA kit used in our labs. The board features Xilinx Spartan-II XC2S30 FPGA and two expansion slots labelled as E and F. These slots are used to interface the D2XL system board with various daughter boards (like DIO1) that Digilent produces. The board also has a push button (referred to as BTN_MAIN) and a LED (LED_MAIN). We will generally use this button as system reset and this LED to observe the system clock. Digilab DIO1 is one of the several daughter boards that can be connected to the D2XL motherboard. This board provides a wide range of I/O needed for our labs. It has five push buttons (labelled BTN1 through BTN5), eight LEDs (LD1-LD8), eight switches (SW1-SW8) and four common anode seven-segment displays (SSD). The 8 LEDs (LD1-LD8) on the DIO1 board are connected through an 8-bit latch which needs to enable by connecting its gate control (labelled as LDG ) to VDD. More details about the FPGA board can be found in Addendum # Seven Segment Display: A seven segment display (SSD) is nothing but seven LEDs arranged in a grid fashion; plus, an eighth LED serving as the decimal point. The LEDs are labelled a, b, c, d, e, f and g, starting from the top and going clock-wise (Fig 3). In order to make an LED glow, a logical 0 must be sent to the cathode and a logical 1 to the anode. To avoid redundancy of connection, it is possible to connect the anode of all the eight LEDs of a SSD together to form a single anode control and select individual LEDs by exercise control over the cathode terminals (this is called the common anode configuration). When connected in this fashion each SSD requires only 9 pins instead of 16. To illuminate a certain digit the common anode control is set to 1 and the appropriate cathodes are sent to 0. Figure 3 shows the seven segment code for each of the ten decimal digits. The following Flash animation graphically explain how SSDs are connected in the Digilab DIO1 board: ee201l_detour.fm [Revised: 2/4/08] 2/14

3 Figure 3: Seven Segment Display 3.3 Output Scanning Mechanism For SSDs DIO1 board has four SSDs and if they are connected in the above configuration they would require 36 pins (9x4) of the FPGA. To lower the number of FPGA pins required to show a specific value on the four SSDs, the designers of the board have connected the cathodes of all four SSDs together (labeled as Ca through Cg and Dp for the decimal point). Therefore, at any given time only one of the SSDs can be illuminated. However, if we select each SSD (by providing a 1 to the common anode for that SSD) and send data to it (i.e., sending zeros for segments we want illuminated) at a high rate, an allusion of constantly lit SSDs can be created. We called this output scanning mechanism for the SSDs. In our designs, we will use 2-bits of a counter to select the seven segment code to be sent on the Ca through Cg bus. When these bits are 00, cathode data for the first SSD is sent, when they are 01 data for the second SSD is sent, and so on. The same two bits are decoded to produce the four anode control signals. That is, when the bits are 00, anode control of the first SSD is enabled, when they are 01, anode control of the second is enabled and so on. Note that the order of inputs of the multiplexer controlling the cathodes should match the order of decoded anode control signals in order for the digits to appear in the correct order on the four SSDs. Fig 4 shows this output scanning in form of a timing waveform. Figure 4: Output Scanning for SSDs ee201l_detour.fm [Revised: 2/4/08] 3/14

4 4. FPGA Design Flow: In this section we will discuss the design flow for implementing a Xilinx Schematic design on to the FPGA on our Digilab board. Figure 5 shows the design flow that we will follow for this class. 4.1 Design Entry: We will use Xilinx Schematic Editor to specify the circuit schematics. In addition to creating the schematic for the core state machine, we will need to create a wrapper or top design which connects signals of the state machine to the input/output devices like the switches, push buttons and LEDs, etc. To do so, Xilinx library provides the following special components which we will be needing: Input/Output Buffers (I, O): Xilinx FPGAs require that we connect buffers to the I/O markers to ensure that signals entering or leaving the FPGA are of appropriate strength. Xilinx component library provides special input buffers (symbol: I) and output buffers (symbol: O) for this purpose. Enter Core Design Simulate Enter Top Design Specify Constraints Synthesize Program the FPGA Global Buffers (GP): Xilinx FPGAs have special buffers Fig 5: Design flow called Global Primary Buffers (symbol: bufgp) which must be used to buffer incoming signals such as clock, reset, etc. with high-fanout. For the clock pin, for example, after the input marker, you place a global buffer (bufgp) before taking the clock to circuit elements like flips-flops, counters, etc. You can not use general purpose buffers (symbol: buf) or input buffers (ibuf) for the clock signal. 4.2 Synthesis & Implementation: Once the circuit has been specified (in a schematic file), Xilinx Synthesis Tool (XST) can decide how to use the configurable logic and the programmable interconnect in the FPGA to implement the desired circuit. The process of interpreting the design, simplifying the circuit and then creating an implementation based on certain target FPGA, is called synthesis and implementation. We will use XST, launched from within the Project Navigator, to synthesize the design and generate a configuration bitstream for the FPGA. 4.3 Programming: We program (or configure) the FPGA by downloading the configuration bitstream generated by the synthesis tool onto the FPGA through the parallel or USB port of a PC. We will use Xilinx s impact configuration/programming software to download the bitstream onto our FPGA board using the parallel port. IF you do not have a parallel port on your PC, then you can borrow special USB cable from your TA and follow the handout and webcast separately posted. This will be quite lengthy and inconvenient. Sorry! ee201l_detour.fm [Revised: 2/4/08] 4/14

5 5. Prelab: Q 5. 1: What does FPGA stand for? (1pt) Q 5. 2: What is the name of the FPGA family that we are using in this lab? (1pt) Q 5. 3: Which FPGA of this family are we using? (1pt) Q 5. 4: What does TQ144 denote? (1pt) Speed grade Package Serial number Model number Q 5. 5: The state memory is usually implemented using: (2pts) And-Or gates RAM Flip flops All of the above Q 5. 6: Next State Logic (NSL) is a purely (combinational/sequential) circuit. (2pts) Q 5. 7: We will implement the detour signal controller using One-Hot method. How many D- flip flops are needed to implement the controller? (2pts) ee201l_detour.fm [Revised: 2/4/08] 5/14

6 6. Procedure: 6.1 Download the zip file ee201l_detour_exer.zip containing the Xilinx ISE project from the Blackboard (under Course Documents). Extract the zipped project into the projects folder (C:\xlinx_projects\) and open the project in Xilinx Project Navigator. Now, if you wish, you can now follow procedure steps 6.10 through 6.14 to synthesize/implement the given incomplete design and download it on to your board to get familiar these steps (and also test your board). This will help you to understand how the incomplete design (both core and top put together) is complete in its own way! Part 1: Completing the core design 6.2 Open the ee201l_detour.sch schematic file. This is an incomplete implementation of the state machine. Complete the design by adding new state memory (flip flops), next state logic and output function logic. Notice the two different types of flip flops used - FDP and FDC. Look up the difference between them using the Symbol Info button in the schematic editor s Symbols tab. Your completed design must correctly implement the state machine from Figure 2 and also produce the four output signals (outputs of the OFL): GL, G1, G2 and GR. 6.3 Use the provided Verilog test fixture (ee201l_detour_tb.v) to test your design. Please note that if the you do not see the signals in the waveform window, there probably is a mistake in the schematic. Also, make sure to use the same signal names for primary inputs and outputs (signals to which I/O markers are attached) as those used in the test bench. Primary inputs of the design are:, RESET and LR_BAR; whereas the primary outputs are: GL, G1, G2, GR and the one-hot coded states I, L1, L12, L123, R1, R12 and R123. Show the waveform of the completed and functionally correct design to your TA. Part 2: Completing a simple top design In Part 2 of this lab, our goal is to implement the detour design onto the FPGA board. For this purpose we will design a simple top schematic that wraps or encapsulates our core state machine and connects its inputs and outputs either to the input and output devices on the FPGA board or to signals such as generated within the top. No changes in the core state machine design will be made and all the necessary logic (often called glue logic ) for interfacing the core design to the input/output components will reside in the top file. For the simple top, we will use one of the switches (SW8) on the DIO1 board to exercise the left/ right detour selection (i.e., to produce the LR_BAR signal) and the eight LEDs (LD1 through LD8, in groups of two each) to create the detour arrow growing towards left or growing towards right and one of the four seven-segment LED displays to show R or L depending upon the state of the L/R signal. Push button on the main D2XL board (BTN1MAIN) will be used as RESET and the LED on the same board will display our system clock. The layout of Digilab Digital I/O 1 (DIO1) (together with I/O resource assignments for this lab) is shown in Figure 6 below. ee201l_detour.fm [Revised: 2/4/08] 6/14

7 RESET L or R LD1MAIN BTN1MAIN GL GL G1 G1 G2 G2 GR GR LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 A1 A2 A3 A4 LR_BAR BTN1 BTN2 BTN3 BTN4 BTN5 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 Fig 6: Layout of the Digilab DIO1 board for the simple top design (Part 2). 6.4 Switch the Sources window view from Behaviroral Simulation to Synthesis/Implementation. You should see that the top-most schematic file in the hierarchy is ee201l_detour_top.sch. This is an incomplete top design. Understand how the provided (incomplete) design works. 6.5 On sheet 1 of ee201l_detour_top.sch, complete the connections/logic for the following signals: LR_BAR (SW8), G1 (LD3 & LD4), G2 (LD5 & LD6) and GR (LD7 & LD8). Notice the special buffers connected to the I/O marker labeled as SW8 (ibuf) and LD1/LD2 (obuf). Look up the details about these buffers (using the Symbol Info button) and be sure to use appropriate buffers for each unconnected signal. PORT and RESET are connected using a third kind of special buffer (bufgp). This buffer is only needed for global signals like the clock and reset. We will leave the state_onehot(15:0) unconnected. During synthesis, the Xilinx XST tool will issue a warning inform you that you left these unconnected. Ignore this warning. 6.6 On sheet 2 of ee201l_detour_top.sch, complete the circuit necessary to show L when LR_BAR is 1 and R when it is 0. Custom-made 8-bit wide 2x1 mux is provided in the project for you to use, if necessary. Figure 3 shows the naming of the LEDs in the seven segment display. In the top schematic (ee201l_detour_top.sch), we have added the glue logic and connected signals of the core design to the I/O markers labeled for the various input and output devices on the board. Each of these input/output devices (switches, buttons & LEDs) is connected to a unique pin of the FPGA and in the next step we will make the connection between the I/O markers in the top schematic and the physical FPGA pins to which various devices are connected. By associating each I/O marker in the top design with a pin number, we can ensure that in the final downloaded design, these signals will be tied to the components connected to the respective FPGA pins. For instance, pin number 91 of the FPGA is connected to the on-board clock generator. Therefore, in order to connect the on-board clock generator to the input of the clock divider circuit in the top design, we must associate the I/O marker labeled PORT to pin 91. This is done in the User Constraint File, or UCF file. 6.7 Go to the project directory (C:\Xilinx_Projects\ee201l_detour_EXER) and locate the UCF file (ee201l_detour.ucf). Open this file in a text editor (such as Notepad/Wordpad). Using ee201l_detour.fm [Revised: 2/4/08] 7/14

8 the table of mapping between FPGA pins and I/O devices given at the end of this handout identify wrong pin associations and correct the mistake(s). Save the file and return to the Project Navigator. You are now ready to synthesize the design and program the FPGA with your new design. 6.8 In the Project Navigator sources pane, select the top schematic. In the Processes window, right-click on Generate Programming File and select Properties. Click the Startup options tab and select JTAG clock for FPGA Start-Up Clock. Click OK. 6.9 In the Project Navigator window, in the Processes for Current Source pane, rightclick and run (or double-click). If the design is synthesized successfully, you will see green colored check marks (or exclamatory marks, indicating some warnings but no errors) next to it. Then right-click and Run (or double-click) Make sure that Digilab boards (D2XL connected to DIO1) are connected to the PC via parallel cable. Also, the boards should be powered up using a 6V (or 5V) DC power supply. The SW1 switch (PORT - JTAG switch) on the main D2XL board should be set to JTAG side. In the process pane, expand the Generate Programming File tab under the. Double click on the tool. A programming bitstream (ee201l_detour_top.bit) is generated in the project directory When the bit-file generation has completed successfully, Xilinx Programming tool impact will open and a wizard will guide you through the set up of your board. All default selections (Parallel port LPT1, etc.) are valid for our setup. If prompted, select the bit file ee201l_detour_top.bit. When the wizards finishes, you will see an icon representing the FPGA chip in the main impact window. Download the.bit file by selecting the FPGA icon and right click and select program (or by choosing Operation -> Program ). You should see a progress indicator as the bitstream is downloaded on the FPGA If programming is successful, the LD1 on the main D2XL board (LD1MAIN as we labeled it in the top schematic) will flash. Check the operation of your design by operating SW8 and seeing the right sequence of LEDs glowing to indicate right detour or the left detour and the right direction indicator appearing on the SSD. Show the correct implementation to your TA. Part 3: Implementing a more complex top In this part, you will modify the top to also show the state number on one of the SSD along with the direction indicator. To do so, you will employ the output scanning mechanism necessary to use multiple SSDs. Consult your TA for more details on output scanning. Once you understand how output scanning works, proceed with the following procedure steps In ee201l_detour_top.sch (sheet 1) you are provided with a bus named state_onehot[15:0]. This 16-bit one-hot coded vector has to be converted to 4-bit hexadecimal number which can then be converted to the appropriate seven-segment code representing each hex digit. Necessary (custom-made) components are provided with A1 A2 A3 A4 SSD1 AN1 SSD2 AN2 SSD3 AN3 LorR SSD4 AN4 ee201l_detour.fm [Revised: 2/4/08] 8/14

9 this project. See the components below and also understand the schematic underneath each of these component. You can use these components or design your own and use them. The goal is to show the state number ( 0 for Idle state, 1 for L1, 2 for L12 3 for L123, 4 for R1, 5 for R12, 6 for R123) on SSD1 (corresponding to AN1) and the direction indicator ( L or R ) on SSD4 (corresponding to AN4). Complete the schematic to implement this new top schematic Synthesize and implement the design using the same procedure steps that you followed in Part 2 (steps 6.11 onwards) and show the working design to your TA.. ee201l_detour.fm [Revised: 2/4/08] 9/14

10 7. Lab Report: Name: Lab Session: Date: TA s Signature: For TAs: Pre-lab (10): Implementation ( ): Report (out of 40): Comments: Q 7. 1: What are the two different D-flip flops that we are using in this lab? What is the difference between them? (2pts) Q 7. 2: Name 2 more D-flip flops that are available in the Xilinx library and briefly explain how are they different from the ones that we are using in this lab.(8pts) Q 7. 3: Q 7. 4: Which pin of the FPGA is connected to the BTN1MAIN on the D2XL board?. (4pts) Which three special buffers are needed for signals that connect to the input and output devices (including the on-board clock generator)? Gives their names and whether they are needed to connect inputs or outputs or both. (6pts) Q 7. 5: Assume that the frequency of the clock entering the FPGA is 25MHz. Notice that we are dividing the input clock by using counters. Calculate the frequency of the divided clock that triggers the detour signal state machine. (5pts) Q 7. 6: Why are we dividing the clock? (5pts) Q 7. 7: What will happen if the output scanning frequency is (much) lower than the system clock s frequency in this design? (10 pts) ee201l_detour.fm [Revised: 2/4/08] 10/14

11 Digilab DIO1 (Digital I/O 1, Rev B) to Digilab D2XL (XC2S30) DIO1B Pin Signal D2XL Pin Signal FPGA Pin DIO1B Pin Signal D2XL Pin Signal FPGA Pin A1 F39 88 A2 F40 18 A3 F37 64 A4 F38 42 A5 F35 3 A6 F36 76 A7 F33 5 A8 F34 4 A9 F31 7 A10 F32 6 A11 F29 11 A12 F30 10 A13 F27 13 A14 F28 12 A15 F25 20 A16 F26 19 A17 F23 22 A18 F24 21 A19 F21 26 A20 F22 23 A21 F19 28 A22 F20 27 A23 F17 30 A24 F18 29 A25 F15 40 A26 F16 31 A27 F13 43 A28 F14 41 A29 F11 46 A30 F12 44 A31 BLU F9 48 A32 PS2D F10 47 A33 GRN F7 50 A34 PS2C F8 49 A35 RED F5 54 A36 HS F6 51 A37 VCC F3 VCC A38 VS F4 56 A39 F1 A40 VU F2 VU B1 CA E39 58 B2 SW1 E40 57 B3 CB E37 60 B4 SW2 E38 59 B5 CC E35 63 B6 SW3 E36 62 B7 CD E33 66 B8 SW4 E34 65 B9 CE E31 74 B10 SW5 E32 67 B11 CF E29 77 B12 SW6 E30 75 B13 CG E27 79 B14 SW7 E28 78 B15 DP E25 83 B16 SW8 E26 80 B17 BTN2 E23 85 B18 BTN1 E24 84 B19 BTN4 E21 87 B20 BTN3 E22 86 B21 A1 E19 94 B22 LD1 E20 93 B23 A2 E17 96 B24 LD2 E18 95 B25 A3 E B26 LD3 E16 99 B27 A4 E B28 LD4 E B29 E B30 LD5 E B31 E9 115 B32 LD6 E B33 E7 118 B34 LD7 E8 117 B35 BTN5 E5 121 B36 LD8 E6 120 B37 VCC E3 VCC B38 LDG E4 122 B39 E1 B40 VU E2 VU ee201l_detour.fm [Revised: 2/4/08] 11/14

12 EE201L - Introduction to Digital Circuits Experiment # 4 FDC FDC FDC QL1 QL12 QL123 D Q D Q D Q C C C A A CLR CLR CLR RESET RESET FDP RESET PRE QL123 QI D Q C B B L LR_BAR LR_BAR R INV L R QL123 GL QI C C GL QL123 QL12 R1 OR2 G1 R12 G1 R123 QL1 QL12 D D QL123 OR4 G2 GR G2 GR QL1 QL12 QL123 L1 L12 L123 Experiment: Designed by: USC VSoE CENG EE201L Lab Detour Sheet Detour core design Drawn by: Student: Date Date Date I ee201l_detour.fm [Revised: 2/4/08] 12/14

13 EE201L - Introduction to Digital Circuits Experiment # 4 VCC CB8CE CB16CE CB8CE BQ(15:0) CQ(7:0) AQ(7:0) Q[15:0] Q[7:0] Q[7:0] PORT CE CEO CE CEO CE CEO PORT C TC C TC C TC A A GP CLR CLR CLR Btn1Main GL RESET GP O O LD1 LD2 LD3 RESET ee201l_detour LD4 BQ(15) L RESET L R B B GL LD5 LR_BAR GL SW8 LR_BAR I state_onehot(0) G1 G2 GR L1 L12 L123 R1 R12 G1 G2 GR L1 L12 VCC L123 R1 R12 R123 C C L1 state_onehot(1) R123 O R O LD6 LD7 LD8 LDG LD1MAIN L12 state_onehot(2) L123 state_onehot(3) R1 R12 state_onehot(4) state_onehot(15:0) state_onehot(5) R123 state_onehot(6) state_onehot(7) state_onehot(8) Converting the current state information into a 16-bit one-hot coded number (useful in Part 3) state_onehot(9) state_onehot(10) state_onehot(11) D D state_onehot(12) state_onehot(13) state_onehot(14) state_onehot(15) Experiment: Designed by: Student: USC VSoE CENG EE201L Lab Sheet Detour TOP schematic (Sheet 1/2) Drawn by: Date Date Date I I I ee201l_detour.fm [Revised: 2/4/08] 13/14

14 EE201L - Introduction to Digital Circuits Experiment # 4 SSD_L(5) A A O SSD_L(7:0) SSD_out(7:0) SSD_out(4) SSD_L(7) VCC SSD_L(0) VCC SSD_L(1) SSD_L(2) SSD_L(3) SSD_L(4) SSD_L(6) E E8 SSD_out(0) SSD_out(1) SSD_out(2) SSD_out(3) SSD_out(5) SSD_out(6) SSD_out(7) O O O O O O O Ca Cb Cc Cd Ce Cf Cg Dp VCC B B An1 An2 An3 An4 C C D D Experiment: Designed by: USC VSoE CENG EE201L Lab Sheet Detour TOP schematic (Sheet 2/2) Drawn by: Student: Date Date Date ee201l_detour.fm [Revised: 2/4/08] 14/14