Local Bus (IFC) Block Diagram of T4240 Block Diagram of T4240QDS T4240QDS Features Photos SERDES DDR

Transcription

1 September 2013

2 The T4240QDS system is a T4240 based development system architecture developed to serve the internal silicon validation, performance, test and application teams. This system is offered stand alone for lab and board farm use or in a 4u chassis for FAE, marketing and customers. This common platform replaces both the test card and development systems used in the past, thus promoting cost savings and environment for multi-team codevelopment. 2

3 Block Diagram of T4240 Block Diagram of T4240QDS T4240QDS Features Photos SERDES DDR Local Bus (IFC) TSEC SPI SDHC USB UART and General IO I2C System Clocking T4240 Requirements and System Power Implementation Software Support : SDK v1.4 Q&A 3

4 PCIe PCIe PCIe PCIe srio srio Interlaken LA-1 SATA 2.0 SATA x 64-bit, dual-threaded cores w/ AltiVec up to 1.8GHz Power Arch Power Arch Power Arch Power Arch Power e6500 Arch Power e6500 Arch Power e6500 Arch Power e6500 Arch Power e6500 Arch Power e6500 Arch Power e6500 Arch Power e6500 Arch e6500 e6500 e6500 e KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache eopenpic PreBoot Loader Security Monitor Internal BootROM Power Mgmt SD/MMC SPI 2x DUART 2x I 2 C IFC 2 x USB2.0 w/phy Clocks/Reset GPIO CCSR SEC PME Pre- Fetch 2MB Banked L2 2MB Banked L2 2MB Banked L2 CoreNet Coherency Fabric PAMU PAMU PAMU QMan BMan RMAN RMan DCE FMan Complex FMan Parse, Classify, Distribute Buffer 1G 1G 1G 10G 10G 1G 1G 1G FMan Parse, Classify, Distribute Buffer 1G 1G 1G 10G 10G 1G 1G 1G 512KB Plat Cache 512KB Plat Cache 512KB Plat Cache Peripheral Access Mgmt Unit DMAx2 32 Lanes up to 10GHz SerDes MT/s 64b DDR3 w/ecc 64b DDR3 w/ecc 64b DDR3 w/ecc Data Path Acceleration Architecture FMan Parse/Class/Distribute/Policing QMan Queuing, Scheduling, Shaping BMan Buffer Manager Rman RapidIO Manager PME Reg-ex Pattern Matcher SEC Wireless, SSL and IPSec Encryption DCE Data Compression Engine TCP/IP offload 40Gbps 64B 20Gbps IMIX 10Gbps IMIX 20Gbps 4KB Real Time Debug Watchpoint Cross Trigger Perf Monitor CoreNet Trace Aurora 4

5 IFC Card NAND ADM NOR NOR PromJet MUX XAUI / HiGig / (Q)SGMII XAUI / HiGig / (Q)SGMII Slot 1: x8 Slot 2: x8 XBAR SD1 DDR1 DDR2 DDR3 DDR3/3LP 240p DDR3/3LP 240p DDR3/3LP 240p DDR3/3LP 240p DDR3/3LP 240p DDR3/3LP 240p XAUI / HiGig / (Q)SGMII / XFI XAUI / HiGig / (Q)SGMII PEX / Interlaken PEX / SRIO PEX PEX / SRIO / SATA Slot 3: x8 Slot 4: x8 Slot 5: x16 Slot 6: x8 Slot 7: x16 Slot 8: x8 Aurora XBAR XBAR XBAR SD2 SD3 SD4 GVDD DVDD/ etc. VDD SVDD/ XVDD I2C1 PMBus PWR LDO PWR VID 4Φ PWR LDO PWR I2C Route + Volt. Trans 1.5V/1.35V PMBus, Slots, Devs, etc. RMT SATA JTAG CCS cfg_xyz IDT IDT IDT 841NT IDT 841NT 841NT 841NT4 SDxCLKx T4240 QIXIS FPGA DDRCLK (option) IDT 840NT4 SYSCLK DDRCLK NET1 NET2 Symmetricom IEEE 1588 IDT 840NT4-01 PHYs 1588_CLKOUT 1588_CLKIN GTX_CLK125x USBCLK TSEC IFC UART SPI ISO SPI SPI XCVR SER1 SER2 USB1 USB2 PROT USB SDHC PROT SDHC emmc 5

6 T4240 Silicon - Supported with JD socket, Tyco socket and direct attach. DDR Controllers Three independent DDR3 controllers supporting data rates up to 2133 MHz. Two DDR3/DDR3LP 64-bit/ECC UDIMM or RDIMMs per controller. DDR power supplies 1.5V or 1.35V nominal to all devices with automatic tracking of VTT/VREF. SerDes Two 8x front side banks with high-speed crosspoint switch fabric routable to two slots or four ipass x4 connectors. SGMII / QSGMII. HiGig / XAUI / XFI. ipass connectors allow evaluation via Cisco RDS or board-to-board traffic. Two 8x back side banks with high-speed crosspoint switch fabric routable to four slots or Aurora/SATA connectors. PCI Express 2.0/3.0. srio 2.0. Interlaken LA. SATA

7 IFC/Local Bus High-speed side. NAND flash: 8-bit, async or sync, up to 2GB, interposer-based sockting, 16 virtual banks. NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB. GASIC: Minimal target (within Qixis FPGA). IFC Debug/Development card. Low-speed side (de-multiplexing handled within FPGA). NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB, 16 virtual banks. PromJET rapid memory download support. Ethernet TSEC1/TSEC2 connect using RGMII to 10/100/1G PHY: VSC8641. IEEE-1588 support via Symmetricom board. Other IO Two USB 2.0 ports with integrated PHYs: one type-a, one micro-ab. esdhc card slot and on-board emmc device. espi bootable memory. Serial ports (2), I2C ports (4) 7

8 Clocks System and DDR clock (SYSCLK, DDRCLK ): IDT co-developed. Switch selectable to one of 16 common settings in the interval 33MHz-166MHz, SW selectable to 1MHz increments. SERDES clocks. Provides , or MHz clocks to all SerDes blocks and slots. QIXIS System Logic FPGA Manages system power and reset sequencing. Manages DUT, board, clock, etc. configuration for dynamic shmoo. Collects V-I-T data in background for code/power profiling. General fault monitoring and logging. Runs from ATX hot power rails allowing operation while system is off. Remote control/configuration via I2C (Komodo). 8

9 Power Supplies Sourced by either Sparkle 750 ATX or 700 1U bulk supplies. Dedicated regulator for VDD (Cores + Platfrom). Adjustable from (0.7V to 1.2V) at ~120A. Regulators can be controlled by VID via software. Dedicated regulator for GVDD (DDR) : 1.35/1.5V at 40A. Linear regulators provide VTT/MVREF automatically track operating voltage. Dedicated regulators/filters for SERDES AVDD supplies. POVDD (now called PROG_SFP) (fuse security or repair) support. Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, etc. Re-use and scalability Interface strategy allows for scalable re-use and high coverage for IP validation. Design was highly reused on B4860 for a co-validation and support environment. 9

10 10

11 11

12 SERDES for T4240QDS was co-designed with B4860. Both share common strategy. Challenge of the SERDES design: Pin out optimization reduced number of layer to two for all four SERDES blocks. 40 db per lane noise requirement. PLL and SVDD/XVDD power required 50KHZ 500MHZ 10mv p-p maximum noise. Needed to use independent filters and dedicated power supplies to reduce fundamental and cross conducted noise. Stack up and material FR408 was highly optimized for best simulation results for the SERDES and DDR. 12

13 Gbps T lanes PCI Express Gen 1&2 2.5 / 5 Up to 4 x1 x2 x4 or Dual x8 PCI Express Gen 3 8 Dual x4 SRIO Gen 1&2 1.25** / 2.5 / / 5 Dual x1 x2 x4 Interlaken LA / 6.25 up to Eight x1 SATA Gen 1&2 1.5 / 3 Dual x1 Aurora 2.5 / / 5 x1 x2 x4 SGMII ` up to 16 x1 2.5X SGMII up to 12 x1 QSGMII 5 up to 4 x1 XAUI up to 4 x4 HiGig / HiGig+ / HiGig / 3.75 up to 4 x4 XFI up to 4 x1 ** Test Mode only 13

14 SD 1 SD 2 SD 3 SD 4 A-H A-H A-H A-H Front Side Ethernet Back Side Others T4240 has 32 lanes SERDES 4 SERDES Modules with 8 lanes in each Module (Lynx 26) Front Side SD 1 & 2 are Ethernet protocols Back Side SD 3 & 4 are other protocols (PEX/SRIO/SATA/Interlaken/Aurora) 14

15 T4240 FRONT SIDE SERDES Modules 1 / 2 Each SERDES Module (1 & 2) consists of 8 lanes shown New for T4 SERDES IP: HiGig, HiGig+, HiGig2, XFI, QSGMII Lane Reversal supported in XAUI and HiGig/+ (software controlled) Polarity inversion for any Ethernet protocol (software controlled) A B C D E F G H Module ; Protocol Freq mapping XAUIa XAUIa XAUIa XAUIa XAUIb XAUIb XAUIb XAUIb 1;1 XAUI HiGiga HiGiga HiGiga HiGiga HiGigb HiGigb HiGigb HiGigb 1;1a :2;1a HiGig / HiGig HiGiga HiGiga HiGiga HiGiga XAUIb XAUIb XAUIb XAUIb 1;1b : 2;1b HiGig / HiGig+ 3.75; XAUI XAUIa XAUIa XAUIa XAUIa SGMIIa SGMIIb SGMIIc SGMIId XAUI 3.125; SGMII 1.25 XAUIa XAUIa XAUIa XAUIa SGMIIa 2xSGMIIb SGMIIc SGMIId XAUI 3.125; SGMIIa,c-d 1.25; SGMIIb XAUIa XAUIa XAUIa XAUIa 2xSGMIIa SGMIIb SGMIIc SGMIId 1;2 XAUI 3.125; SGMIIa 3.125; SGMIIb-d 1.25 XAUIa XAUIa XAUIa XAUIa 2xSGMIIa 2xSGMIIb SGMIIc SGMIId XAUI 3.125; SGMIIa-b 3.125; SGMIIc-d 1.25 XAUIa XAUIa XAUIa XAUIa 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId XAUI 3.125; SGMII HiGiga HiGiga HiGiga HiGiga SGMIIa SGMIIb SGMIIc SGMIId HiGig 3.125; SGMII 1.25 HiGiga HiGiga HiGiga HiGiga SGMIIa 2xSGMIIb SGMIIc SGMIId HiGig 3.125; SGMIIa,c-d 1.25; SGMIIb HiGiga HiGiga HiGiga HiGiga 2xSGMIIa SGMIIb SGMIIc SGMIId 1;2a HiGig 3.125; SGMIIa 3.125; SGMIIb-d 1.25 HiGiga HiGiga HiGiga HiGiga 2xSGMIIa 2xSGMIIb SGMIIc SGMIId HiGig 3.125; SGMIIa-b 3.125; SGMIIc-d 1.25 HiGiga HiGiga HiGiga HiGiga 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId HiGig 3.125; SGMII HiGiga HiGiga HiGiga HiGiga SGMIIa SGMIIb SGMIIc SGMIId 1;2b HiGig+ 3.75; SGMII 1.25 SGMIIe SGMIIf SGMIIh SGMIIg SGMIIa SGMIIb SGMIIc SGMIId SGMIIa-h ;3 SGMIIe SGMIIf SGMIIh SGMIIg SGMIIa 2xSGMIIb SGMIIc SGMIId SGMIIa,c-h 1.25; SGMIIb ;4 SGMIIe SGMIIf SGMIIh SGMIIg 2xSGMIIa SGMIIb SGMIIc SGMIId SGMIIa 3.125; SGMIIb-h ;5 SGMIIe SGMIIf SGMIIh SGMIIg 2xSGMIIa 2xSGMIIb SGMIIc SGMIId 2;9 SGMIIa-b 3.125; SGMIIc-h 1.25 SGMIIe SGMIIf SGMIIh SGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId SGMIIa-d 3.125; SGMIIe-h 1.25 X X QSGMIIb X X X QSGMIIa X 1;6 : 2;10 QSGMII 5 SGMIIe SGMIIf SGMIIh SGMIIg X X QSGMIIa X SGMIIe-h 1.25; QSGMII 5 SGMIIe SGMIIf SGMIIh 2xSGMIIg X X QSGMIIa X 1;7 SGMIIe-f,h 1.25; SGMIIg 3.125; QSGMII 5 SGMIIe SGMIIf 2xSGMIIh SGMIIg X X QSGMIIa X 2;11 SGMIIe-g 1.25; SGMIIh 3.125; QSGMII 5 SGMIIe SGMIIf 2xSGMIIh 2xSGMIIg X X QSGMIIa X 1;8 SGMIIe-f 1.25; SGMIIg-h 3.125; QSGMII 5 2xSGMIIe 2xSGMIIf 2xSGMIIh 2xSGMIIg X X QSGMIIa X SGMIIe-h 3.125; QSGMII 5 XAUIa XAUIa XAUIa XAUIa X X QSGMIIa X 1;9 : 2;13 XAUI 3.125; QSGMII 5 HiGiga HiGiga HiGiga HiGiga X X QSGMIIa X 1;9 : 2;13 HiGig / HiGig+ 3.75; QSGMII 5 XFIc XFId XFIb XFIa SGMIIa SGMIIb SGMIIc SGMIId 2;3 XFI ; SGMII 1.25 XFIc XFId XFIb XFIa 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId 2;4 XFI ; SGMII XFIc XFId XFIb SGMIIg SGMIIa SGMIIb SGMIIc SGMIId 2;5 XFI ; SGMII 1.25 XFIc XFId XFIb 2xSGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId 2;6 : 2;7 XFI ; SGMII X XFId SGMIIh SGMIIg SGMIIa SGMIIb SGMIIc SGMIId XFI ; SGMII ;8 X XFId 2xSGMIIh 2xSGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId XFI ; SGMII X XFId XFIb X X X QSGMIIa X 2;12 XFI ; QSGMII 5 15

16 T4240 BACK SIDE -- SERDES Modules 3 / 4 A B C D E F G H Freq mapping SOC PRTCL PEXa PEXa PEXa PEXa PEXa PEXa PEXa PEXa T4240;3/4;1 PEX 5/2.5 PEXa PEXa PEXa PEXa PEXb PEXb PEXb PEXb T4240;3/4;2 PEXa 5/2.5; PEXb 8/5/2.5 PEXa PEXa PEXa PEXa SRIOa SRIOa SRIOa SRIOa T4240;3/4;3 PEX 5/2.5; SRIO 5/2.5/1.25 PEXa PEXa PEXa PEXa SRIOa SRIOa SRIOa SRIOa PEX 8/5/2.5; SRIO LA LA LA LA LA LA LA LA T4240;3;4 LA / 6.25 LA LA LA LA PEXb PEXb PEXb PEXb T4240;3;5 LA / 6.25; PEX 8/5/2.5 LA LA LA LA SRIOa SRIOa SRIOa SRIOa T4240;3;6 LA / 6.25; SRIO 5 / / 2.5 PEXa PEXa PEXa PEXa PEXb PEXb SATAa SATAb T4240;4;4 PEX 5/2.5; SATA 3/1.5 PEXa PEXa PEXa PEXa Aurora Aurora SATAa SATAb T4240;4;5 PEX 5/2.5; Aurora 5/2.5; SATA 3/1.5 PEXa PEXa PEXa PEXa Aurora Aurora SRIOa SRIOa T4240;4;6 PEX 5/2.5; Aurora 5/2.5; SRIO 5/2.5/1.25 PEXa PEXa PEXa PEXa Aurora Aurora SRIOa SRIOa PEX 8/5/2.5; Aurora 3.125; SRIO PEXa PEXa PEXa PEXa Aurora Aurora Aurora Aurora T4240;4;7 PEX 5/2.5; Aurora 5/2.5 Each SERDES Module (3 & 4) consists of 8 lanes shown above New for T4 SERDES IP: PEX Gen3 (8Gb), Interlaken (LA) Downgrading is feasible both for PEX and for SRIO (e.g. if 4x is supported, then downgrading for 2x and 1x is possible). Polarity inversion for any protocol (software controlled, except PEX is auto-negotiated) Improved Lane Reversal Support: Auto-negotiated Lane Reversal for PEX native x4 or x8 Software programmable Lane Reversal for PEX (x2/x4/x8), SRIO (x2/x4) Lane mapping control in software for Interlaken LA (x4/x8) No lane swapping support for Aurora! 16

17 Vitesse 3316 Crossbar Switch: Up to 11.5 Gbps. Arbitrary lane assignment provides flexible muxing solution. Supports 10Gb XFI (10GBASE_KR), PEX Gen3, and Out-of-Band signal forwarding for SATA. Signal conditioner ( programmable input equalization up to 26dB and output pre-emphasis up to 9dB. LOS (Loss of Signal) Detector on every port. I2C and SPI programming interfaces. Static Hardware pin strapping of select modes. ~ $ pins 15x15mm BGA package. 17

18 18

19 19

20 Three controllers pushed DDR on two sides of the pin out. Power delivery of memory and termination is spread out. Escape of vertical routes other than DDR are challenged. One side of pin out with dual controllers drives overall system layer count. Top speed of 2133 is very challenging for DDR3 technology. Voltage swing at 1.5V very wide. Timing budget pushes more burden on the T4240 controller, while less margin for system. 20

21 Provides a high speed and a low speed segments. High speed is lighter loaded and designed to run full speed synchronous or non synchronous devices. Low speed is fully separated and buffered by FPGA, like many customers will implement. Asynchronous devices and Promjet ROM emulation on this segment. Add-in card on high speed side. Supports various wide path and or fast synchronous devices such as synchronous NAND. Supports Test port validation card. 21

22 AMC AD[0:31],A[26:31] IFC connectivity ADDR DATA T4240 IFC AD[0:24] AD[27:31] A[26:31] AD[0:31],A[26:31] 1.8V Muxed Bus Banks= ADDR/16 DATA ADM Mux NOR FLASH 64MB/128MB CTRL AVD CLE WE0 WE1 WE2 WE3 CS0 CS1 CS2 CS3... OE Total Bus Loads: 4 CTRL CBT AD[0:7] AD[0:31],A[26:31] NAND FLASH 1/2-1GB 0n socket FBGA-63 DeMux FPGA GAsic Target (n regs) ADDR data ctrl Banks = 16 NOR FLASH 64MB/128MB ADDR data ctrl Banks = 1 PromJet IFC CARD/ Test port Connector RCW BCSR regs FPGA Minimal GAsic support (IO to ~2 registers) Dynamic boot reassignment of chip selects (All CS route to FPGA) NOR/PromJet demux inside. POR CFG bits 22

23 Fundamentally the same as P5020/P5040 functionally TSECs(RGMII) are on LVDD voltage rail, which is 2.5V or 1.8V(when acting as GPIOs only). I2C and UART are on DVDD voltage rail, which is 2.5 or 1.8V. OVDD voltage rail at only 1.8V encompasses a much larger set of interfaces besides miscellaneous types: IFC SPI SDHC Miscellaneous types like SYSCLK, DDRCLK, DMA, IRQ, JTAG, etc. 1.8V is becoming predominate general IO voltage Adds challenge to open drain bi-directional busses like I2C, when means special provisions for more complicated sub-systems. Many OVDD based signals needed translation to work with rest of system. 23

24 OVDD LVDD 1.8V domain 2.5V domain DUT IRQ[0:11] TRANS PHY_INT_B (2.5V) IRQ_OUT_B SYMMETRICOM_INT_B ( P_DETECT_B LP_P_DETECT_B TRANS LP_VDD QIXIS 3.3V 3.3V domain 24

25 QIXIS DUT DVDD-to-3V POST/ IRS OCM HOT3.3V DVDD UART 2 LEVEL SHFT RS232 Transceivers Port #2 Top port UART 1 Port #1 Bottom port 25

26 QIXIS Secondary QDS COP CASCADE_xyz DUT Aurora Pod utap/ COP/ etc. AURORA COP ecwtap Mux cfg_jtag_cascade COP_xyz JTAG_Route TAP TDI TCK S TDO TRST_B ecwtap/ Amphisbaena sw_jtag_route[0:2] 26

27 Very extensive on this implementation Clocks, crossbars, power supply, add-in cards, power measuring features and more controlled through I2C. Processor and remote host capability Dual system validation control link Primary I2C bus is 3.3V, but voltage translated and buffered to T4240 as either 2.5V or 1.8V. A big challenge. 27

28 QIXIS I2C Monitoring for Background Data C ollection (I-V-T) Komodo Controller (3.3V I2C) HDR LVL I2C1_CH7_CH7 LVL RST_I2C_B I2C1_CH7 PCA9547 I2C1_CH7_CH6... I2C1_CH7_CH1 I2C1_CH7_CH0 I2C1 LVL HDR PCA9547 I2C1_CH6... I2C1_CH1 I2C1_CH0 DUT I2C2 LVL HDR I2C3 LVL HDR I2C4 HDR DVDD: 1.8 or 2.5V 3.3V Headers to Remote Systems Note that I2C4 is NOT translated. 28

29 QIXIS (FPGA) Config Switches VCC_3.3_HOT EXT CLK IN SMA MHz OSC CFG CLK_IN_SEL 25 MHz XTAL HCSL 100 MHZ ICS871S1022 PLL (SSC) LEGEND I2C1 CH1 CFG CLKS OE SYSCLK_PIXIS 25 MHz XTAL CFG SPREAD 100 MHz 100 MHz Spread Spectrum Source = SMA injection/monitoring point = injection/monitoring point HCSL differential clock LVDS differential clock ICS8535I-31 25MHz Fanout Buffer HCSL HCSL LVPECL differential clock LVPECL / 6 LVCMOS single-ended clock (SSC) = Spread Spectrum Clocking Option 0x60 25MHz Ref CLK Optional MHz XTAL 0x6C Optional MHz XTAL 0x6D Optional MHz XTAL 0x6E 0x6F I2C I2C PLL (SSC) I2C PLL IDT840NT MHz Δf = 0.5M N1 N2 8/16 IDT8T49N222i-xxx N1 N2 Nfrac SYSCLK DDRCLK RTC N1 100 PLL N MHz Synthesizer Mode IDT8T49N222i-xxx I2C I2C PLL IDT8T49N222i-yyy PLL N N MHz High Bandwidth Mode IDT8T49N222i-yyy PLL N N MHz Synthesizer Mode N N MHz High Bandwidth Mode IDT840NT MHz LVDS 25/125 MHz 24MHz LVDS LVDS LVDS LVDS LVDS LVDS LVDS 1.8 V 3.3 V 1.8 V 1.8 V SD3_REFCLK1_PB SD3_REFCLK2_PB SD4_REFCLK1_PB SD4_REFCLK2_PB V-div 2.5V 3.3V 125MHz RGMII PHYs / 3 Test Port 1.8V CLK125M_DDR (125MHz) HCSL HCSL HCSL HCSL 1.8V CLK125M_DDR 1.8V CLK USB 2 IDT6V31021 SD1_REFCLK 1 SD1_REFCLK 2 SD2_REFCLK 1 SD2_REFCLK 2 SYSCLK_DUT (66.67 MHz typ) SD3_REFCLK 1 SD3_REFCLK 2 SD4_REFCLK 1 SD4_REFCLK 2 I2C DDRCLK_DUT (133.3 MHz typ) RTCCLK_DUT (3.125 MHz typ) SMA SMA 1588 Module SMA Slot 5 (x16) Slot 6 (x8) Slot 7 (x16) Aurora Slot 8 (x8) EC[1:2]_GTX_CLK MHz 125 MHz (modulated) 12.5 MHz typ 24 MHz T4240 IFC CLK1 IFC CLK0 IFC NDDDR CLK SYS CLK DDR CLK RT CLK CLK OUT SD1 REFCLK1 SD1 REFCLK2 Front Side SERDES (ENET) SD2 REFCLK1 SD2 REFCLK2 SD3 REFCLK1 SD3 REFCLK2 Back Side SERDES (PCIe, etc) SD4 REFCLK1 SD4 REFCLK2 EC[1:2] GTX CLK CLK IN 1588 CLK OUT USB CLK 29

30 Slew rate requirement for All rails except for PROG_SFP is 24V/ms max. PROG_SFP is 18V/ms max. VDD (Cores + Platfrom) has a DC and AC component at 1.0V mv DC mv AC (general transient deviation) mv AC transient for up to 1us. +- Load step static to full on estimated at 30A. (should be the goal for VDD regulator). Customer should plan for a di/dt on the load step of 12A/us. Speculative until characterization. SVDD/XVDD require independent filtering of noise to a max of 10mvp-p from 50KHZ 500MHZ. 30

31 A specific method of selecting the optimum voltage-level to guarantee performance and power targets. QorIQ device contains fuse block registers defining required voltage level. This EFUSE definition is accessed through the Fuse Status Register (DCFG_FUSESR). Customer system must use the VID to change the voltage regulators in the system in a reliable and safe methodology. QorIQ Chassis Architecture Specification, Generation 2 Revision 0.9 defines the general EFUSE definition. A set of 24 efuses ([0-23]) that determine the speed bin and voltage requirements for the device domains. The range and steps are much more flexible than actually needed by manufacturing; only the fuses necessary to provide the required voltages will be implemented. 31

32 FUSESR - Current Chassis Definition Bits Field Definition Reserved 2-3 BIN 2 b00 - Speed bin 1 (low) 2 b01 - Speed bin 2 (medium) 2 b10 - Speed bin 3 (high) 2 b11 - Speed bin 4 (premium) 4-8 PLAT_V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b V 5 b11001 reserved 5 b11111 reserved 9-13 DA_V Same as PLAT_V DB_V Same as PLAT_V DC_V Same as PLAT_V Reserved Reserved =1.1+n*12.5mV =1V+n*12.5mV (MSB=1) Default =1V-n*12.5mV (MSB=0) Reserved =0.8V-n*12.5mV (consider change of resolution to 6.25mV, and use the >1.0V options) Use ALT field

33 At power up time zero, regulator must come up at default voltage as defined per product. For T4240, that is 1.0V. VERY EARLY in the boot code and before many high speed or other power hungry features or interfaces are turned on, the DCFG_FUSESR register is read for the VID information. This value is translated into whatever commands to program up the new voltage value for the regulator. Once the regulator is sent the new values, a period of time needs to pass to allow the regulator to change values BEFORE power hungry features and higher clock rates are enabled/changed. 33

34 GPIOs. Typically a parallel port, simple VRM type regulator. Older AMD and VR11 Intel type regulators are typical, but many other companies. Default voltage (in this case 1.0V for T4240), must be configured when GPIOs are at tier one power sequence using pull-up and pull-down resistors. Out of reset and into the boot code, new VID is translated and thus GPIOs are programmed and driving regulator to new value. May have to use a voltage translator or a open-drain approach to adapt 1.8V GPIOs of T4240. Software is responsible for guarding any erroneous voltage values etc I2C bus or Power Management Bus (PMBus) More sophisticated and perhaps digital control loop device with telemetry. Program EEprom or use resistor strapping for default voltage. Out of reset, serial commands to regulator to set new voltage level determined by VID. IFC (Local Bus). Same as GPIOs or even I2C, but with the help of a FPGA or ASIC as the host interface via IFC. 34

35 Regulator voltage change delay and over current protection (OCP). Voltage delay is the time from the regulator receiving a new VID value and changing to the new voltage. Going too fast can cause a fault = shutdown. Many regulators, especially later model PMBus, SVID and VR12 types automatically change voltage gradually and in many case the time can be programmable. Older VR11 parallel type Intel regulators have to be stepped by software to avoid an OCP event. Voltage resolution Programmable regulators have a resolution from 50mv to 3.25mv steps. It costs more to support large VID ranges at 3% percent regulation. Our teams should be careful to not have too broad of range for the customer to have to validate of temperature, load and voltage. The lower the voltage, the more difficult it is to obtain 3% tolerance. Default Voltage may not be programmable. VR11 regulators have a default of 1.1V, which is ok for T4240, but perhaps not for other products. 35

36 36

37 Provide ample power for schmooing up to 1.2V and a 3 percent goal. 120A VR11 Intel analog VERY FAST response time 4 phase regulator. 6.25mv resolution. Since di/dt of T4240 is not known or characterized, PDN included several low ESR POSCAPS at 5mohm and 47uf 0805 ceramic XR5 capacitors. Current sensing was added on each phase and on a IMON total current representation. Placement and layout was very challenging. Since pin out implemented very high speed signals on all four corners, had to place VDD regulator 3.5 inches away, which limits response due to inductance. Use of three power layers to approach inner C5s of T4240. Two 2oz and one 1oz power plane splits with matching grounds. Since heat sinks take up space and cost, optimum output stage FETS and adequate placement spreading was used to handle thermal loss across system pcb. 37

38 Provide very low noise power and PLL filtering. 10mv p-p 50KHZ-500MHZ requirement. Use of Low Drop Out regulators exclusive to SVDD and XVDD. Filters were chosen to reduce droop and reduce cross IP block noise. Coordinated heavily with SERDES team for implementation. Added hooks to allow SERDES team to experiment with filtered version of VDD for SVDD and GVDD for XVDD. 38

39 T4240 requires programmable regulator at 12.5mv min steps. PWM Control VCC_12_BULK There are four sets of sense pins ganged and balanced with 10ohm resistors. T4240 Current includes 10% adder for schmooing and worst case silicon. I2C Power Monitor IMON is a current from regulator that represents a sum of all four phase current. ISL6334IRZ 8 BIT VID control VR11 style. ISL6620CR ISL6620CR PHASE1_CPLVDD I2C Power Monitor PHASE2_CPLVDD VDD_CORE_PL VDD V Cores & Platfrom 100A Cores & Platfrom Total Power capability is 120A 0.9V-1.1V. 3% percent. Based on 25A step with estimated slew of 15A/us. VCC_xxx = Source of Power VDD_xxx/AVDD_xxx = Power Rail for Device ISL6620CR ISL6620CR I2C Power Monitor PHASE3_CPLVDD I2C Power Monitor PHASE4_CPLVDD I2C Power Monitor 39

40 VCC_5 (ATX PS) VCC_12_BULK (ATX PS) PM Bus Integrated Module 1.8/2.5V 5% Integrated Module 1.8V 5% Integrated Module 2.5V 5% 40A Switcher V 5% To Devices VCC_DVDD To Devices VCC_1.8 To Devices VDD_OVDD VDD_DVDD VDD_BVDD VCCA_2.5 To power LVDD plane and phys etc.. There is another version called To Devices VCC2_2.5 for other stuff. VDD_LVDD GPIO mode tested on TESTER/HSSI thus no 1.8V needed. To DIMMs /MVREF/M_VTT VCC_GVDD VCC_GVDD_S VDD_GVDD ZL6105 (ATX PS) VCC_3.3 I2C Power Monitor VCC_1.8 VCC_1.8. OVDD 1.8V 0.6 General I/O / SPI / SDHC A DVDD 1.8 / 2.5V UART/ I2C 0.15 A BVDD 1.8V 0.5 A Integrated Flash Controller LVDD 1.8V GPIO / 2.5V ENET 0.35 A G1VDD G3VDD 1.35/1.5 DDR I/O 3.4 A V T4240 * Ferrite Bead is specifially Murata BLM18PG121SH1. Ferrite Bead VDD_CORE_PL f2 VDD_USB12_VDD_3P3 USB1/2_VDD_3P3 3.3V USB IO 40 MA f2 C = 2.2 uf C = 2.2 uf C = uf VCC_1.8 f2 VDD_USB12_VDD_1P0 USB1/2_ VDD_1P0 1.0V USB Core 40 MA VCC_xxx = Source of Power VDD_xxx/AVDD_xxx = Power Rail for Device f2 VDD_USB12_VDD_1P8 USB1/2_VDD_1P8 1.8V USB IO 40MA 40

41 VDD_GVDD T4240 VCC_1.8 LDOs primary due to uncertain noise requirements and separation. Red resistors are optional stuff in lieu of primary. f4 VDD_X1VDD X1VDD 1.35/1.5V 0.6A Linear Reg 1.35/1.5 V VCC_X12_VDD VCC_X12_VDD_S f4 VDD_X2VDD X2VDD 1.35/1.5V 0.6A Linear Reg 1.35/1.5 V VCC_X34_VDD VCC_X34_VDD_S f4 VDD_X3VDD X3VDD 1.35/1.5V 0.6A LT3070 f4 VDD_X4VDD X4VDD 1.35/1.5V 0.6A Ferrite Bead * All SERDES filter and power noise requirement = 10mv p-p from 50khz to 500MHZ.. Ferrite Bead C = 2.2 uf C = 2.2 uf C = uf f4 * Ferrite Bead is specifially Murata BLM18PG121SH1. VCC_xxx = Source of Power VDD_xxx = Power Rail for Device VDD_CORE_PL VCC_1.8 Linear Reg 1.0V VCC_S12_VDD VCC_S12_VDD_S f4 VDD_S1VDD S1VDD 1.0V 0.34A Linear Reg 1.0V VCC_S34_VDD VCC_S34_VDD_S f4 VDD_S2VDD S2VDD 1.0V 0.34A LT3070 f4 VDD_S3VDD S3VDD 1.0V 0.34A 41 f4 VDD_S4VDD S4VDD 1.0V 0.34A

42 VCC_X1234_VDD_S T4240 * All SERDES filter and power noise requirement = 10mv p-p from 50khz to 500MHZ.. R = 0.33 ohm C = 0.003uF C = 4.7 uf C = 47 uf f3 f3 f3 f3 f3 AVDD_SRDS1_PLL1 AVDD_SRDS1_PLL2 AVDD_SRDS2_PLL1 AVDD_SRDS2_PLL2 AVDD_SRDS3_PLL1 AVDD_SRDS1_PLL V Group1_ PLL1 40mA AVDD_SRDS1_PLL V Group1_ PLL2 40mA AVDD_SRDS2_PLL V Group2_ PLL1 40mA AVDD_SRDS2_PLL V Group2_ PLL2 40mA AVDD_SRDS3_PLL V Group3_ PLL1 40mA Grounds need isolation f3 AVDD_SRDS3_PLL2 AVDD_SRDS3_PLL V Group3_ PLL2 40mA f3 f3 f3 AVDD_SRDS4_PLL1 AVDD_SRDS4_PLL2 AVDD_SRDS4_PLL V Group4_ PLL1 40mA AVDD_SRDS4_PLL V Group4_ PLL2 40mA VCC_xxx = Source of Power VDD_xxx = Power Rail for Device 42

43 R = 5 ohm f1 VCC_1.8 VCC_xxx = Source of Power Linear Reg GND / 1.89 V C = 1 uf VDD_xxx = Power Rail for Device AVDD_CC1 f1 AVDD_CC2 f1 AVDD_CGA3 f1 AVDD_CGB1 C = 10 uf f1 AVDD_CGB2 f1 AVDD_DDR f1 AVDD_PL f1 VDD_CORE_PL FA_VDD VDD_LP VCC_1.8 VDD_IRS_VDD VCC_POVDD VDD_POVDD Strict timing and rise time requirements.. T4240 AVDD_CGA1 1.8V GroupA_ PLL1 AVDD_CGA2 1.8V GroupA_PLL2 IRS_VDD 1.8V 3mA 3mA AVDD_CGA3 1.8V GroupA_PLL3 3mA AVDD_CGB1 1.8V GroupB_PLL1 3mA AVDD_CGB2 1.8V GroupB_PLL2 AVDD_DDR 1.8V DDR_PLL AVDD_PL 1.8V Platform_PLL 3mA 3mA 3mA FA_VDD 1.0V Process Detect 0.05A VDD_LP 1.0V Low Power Security Monitor IR Sense analog 0.05A GND (read) POVDD 150mA 1.89V (write) Fuse Prgm 43

44 VCC_5 (ATX PS) Integrated Module 1.2V 5% Integrated Module 2.5V 5% VCC_EPHY_1.2 VCCB_2.5 VCC_HOT_5 (ATX PS) Integrated Module 3.3V 5% Integrated Module 1.5V 5% VCC_HOT_3.3 VCC_HOT_1.5 VCC_xxx = Source of Power VDD_xxx = Power Rail for Device 44

45 T4240/4160 rev 1 BSC9131 rev 1 and BSC9131RDB BSC9132 rev 1 and BSC9132QDS G4860 rev 1 TWR-P1025 P1020RDB-PD P1023RDB-PA P1010RDB 1 GHz MPC85xx processor and board support removed P1020U, P1020MBG, P1020RDB-PC, P1024RDB, P1025RDB, P1023RDS support removed 45

46 U-Boot Boot Loader U-Boot Secure Boot for T4240 and B4860 Cryptographic blob generation commands in ESBC Linux Kernel and Virtualization Linux kernel Linux Preempt Real-Time (RT) - v rt9 Preempt RT support for B4860QDS and TWR-P1025 Linux Container (LXC) Libvirt Kernel-based Virtual Machine (KVM) features: KVM: e T4240 and B4860 KVM: QEMU 1.4 KVM: USB pass through Yocto and Toolchain Yocto/Poky 1.4 "Dylan" gcc-4.7.2, eglibc-2.15, binutils , gdb Mixed mode builds - ability to build both 32-bit and 64-bit applications with same toolchain 46

47 DPAA Offloading driver added [P4080, B4860/4420] Ethernet DPAA: ethtool update relating to 3.8 kernel upgrade Ethernet DPAA: PAUSE frame run-time control using ethtool Ethernet DPAA: netpoll support Ethernet DPAA: Linux standard API for hardware timestamping (IEEE1588) Ethernet DPAA: Removed the Qdisc support bypass from the standard SDK configuration FMan: Virtual Storage Profile using chosen node FMan: Pre-silicon support for T4240 and B4860 rev 2 FMan: Microcode version update IEEE1588 driver: P5040 and 64-bit PCIe: hot remove/rescan PCIe: End Point (EP) support [P4080, T4240] QMAN: Pre-silicon support for T4240 and B4860 rev 2 SEC: QMan Interface for DPAA processors Thermal Monitor support [using on-board sensors for T4240QDS, B4860QDS, P1022DS] XFI support on B4860QDS 47

48