8M ( 8/ 16) FLASH MEMORY & 2M ( 8) STATIC RAM

Transcription

1 FUJITSU SEMICONDUCTOR DATA SHEET DS5-5-E MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 8M ( 8/ 6) FLASH MEMORY & 2M ( 8) STATIC RAM FEATURES Power supply voltage of 2.7 to 3.6 V High performance ns maximum access time Operating Temperature 2 to +85 C FLASH MEMORY Simultaneous operations Read-while Erase or Read-while-Program Minimum, write/erase cycles Sector erase architecture Two 6 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. Boot Code Sector Architecture MB84VD22: Top sector MB84VD23: Bottom sector Embedded Erase TM Algorithms Automatically pre-programs and erases the chip or any sector Embedded Program TM Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. Low VCC write inhibit 2.5 V Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device Please refer to "MBM29DL8TA/BA" data sheet in detailed function SRAM Power dissipation Operating : 35 ma max. Standby : 5 µa max. Power down features using CEs and CE2s Data retention supply voltage: 2. V to 3.6 V Embedded Erase TM and Embedded Program TM are trademarks of Advanced Micro Devices, Inc.

2 BLOCK DIAGRAM VCCf VSS A to A8 A to A8 RY/BY A- RESET CEf BYTE 8 M bit Flash Memory DQ8 to DQ5 DQ to DQ7 VCCs VSS A to A6 SA OE CEs CE2s 2 M bit Static RAM EXAMPLE OF CONNECTION WITH CHIPSET VCC A[:9] A[:9] A A[:8] SA VCCf BYTE RESET ROM_CS/ CEf RY/BY RAM_CS/ CEs Battery Backup Control VCCs CE2s BATTERY BACKUP HWR/ LWR/ RD/ D[:5] CHIPSET D[:5] OE DQ[:5] MB84VD22/3 2

3 PIN ASSIGNMENTS (Top View) A B C D E F G H 6 CEs VSS DQ A A2 A4 CE2s A9 5 A DQ5 DQ2 A A3 A7 RY/BY A4 4 OE DQ7 DQ4 DQ A6 A8 RESET A5 3 A A8 A5 DQ8 DQ3 DQ2 A2 BYTE 2 A3 A7 SA* CEf DQ VCCf DQ6 DQ5/A- VCCs A6 VSS DQ9 DQ DQ3 DQ4 *: A7 for SRAM Table Pin Configuration Pin Function Input/ Output A to A6 Address Inputs (Common) I A-, A7 to A8 Address Input (Flash) I SA Address Input (SRAM) I DQ to DQ7 Data Inputs/Outputs (Common) I/O DQ8 to DQ5 Data Inputs/Outputs (Flash) I/O CEf Chip Enable (Flash) I CEs Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I Write Enable (Common) I RY/BY Ready/Busy Outputs (Flash) O BYTE Selects 8-bit or 6-bit mode (Flash) I RESET Hardware Reset Pin/Sector Protection Unlock (Flash) I N.C. No Internal Connection VSS Device Ground (Common) Power VCCf Device Power Supply (Flash) Power VCCs Device Power Supply (SRAM) Power 3

4 PRODUCT LINE UP Flash Memory SRAM +.6 V Ordering Part No. VCC = 3. V Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) 4 5 BUS OPERATIONS.3 V Table 2 User Bus Operations (BYTE=VIL) Operation (), (3) CEf CEs CE2s OE DQ to DQ7 DQ8 to DQ5 RESET H X Full Standby H X X HIGH-Z HIGH-Z H X L Output Disable X X X H H HIGH-Z HIGH-Z H H X Read from Flash (2) L L H DOUT HIGH-Z H X L H X Write to Flash L H L DIN HIGH-Z H X L Read from SRAM H L H L H DOUT HIGH-Z H Write to SRAM H L H X L DIN HIGH-Z H H X Flash Hardware Reset X X X HIGH-Z HIGH-Z L X L Table 3 User Bus Operations (BYTE=VIH) Operation (), (3) CEf CEs CE2s OE DQ to DQ7 DQ8 to DQ5 RESET H X Full Standby H X X HIGH-Z HIGH-Z H X L Output Disable X X X H H HIGH-Z HIGH-Z H H X Read from Flash (2) L L H DOUT DOUT H X L H X Write to Flash L H L DIN DIN H X L Read from SRAM H L H L H DOUT HIGH-Z H Write to SRAM H L H X L DIN HIGH-Z H H X Flash Hardware Reset X X X HIGH-Z HIGH-Z L X L Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Notes:. Other operations except for indicated this column are inhibited. 2. can be VIL if OE is VIL, OE at VIH initiates the write operations. 4. Do not apply CEf = VIL, CEs = VIL and CE2s = VIH at a time. 4

5 FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY Two 6 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes. Individual-sector, multiple-sector, or bulk-erase capability. ( 8) ( 6) ( 8) ( 6) Bank Bank 2 6K byte/8k word 32K byte/6k word 8K byte/4k word 8K byte/4k word 8K byte/4k word 8K byte/4k word 32K byte/6k word 6K byte/8k word FFFFFH FCH F4H F2H FH EEH ECH E4H EH DH CH BH AH 9H 8H 7H 6H 5H 4H 3H 2H H H 7FFFFH 7EH 7AH 79H 78H 77H 76H 72H 7H 68H 6H 58H 5H 48H 4H 38H 3H 28H 2H 8H H 8H H Bank 2 Bank 6K byte/8k word 32K byte/6k word 8K byte/4k word 8K byte/4k word 8K byte/4k word 8K byte/4k word 32K byte/6k word 6K byte/8k word FFFFFH FH EH DH CH BH AH 9H 8H 7H 6H 5H 4H 3H 2H CH 4H 2H H EH CH 4H H 7FFFFH 78H 7H 68H 6H 58H 5H 48H 4H 38H 3H 28H 2H 8H H CH AH 9H 8H 7H 6H 2H H MBM29DL8TA Sector Architecture MB84VD22 Sector Architecture MBM29DL8BA Sector Architecture MB84VD23 Sector Architecture 5

6 To Top / Lineup / Index Table 4 Sector Address Tables (MB84DV22) Sector Address Bank Sector Bank Address Sector Size (Kbytes/ Kwords) ( 8) Address Range ( 6) Address Range A8 A7 A6 A5 A4 A3 A2 SA X X X 64/32 H to FFFFH H to 7FFFH SA X X X 64/32 H to FFFFH 8H to FFFFH SA2 X X X 64/32 2H to 2FFFFH H to 7FFFH SA3 X X X 64/32 3H to 3FFFFH 8H to FFFFH SA4 X X X 64/32 4H to 4FFFFH 2H to 27FFFH SA5 X X X 64/32 5H to 5FFFFH 28H to 2FFFFH Bank 2 SA6 X X X 64/32 6H to 6FFFFH 3H to 37FFFH SA7 X X X 64/32 7H to 7FFFFH 38H to 3FFFFH SA8 X X X 64/32 8H to 8FFFFH 4H to 47FFFH SA9 X X X 64/32 9H to 9FFFFH 48H to 4FFFFH SA X X X 64/32 AH to AFFFFH 5H to 57FFFH SA X X X 64/32 BH to BFFFFH 58H to 5FFFFH SA2 X X X 64/32 CH to CFFFFH 6H to 67FFFH SA3 X X X 64/32 DH to DFFFFH 68H to 6FFFFH SA4 X 6/8 EH to E3FFFH 7H to 7FFFH SA5 X X 32/6 E4H to E7FFFH, E8H to EBFFFH 72H to 73FFFH, 74H to 75FFFH SA6 8/4 ECH to EDFFFH 76H to 76FFFH Bank SA7 8/4 EEH to EFFFFH 77H to 77FFFH SA8 8/4 FH to FFFFH 78H to 78FFFH SA9 8/4 F2H to F3FFFH 79H to 79FFFH SA2 X X 32/6 F4H to F7FFFH, F8H to FBFFFH 7AH to 7BFFFH, 7CH to 7DFFFH SA2 X 6/8 FCH to FFFFFH 7EH to 7FFFFH Note:The address range is A8: A- if in byte mode (BYTE = VIL). The address range is A8: A if in word mode (BYTE = VIH). 6

7 Table 5 Sector Address Tables (MB84DV23) Sector Address Bank Sector Bank Address Sector Size (Kbytes/ Kwords) ( 8) Address Range ( 6) Address Range A8 A7 A6 A5 A4 A3 A2 SA2 X X X 64/32 FH to FFFFFH 78H to 7FFFFH SA2 X X X 64/32 EH to EFFFFH 7H to 77FFFH SA9 X X X 64/32 DH to DFFFFH 68H to 6FFFFH SA8 X X X 64/32 CH to CFFFFH 6H to 67FFFH SA7 X X X 64/32 BH to BFFFFH 58H to 5FFFFH SA6 X X X 64/32 AH to AFFFFH 5H to 57FFFH Bank 2 SA5 X X X 64/32 9H to 9FFFFH 48H to 4FFFFH SA4 X X X 64/32 8H to 8FFFFH 4H to 47FFFH SA3 X X X 64/32 7H to 7FFFFH 38H to 3FFFFH SA2 X X X 64/32 6H to 6FFFFH 3H to 37FFFH SA X X X 64/32 5H to 5FFFFH 28H to 2FFFFH SA X X X 64/32 4H to 4FFFFH 2H to 27FFFH SA9 X X X 64/32 3H to 3FFFFH 8H to FFFFH SA8 X X X 64/32 2H to 2FFFFH H to 7FFFH SA7 X 6/8 CH to FFFFH EH to FFFFH SA6 X X 32/6 4H to 7FFFH, 8H to BFFFH AH to BFFFH, CH to DFFFH SA5 8/4 2H to 3FFFH 9H to 9FFFH Bank SA4 8/4 H to FFFH 8H to 8FFFH SA3 8/4 EH to FFFFH 7H to 7FFFH SA2 8/4 CH to DFFFH 6H to 6FFFH SA X X 32/6 8H to BFFFH, 4H to 7FFFH 4H to 5FFFH, 2H to 3FFFH SA X 6/8 H to 3FFFH H to FFFH Note: The address range is A8: A- if in byte mode (BYTE = VIL). The address range is A8: A if in word mode (BYTE = VIH). 7

8 Table 6. Flash Memory Autoselect Codes Type A6 A A A- * Code (HEX) Manufacturer s Code VIL VIL VIL VIL 4H Device Code MB84VD22 MB84VD23 Byte VIL VIL VIH VIL 4AH Word X 224AH Byte VIL VIL VIH VIL CBH Word X 22CBH *: A- is for Byte mode. Table 6. 2 Expanded Autoselect Code Table Type Code DQ5 DQ4 DQ3 DQ2 DQ DQ DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ DQ Manufacturer s Code 4H A-/ Device Code MB84VD22 (B) (W) MB84VD23 (B) (W) 4AH 224AH CBH 22CBH A- A- HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z (B): Byte mode (W): Word mode 8

9 Command Sequence Read/Reset Read/Reset Autoselect Bus Write Cycles Req d Table 7 First Bus Write Cycle Flash Memory Command Definitions Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Word Byte XXXH FH Word 555H 2AAH 555H 3 AAH 55H Byte AAAH 555H AAAH FH RA RD (BA) 55H 555H 9H Word 555H 2AAH 3 AAH Byte AAAH 555H (BA) AAAH Program Word 555H 2AAH 555H 4 AAH 55H Byte AAAH 555H AAAH AH PA PD Chip Erase Word 555H 2AAH 555H 555H 2AAH 555H 6 AAH 55H 8H AAH 55H Byte AAAH 555H AAAH AAAH 555H AAAH H Sector Erase Word 555H 2AAH 555H 555H 2AAH 6 AAH 55H 8H AAH Byte AAAH 555H AAAH AAAH 555H 55H SA 3H Erase Suspend BA BH Erase Resume BA 3H Set to Word 555H 2AAH 555H Fast Mode 3 AAH 55H Byte AAAH 555H AAAH 2H Fast Word XXXH Program * 2 Byte XXXH AH PA PD Reset from Word BA Fast Mode * 2 9H XXXH Byte BA XXXH FH Word Byte 4 XXXH 6H SPA 6H SPA 4H SPA SD Extended Sector Protect Notes:. Address bits A to A8 = X = H or L for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA). 2. Bus operations are defined in Tables 2 and RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A8, A7, A6, A5, A4, A3, and A2 will uniquely select any sector. BA = Bank Address (A6 to A8) 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. 5. SPA =Sector address to be protected. Set sector address (SA) and (A6, A, A) = (,, ). SD = Sector protection verify data. Output H at protected sector addresses and output H at unprotected sector addresses. * : This command is valid while Fast Mode. 9

10 ABSOLUTE MAXIMUM RATINGS Storage Temperature C to +25 C Ambient Temperature with Power Applied C to +85 C Voltage with Respect to Ground All pins (Note)....3 V to VCCf +.5 V.3 V to VCCs +.5 V VCCf/VCCs Supply (Note)....3 V to +4.6 V Note: Minimum DC voltage on input or I/O pins are.5 V. During voltage transitions, inputs may negativeovershoot VSS to 2. V for periods of up to 2 ns. Maximum DC voltage on output and I/O pins are VCCf +.5 V or VCCs +.5 V. During voltage transitions, outputs may positive overshoot to VCC +2. V for periods of up to 2 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING RANGES Commercial Devices Ambient Temperature (TA)... 2 C to +85 C VCCf/VCCs Supply Voltages V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.

11 DC CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min. Typ. Max. Unit ILI Input Leakage Current. +. µa ILO Output Leakage Current. +. µa ICCf ICC2f ICC3f*** ICC4f*** ICC5f ICCs ICC2s ISBf ISB2f ISBs ISB2s** Flash VCC Active Current (Read) Flash VCC Active Current (Program/Erase) Flash VCC Active Current (Read-While-Program) Flash VCC Active Current (Read-While-Erase) Flash VCC Active Current (Erase-Suspend- Program) SRAM VCC Active Current SRAM VCC Active Current Flash VCC Standby Current Flash VCC Standby Current (RESET) SRAM VCC Standby Current SRAM VCC Standby Current VCCf = VCC Max., CEf = VIL OE = VIH Byte 8 tcycle = MHz Word 2 Byte 8 tcycle = 5 MHz Word VCCf = VCC Max., CEf = VIL, OE = VIH 35 ma CE = VIL, OE = VIH CE = VIL, OE = VIH Byte 45 Word 45 Byte 45 Word 45 CE = VIL, OE = VIH 35 ma VCCs = VCC Max., CEs = VIL, CE2s = VIH CEs =.2 V, CE2s = VCCs.2 V, = VCCs.2 V VCCf = VCC Max., CEf = VCCf ±.3 V RESET = VCCf ±.3 V * : VCC indicate lower of VCCf or VCCs ** :During standby mode with CEs = VCCS.2 V, CE2s should be CE2s <.2V or CE2s > VCCS.2V *** :Embeded Algorithm (program or erase) is in progress. (@5 MHz) ma ma ma tcycle = MHz 4 ma tcycle = MHz 2 ma tcycle = MHz 35 ma tcycle = MHz 6 ma 5 µa VCCf = VCC Max., RESET = VSS ±.3 V 5 µa CEs = VIH or CE2s = VIL 2 ma CEs = VCC.2 V or CE2s =.2 V VCCs = 3. V ±% VCCs = 3.3 V ±.3 V TA = 25 C 2.5 µa TA = 2 to +85 C 55 µa TA = 25 C.5 3 µa TA = 2 to +85 C 6 µa TA = 25 C 2 µa VCCs TA = 2 to = C 5 µa V TA = 2 to +85 C 5 µa VIL Input Low Level.3.6 V VIH Input High Level 2.2 VCC+.3* V VOL Output Low Voltage IOL = 2. ma, Level VCCf = VCCs = VCC Min..4 V VOH Output High Voltage IOH = 5 µa, Level VCCf = VCCs = VCC Min. VCC.5 V VLKO Flash Low VCC Lock-Out Voltage V

12 AC CHARACTERISTICS CE Timing JEDEC Parameter Symbols Standard Description Test Setup - Unit tccr CE Recover Time Min. ns Timing Diagram for alternating SRAM to Flash CEf tccr tccr CEs CE2s tccr tccr Read Only Operations Characteristics (Flash) Parameter - Symbols Description Test (Note) Setup JEDEC Standard Min. Max. Unit tavav trc Read Cycle Time ns tavqv tacc Address to Output Delay CEf = VIL OE = VIL ns telqv tcef Chip Enable to Output Delay OE = VIL ns tglqv toe Output Enable to Output Delay 4 ns tehqz tdf Chip Enable to Output High-Z 3 ns tghqz tdf Output Enable to Output High-Z 3 ns taxqx toh Output Hold Time From Addresses, CEf or OE, Whichever Occurs First ns tready RESET Pin Low to Read Mode 2 µs telfl telfh CE or BYTE Switching Low or High 5 ns Note: Test Conditions Output Load: TTL gate and 3 pf Input rise and fall times: 5 ns Input pulse levels:. V to 3. V Timing measurement reference level Input:.5 V Output:.5 V 2

13 Read Cycle (Flash) trc ADDRESSES Addresses Stable tacc CEf toe tdf OE toeh tce DQ HIGH-Z Output Valid HIGH-Z trc ADDRESSES Addresses Stable tacc trh RESET toh DQ HIGH-Z Output Valid 3

14 Erase/Program Operations (Flash) Parameter Symbols - Description JEDEC Standard Min. Typ. Max. Unit tavav twc Write Cycle Time ns tavwl tas Address Setup Time ( to Addr.) ns tavel tas Address Setup Time (CEf to Addr.) ns taso Address Setup Time to OE Low During Toggle Bit Polling 5 ns twlax tah Address Hold Time ( to Addr.) 5 ns telax tah Address Hold Time (CEf to Addr.) 5 ns taht Address Hold Time from CE or OE High During Toggle Bit Polling ns tdvwh tds Data Setup Time 5 ns twhdx tdh Data Hold Time ns toeh Output Enable Hold Time Read ns Toggle and Data Polling ns tceph CE High During Toggle Bit Polling 2 ns toeph OE High During Toggle Bit Polling 2 ns tghel tghel Read Recover Time Before Write (OE to CEf) ns tghwl tghwl Read Recover Time Before Write (OE to ) ns twlel tws Setup Time (CEf to ) ns telwl tcs CEf Setup Time ( to CEf) ns tehwh twh Hold Time (CEf to ) ns twheh tch CEf Hold Time ( to CEf) ns twlwh twp Write Pulse Width 5 ns teleh tcp CEf Pulse Width 5 ns twhwl twph Write Pulse Width High 3 ns tehel tcph CEf Pulse Width High 3 ns twhwh twhwh Byte Programming Operation 8 µs twhwh2 twhwh2 Sector Erase Operation (Note ) sec 5 sec tvcs VCCf Setup Time 5 µs tvlht Voltage Transition Time (Note 2) 4 µs tvidr Rise Time to VID (Note 2) 5 ns trb Recover Time from RY/BY ns trp RESET Pulse Width 5 ns trh RESET Hold Time Before Read 2 ns teoe Delay Time from Embedded Output Enable ns tbusy Program/Erase Valid to RY/BY Delay 9 ns tflqz BYTE Switching Low to Output High-Z 3 ns tfhqv BYTE Switching High to Output Active 3 ns Note :. This does not include the preprogramming time. 2. This timing is for Sector Protection Operation. 4

15 Write Cycle ( control) (Flash) 3rd Bus Cycle Data Polling ADDRESSES 555H PA PA twc tas tah trc CEf tcs tch tco OE tghwl twp twph twhwh tfoe tds toh tdh DQ AH PD DQ7 DOUT DOUT Notes:. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence 6. These waveforms are for the x6 mode. The addresses differ from x8 mode. 5

16 Write Cycle (CEf control) (Flash) 3rd Bus Cycle Data Polling ADDRESSES 555H PA PA twc tas tah tws twh OE tghel tcp tcph twhwh CEf tds tdh DQ AH PD DQ7 DOUT Notes:. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence 6. These waveforms are for the x6 mode. The addresses differ from x8 mode. 6

17 AC Waveforms Chip/Sector Erase Operations (Flash) ADDRESSES 555H 2AAH 555H 555H 2AAH SA * twc tas tah CEf tcs tch OE tghwl twp twph tds tdh 3H for Sector Erase DQ AAH 55H 8H AAH 55H H/ 3H tvcs VCC Notes:. SA is the sector address for Sector Erase. Addresses = 555H forchip Erase. 2. These waveforms are for the x6 mode. The addresses differ from x8 mode. 7

18 AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) CE t CH t OE t DF OE t OEH t CE DQ7 Data DQ7 * DQ7 = Valid Data High-Z t WHWH or 2 DQ to DQ6 Data DQ to DQ6 = Output Flag DQ to DQ6 Valid Data High-Z t BUSY t EOE RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation). AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) Address taht taso taht tas CE tceph toeph toeh toeh OE tdh toe tce * DQ 6/DQ2 Data Toggle Data Toggle Data Toggle Data Stop Toggling Output Valid tbusy RY/BY * : DQ6 stops toggling (The device has completed the Embedded operation). 8

19 RY/BY Timing Diagram during Write/Erase Operations (Flash) CEf The rising edge of the last signal Entire programming or erase operations RY/BY tbusy RESET, RY/BY Timing Diagram (Flash) RESET trp trb RY/BY tready Timing Diagram for Word Mode Configuration (Flash) CE BYTE DQ to DQ4 telfh Data Output (DQ to DQ7) tfhqv Data Output (DQ to DQ4) DQ5/A- A- DQ5 9

20 Timing Diagram for Byte Mode Configuration (Flash) CE BYTE DQ to DQ4 telfl Data Output (DQ to DQ4) Data Output (DQ to DQ7) DQ5/A- DQ5 A- tflqz BYTE Timing Diagram for Write Operations (Flash) The falling edge of the last signal CE or BYTE Input Valid tset (tas) thold (tah) Temporary Sector Unprotection (Flash) VCC tvidr tvcs tvlht VID 3 V 3 V RESET CE RY/BY tvlht Program or Erase Command Sequence tvlht Unprotection period 2

21 Back-to-back Read/Write Timing Diagram Read Command Read Command Read Read trc twc trc twc trc trc Address BA BA2 BA BA2 (555H) (PA) BA BA2 (PA) tas tah tacc tce taht tas CE toe tceph OE tghwl twp toeh tdf tds tdh tdf DQ Valid Output Valid Intput (AH) Valid Output Valid Intput (PD) Valid Output Status 2

22 Extended Sector Protection (Flash) VCC tvcs RESET tvlht tvidr Add SPAX SPAX SPAY A A A6 CE OE TIME-OUT Data 6H 6H 4H H 6H toe SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 5 µs (min) 22

23 Read Cycle (SRAM) Parameter Symbol Parameter Description Min. Max. Unit trc Read Cycle Time ns taa Address Access Time ns tco Chip Enable (CEs) Access Time ns tco2 Chip Enable (CE2s) Access Time ns toe Output Enable Access Time 5 ns tcoe Chip Enable (CEs Low and CE2s High) to Output Active 5 ns toee Output Enable Low to Output Active ns tod Chip Enable (CEs High or CE2s Low) to Output High-Z 4 ns todo Output Enable High to Output High-Z 4 ns toh Output Data Hold Time ns Read Cycle (Note ) (SRAM) trc ADDRESSES taa toh tco CEs tcoe tco2 tod CE2s tod toe OE toee todo DQ tcoe VALID DATA OUT Note:. remains HIGH for the read cycle. 23

24 Write Cycle (SRAM) Parameter Symbol Parameter Description Min. Max. Unit twc Write Cycle Time ns twp Write Pulse Width 6 ns tcw Chip Enable to End of Write 8 ns tas Address Setup Time ns twr Write Recovery Time ns todw Low to Output High-Z 4 ns toew High to Output Active ns tds Data Setup Time 4 ns tdh Data Hold Time ns Write Cycle (Note 4) ( control) (SRAM) twc ADDRESSES tas twp twr tcw CEs CE2s tcw todw toew DOUT Note 2 Note 3 tds tdh DIN Note 5 VALID DATA IN Note 5 Notes: 2. If CEs goes LOW (or CE2s goes HIGH) coincident with or after goes LOW, the output will remain at high impedance. 3. If CEs goes HIGH (or CE2s goes LOW) coincident with or before goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 24

25 Write Cycle (Note 4) (CEs control) (SRAM) twc ADDRESSES tas twp twr tcw CEs CE2s tcw tcoe todw DOUT tds tdh DIN Note 5 VALID DATA IN Note 5 Notes: 2. If CEs goes LOW (or CE2s goes HIGH) coincident with or after goes LOW, the output will remain at high impedance. 3. If CEs goes HIGH (or CE2s goes LOW) coincident with or before goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 25

26 Write Cycle (Note 4) (CE2s Control) (SRAM) twc ADDRESSES tas twp twr tcw CEs CE2s tcw tcoe todw DOUT tds tdh DIN Note 5 VALID DATA IN Note 5 Notes: 2. If CEs goes LOW (or CE2s goes HIGH) coincident with or after goes LOW, the output will remain at high impedance. 3. If CEs goes HIGH (or CE2s goes LOW) coincident with or before goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 26

27 ERASE AND PROGRAMMING PERFORMANCE (Flash) Parameter Limits Min. Typ. Max. Unit Comment Sector Erase Time sec Byte Programming Time 8 3 µs Word Programming Time 6 36 µs Chip Programming Time 8.4 T.B.D sec Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Erase/Program Cycle, cycles DATA RETENTION CHARACTERISTICS (SRAM) Parameter Symbol Parameter Description Min. Typ. Max. Unit VDH Data Retention Supply Voltage V IDDS2 Standby Current VDH = 3. V 5* µa VDH = 3.6 V 6 µa tcdr Chip Deselect to Data Retention Mode Time ns tr Recovery Time 5 ms * : 5 µa (Max.) at TA = 2 C to +4 C CEs Controlled Data Retention Mode (Note ) VCCs DATA RETENTION MODE 2.7 V VIH See Note 2 See Note 2 CEs tcdr VCCS.2 V tr GND 27

28 CE2s Controlled Data Retention Mode (Note 3) VCCs DATA RETENTION MODE 2.7 V VIH CE2s tcdr tr VIL.2 V GND Notes:. In CEs controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-.2V or Vss to.2v during data retention mode. Other input and input/output pins can be used between -.3V to Vccs+.3V. 2. When CEs is operating at the VIH min. level (2.2 V), the standby current is given by ISBs during the transition of VCCs from 3.6 to 2.2 V. 3. In CE2s controlled data retention mode, input and input/output pins can be used between between -.3V to Vccs+.3V. PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN = T.B.D T.B.D pf COUT Output Capacitance VOUT = T.B.D T.B.D pf CIN2 Control Pin Capacitance VIN = T.B.D T.B.D pf Note: Test conditions TA = 25 C, f =. MHz HANDLING OF PACKAGE Please handle this package carefully since the sides of packages are right angle. CAUTION.)The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2.)For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector useing "Extended sector protect" command. 28

29 PACKAGE 48-pin plastic FBGA (BGA-48P-M6) PACKAGE DIMENSIONS 48-pin plastic BGA (BGA-48P-M6) Note: The actual shape of coners may differ from the dimension..±.5(.433±.6).4±.2 (.55±.8).3±. (.2±.4) 7.±.5(.276±.6).±.5 (.394±.6) Ø.4±. (Ø.6±.4) 5.±.5 (.97±.6).5(.6) st PIN INDEX.±.5 (.39±.6) INDEX C 998 FUJITSU LIMITED MCM-M-2-3 Dimension in mm (inches). 29

30 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4--, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa , Japan Tel: (44) Fax: (44) North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA , USA Tel: (48) Fax: (48) Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (8) Fax: (48) Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6- D-6333 Dreieich-Buchschlag Germany Tel: (63) 69- Fax: (63) Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #5-8, 5 Lorong Chuan New Tech Park Singapore Tel: (65) Fax: (65) All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F985 FUJITSU LIMITED Printed in Japan 3