16Mb(1M x 16 bit) Low Power SRAM

Transcription

1 16Mb(1M x 16 bit) Low Power SRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROP- ERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1

2 Document Title 1M x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft November 14, 2003 Preliminary 1.0 Finalize March 31, 2005 Final 2.0 Revised - Added Lead Free Products May 11, 2005 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 2

3 1M x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES Process Technology: Full CMOS Organization: 1M x16 Power Supply Voltage: 2.7~3.3V Low Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 48-FBGA x7.00 GENERAL DESCRIPTION The K6F1616U6C families are fabricated by SAMSUNG s advanced full CMOS process technology. The families support industrial operating temperature ranges. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed 1. The parameter is measured with 30pF test load. 2. Typical value is measured at VCC=3.0V, TA=25 C and not 100% tested. Power Dissipation Standby (ISB1, Typ.) Operating (ICC1, Max) PKG Type K6F1616U6C-F Industrial(-40~85 C) 2.7~3.3V 55 1) /70ns 5µA 2) 5mA 48-FBGA x7.00 PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A LB OE A0 A1 A2 Clk gen. Precharge circuit. B I/O9 UB A3 A4 I/O1 Vcc Vss C D I/O10 I/O11 A5 A6 I/O2 I/O3 Vss I/O12 A17 A7 I/O4 Vcc Row Addresses Row select Memory Cell Array E Vcc I/O13 NC A16 I/O5 Vss F I/O15 I/O14 A14 A15 I/O6 I/O7 I/O1~I/O8 Data cont I/O Circuit Column select G I/O16 A19 A12 A13 WE I/O8 I/O9~I/O16 Data cont H A18 A8 A9 A10 A11 NC Data cont Column Addresses 48-FBGA: Top View (Ball Down) Name Function Name Function, Chip Select Inputs Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O9~16) A0~A19 Address Inputs LB Lower Byte(I/O1~8) I/O1~I/O16 Data Inputs/Outputs NC No Connection OE WE UB LB Control Logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 3

4 PRODUCT LIST 1. LF : Lead Free Product Part Name K6F1616U6C-FF55 K6F1616U6C-XF55 K6F1616U6C-FF70 K6F1616U6C-XF70 Industrial Temperature Products(-40~85 C) Function 48-FBGA, 55ns, 3.0V 48-FBGA, 55ns, 3.0V, LF 1) 48-FBGA, 70ns, 3.0V 48-FBGA, 70ns, 3.0V, LF 1) FUNCTIONAL DESCRIPTION OE WE LB UB I/O1~8 I/O9~16 Mode Power H X 1) X 1) X 1) X 1) X 1) High-Z High-Z Deselected Standby X 1) L X 1) X 1) X 1) X 1) High-Z High-Z Deselected Standby X 1) X 1) X 1) X 1) H H High-Z High-Z Deselected Standby L H H H L X 1) High-Z High-Z Output Disabled Active L H H H X 1) L High-Z High-Z Output Disabled Active L H L H L H Dout High-Z Lower Byte Read Active L H L H H L High-Z Dout Upper Byte Read Active L H L H L L Dout Dout Word Read Active L H X 1) L L H Din High-Z Lower Byte Write Active L H X 1) L H L High-Z Din Upper Byte Write Active L H X 1) L L L Din Din Word Write Active 1. X means don t care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS 1) Item Symbol Ratings Unit Voltage on any pin relative to Vss VIN,VOUT -0.2 to VCC+0.3V(Max. 3.6V) V Voltage on Vcc supply relative to Vss VCC -0.2 to 3.6 V Power Dissipation PD 1.0 W Storage temperature TSTG -65 to 150 C Operating Temperature TA -40 to 85 C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4

5 RECOMMENDED DC OPERATING CONDITIONS 1) Item Symbol Min Typ Max Unit Supply voltage Vcc V Ground Vss V Input high voltage VIH Vcc+0.2 2) V Input low voltage VIL ) V Note: 1. TA=-40 to 85 C, otherwise specified 2. Overshoot: VCC+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and Undershoot are sampled, not 100% tested. CAPACITANCE 1) (f=1mhz, TA=25 C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pf Input/Output capacitance CIO VIO=0V - 10 pf 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ 1) Max Unit Input leakage current ILI VIN=Vss to Vcc -1-1 µa =VIH Output leakage current or =VIL or OE=VIH or WE=VIL or LB=UB=VIH, ILO -1-1 µa VIO=Vss to Vcc Cycle time=1µs, 100%duty, IIO=0mA, 0.2V, LB 0.2V ICC ma or/and UB 0.2V, Vcc-0.2V, VIN 0.2V or VIN VCC-0.2V Average operating current ICC2 Cycle time=min, IIO=0mA, 100% duty, =VIL, 70ns =VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH 55ns ma Output low voltage VOL IOL = 2.1mA V Output high voltage VOH IOH = -1.0mA V Standby Current (CMOS) ISB1 1. Typical values are measured at VCC=3.0V, TA=25 C and not 100% tested. Other input =0~Vcc 1) Vcc-0.2V, Vcc-0.2V( controlled) or 2) 0V 0.2V( controlled) µa 5

6 AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.2V to Vcc-0.2V Input rising and falling time: 5ns Input and output reference voltage:1.5v Output load(see right): CL=100pF+1TTL CL=30pF+1TTL AC CHARACTERISTICS (Vcc=2.7~3.3V, TA=-40 to 85 C) CL 1) VTM 3) 1. Including scope and jig capacitance 2. R1=3070Ω, R2=3150Ω 3. VTM =2.8V R1 2) R2 2) Read Write Speed Bins Parameter List Symbol 55ns 70ns Units Min Max Min Max Read cycle time trc ns Address access time taa ns Chip select to output tco ns Output enable to valid output toe ns LB, UB valid to data output tba ns Chip select to low-z output tlz ns Output enable to low-z output tolz ns LB, UB enable to low-z output tblz ns Output hold from address change toh ns Chip disable to high-z output thz ns OE disable to high-z output tohz ns UB, LB disable to high-z output tbhz ns Write cycle time twc ns Chip select to end of write tcw ns Address set-up time tas ns Address valid to end of write taw ns Write pulse width twp ns Write recovery time twr ns Write to output high-z twhz ns Data to write time overlap tdw ns Data hold from write time tdh ns End write to output low-z tow ns LB, UB valid to end of write tbw ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR Vcc-0.2V 1), VIN 0V V Data retention current IDR Vcc=1.5V, Vcc-0.2V 1), VIN 0V ) 15 µa Data retention set-up time tsdr See data retention waveform ns Recovery time trdr trc ) Vcc-0.2V, Vcc-0.2V( controlled) or 2) 0 0.2V( controlled) 2. Typical value are measured at TA=25 C and not 100% tested. 6

7 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, =OE=VIL, =WE=VIH, UB or/and LB=VIL) Address trc toh Data Out Previous Data Valid Data Valid taa TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) trc Address taa toh tco thz UB, LB tba tbhz OE toe Data out High-Z tolz tblz tlz Data Valid tohz NOTES (READ CYCLE) 1. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 7

8 TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) Address twc tcw(2) twr(4) UB, LB taw tbw twp(1) WE tas(3) tdw tdh Data in High-Z Data Valid High-Z twhz tow Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) ( Controlled) Address twc tas(3) tcw(2) twr(4) taw UB, LB tbw twp(1) WE tdw tdh Data in Data Valid Data out High-Z High-Z 8

9 TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) Address twc tcw(2) taw twr(4) UB, LB WE tas(3) tbw twp(1) tdw tdh Data in Data Valid Data out High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(twp) of low and low WE. A write begins when goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when goes high and WE goes high. The twp is measured from the beginning of write to the end of write. 2. tcw is measured from the going low to the end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr is applied in case a write ends with or WE going high. DATA RETENTION WAVEFORM controlled VCC tsdr Data Retention Mode trdr 2.7V 2.2V VDR GND VCC - 0.2V controlled VCC Data Retention Mode 2.7V tsdr trdr VDR 0.4V 0.2V GND 9

10 PACKAGE DIMENSION Unit: millimeters 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View B B B A #A1 B C D C E C1 C F G H Side View Detail A E1 D A E E1 Y C Min Typ Max A B B C C D E E Y Notes. 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are ±0.050 unless specified beside figure. 4. Typ: Typical 5. Y is coplanarity: 0.10(Max) 10

11 This datasheet has been downloaded from: Datasheets for electronic components.