512KX8 CMOS S-RAM (Monolithic)
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1 512KX8 CMOS S-RAM (Monolithic) Features Access Times: 55, 70, 85 and 100ns Package Option: 32-Pin Ceramic DIP, JEDEC Approved Pinout 36-Lead Ceramic SOJ JEDEC Approved Revolutionary Pinout 32-Lead Ceramic SOJ Industrial and Military Screening TTL Compatible Input/Output Single 5V (±10%) Power Data Retention Product Description The MES5128 is a Monolithic 4 Megabit Static Ram. The module is organized as 512Kx8 and packed in a multilayer High Temperature cofired ceramic package, designed for better speed performance. These modules are available in 55ns to 100ns versions. Low Power versions are also available. Block Diagram December, 2003 Rev. A 1 OF 13
2 Pin Names Truth Table (H=VIH L=VIL X=Don't Care) Pin Name Pin Function OE# WE# CS# I/O Mode A0 A18 Address Inputs X X H Hi-Z Standby D0 D7 Data Inputs/Outputs L H L DOUT Read CS# Chip Select X L L DIN Write WE# Write Enable H H L Hi-Z Out Disable OE# Output Enable GND Ground Vcc Power (+5V ±10%) NC No Connection Note: # Symbol means Active Low Signal Pin Configurations (Top View) DIP (D) CSOJ (J1) CSOJ (J) 1 A18 Vcc 32 1 A18 Vcc 32 2 A16 A A16 A A14 A A14 A A12 WE# 29 4 A12 WE# 29 5 A7 A A7 A A6 A A6 A A5 A A5 A A4 A A4 A A3 OE# 24 9 A3 OE# A2 A A2 A A1 CS# A1 CS# A0 D A0 D D0 D D0 D D1 D D1 D D2 D D2 D GND D GND D3 17 December, 2003 Rev. A 2 OF 13
3 Absolute Maximum Ratings Item Rating Supply Voltage Relative to GND Voltage on Any Pin Relative to GND Operating Temperature Storage Temperature -0.5V to +7.0V -0.5V to Vcc +0.5V -55 C to +125 C -65 C to +150 C Recommended Operating Conditions Parameter Symbol Min Max Unit Supply Voltage VCC V Input High Voltage VIH 2.2 VCC +0.3 V Input Low Voltage VIL V Operating (Military) TA C Temperature (Industrial) C Capacitance (TA = +25 C, VIN = 0V, f = 1.0 MHz) Description Symbol Limits Unit Min Max Input Capacitance CIN 20 pf Output Capacitance COUT 20 pf These parameters are guaranteed, but not tested. December, 2003 Rev. A 3 OF 13
4 DC Characteristics (Vcc = 5V) Parameter Symbol Min Max Units Input Leakage Current ILI (1) -2 2 µa Output Leakage Current ILO (2) -2 2 µa Output Low Voltage VOL (3) 0.4 V Output High Voltage VOH (4) 2.4 V 55ns 5 Standby Supply Current ISB (5) 70ns 5 ma 85ns 5 100ns 3 55ns 50 Dynamic Operating Current ICC (6) 70ns 50 ma 85ns ns 50 Notes: (1) VCC = Max, VI/O = VCC to GND. (2) VI/O = VCC to GND, CS# VIH, OE# VIH. (3) VCC = Min, IOL = +2.1mA. (4) VCC = Min, IOH = -1.0mA. (5) VCC = Max, CS# = VIH, OE# = VIH, f = 5MHz. (6) VCC = Max, CS# = VIL, OE# = VIH, f = 5MHz. December, 2003 Rev. A 4 OF 13
5 AC Characteristics Write Cycle Parameter Symbol 55ns 70ns 85ns 100ns Limits Units Write Cycle Time TAVAV min ns Address Set-up Time TAVWL min ns Address Valid to End of Write TAVWH min ns Data Valid to End of Write TDVWH min ns Chip Select Low to End of Write TELWH min ns Write Pulse Width TWLWH min ns Address Hold from Write End TWHAX min ns Data Hold Time TWHDX min ns Write Enable Low to High Z TWLQZ* max ns Output Active from End of Write TWHQX* min ns Read Cycle Parameter Symbol 55ns 70ns 85ns 100ns Limits Units Read Cycle Time TAVAV min ns Address Access Time TAVQV max ns Output Hold from Addr. Change TAVQX min ns Chip Select Access Time TELQV max ns Output Enable to Output Valid TGLQV max ns Chip Select to Output in Low Z TELQX* min ns Chip Disable to Output in High Z TEHQZ* max ns Output Enable to Output in Low Z TGLQX* min ns Output Disable to Output in High Z TGHQZ* max ns (*) - Parameter is guaranteed, but not tested. December, 2003 Rev. A 5 OF 13
6 December, 2003 Rev. A 6 OF 13
7 December, 2003 Rev. A 7 OF 13
8 AC Test Conditions Item Conditions Input Pulse Levels GND to 3.0V Input Rise and Fall Times 5ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load: 1 TTL Load, CL=100pF Note: For TWHQX, TWLQZ, TEHQZ, TELQX, TGHQZ and TGLQX CL = 5pF Data Retention Characteristics (Over Operating Temp Range) Test Conditions: GND = 0V, VCC=3V, CS# VCC-0.2V, VIH VCC - 0.2V, VIL 0.2V. Characteristic Symbol Min Typ. Max Unit VCC for Data Retention VDR 2.4 V D.R Quiescent Current ICCDR 100 (1) 400 (1) µa Chip Disable to D.R Time TCDR 0 nsec Operation Recovery Time TR 5 nsec (1) Lower D.R Currents are available upon request Data Retention (CS# - Controlled) December, 2003 Rev. A 8 OF 13
9 Outline Drawing for 32-Pin Ceramic DIP (D) December, 2003 Rev. A 9 OF 13
10 Outline Drawing for 32-Lead Ceramic SOJ (J1) December, 2003 Rev. A 10 OF 13
11 Outline Drawing for 36-Lead Ceramic SOJ (J) December, 2003 Rev. A 11 OF 13
12 Ordering Information (Standard Military Screened Products*) Model Number Speed Package MES5128D55MNL 55ns CDIP32 MES5128D70MNL 70ns CDIP32 MES5128D85MNL 85ns CDIP32 MES5128D100MNL 100ns CDIP32 MES5128J155MNL 55ns CSOJ32 MES5128J170MNL 70ns CSOJ32 MES5128J185MNL 85ns CSOJ32 MES5128J1100MNL 100ns CSOJ32 MES5128J55MNL 55ns CSOJ36 MES5128J70MNL 70ns CSOJ36 MES5128J85MNL 85ns CSOJ36 MES5128J100MNL 100ns CSOJ36 (*) - Contact Elisra for additional designs December, 2003 Rev. A 12 OF 13
13 Part Number Breakdown December, 2003 Rev. A 13 OF 13
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REVISION ISTORY Revision Description Issue Date Initial Issue Jul.13.2011 0 FEATURES Fast access time : 55/70ns ow power consumption: Operating current : 45/30mA (TYP.) Standby current : 10A (TYP.) -version
A24C02. AiT Semiconductor Inc. ORDERING INFORMATION
DESCRIPTION provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 256 words of 8 bits each. The device is optimized for use in many industrial and
DS1225Y 64k Nonvolatile SRAM
19-5603; Rev 10/10 NOT RECOMMENDED FOR NEW DESIGNS 64k Nonvolatile SRAM www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during
LY62L102516A 1024K x 16 BIT LOW POWER CMOS SRAM
Y62102516A 1024K x 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jan. 09. 2012 Rev. 1.1 Deleted WRITE CYCE Notes : 1.WE#,, B#, UB# must be high or must
AS6C TINL 16M Bits LOW POWER CMOS SRAM
REVISION ISTORY Revision Description Issue Date Initial Issue Jan. 09. 2012 0 FEATURES Fast access time : 55ns ow power consumption: Operating current : 45mA (TYP.) Standby current : 4 A (TYP.) S-version
AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 V CC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current Icc1 on
HT93LC46 CMOS 1K 3-Wire Serial EEPROM
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M Rev: /10
www.centon.com MEMORY SPECIFICATIONS 16,777,216 words x 64Bit Synchronous Dynamic RAM Memory Module (Unbuffered DIMM) Centon's 128MB Memory Module is 16,777,216 words by 64Bit Synchronous Dynamic RAM Memory
512Kx32 Synchronous Pipeline Burst SRAM
* 512Kx32 Synchronous Pipeline Burst SRAM FEATURES Fast clock speed: 200, 166, 150 & 133MHz Fast access times: 3.0ns, 3.5ns, 3.8ns & 4.0ns Fast OE# access times: 3.0ns, 3.5ns, 3.8ns 4.0ns +3.3V power supply
LY62L409716A 4M X 16 BIT LOW POWER CMOS SRAM
Y62409716A 4M 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jun.08.2017 yontek Inc. reserves the rights to change the specifications and products without
D0 - D8 INPUT REGISTER. RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 OUTPUT REGISTER RESET LOGIC RCLK REN1
CMOS SyncFIFO 64 x 9, 256 x 9, 512 x 9, 1,24 x 9, 2,48 x 9, 4,96 x 9 and 8,192 x 9 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 218 FEATURES: 64 x 9-bit organization (IDT72421)
24AA01/24LC01B. 1K I 2 C Serial EEPROM. Description: Device Selection Table. Features: Package Types. Block Diagram. Part Number.
K I C Serial EEPROM Device Selection Table Part Number Features: Range Max. Clock Frequency Temp. Ranges AA0.7-. 00 khz () I LC0B.-. 00 khz I, E Note : 00 khz for
WINTEC I. DESCRIPTION: III. TIMING
ISIONS ZONE DESCRIPTION APPVD 1/26/01 NR I. DESCRIPTION: III. TIMING is a 8Mx64 industry standard 8-pin PC-100 DIMM Manufactured with 4 8Mx 400-mil TSOPII-54 100MHz Synchronous DRAM devices Requires 3.3V+/-0.3V
3.3V CMOS 1-TO-5 CLOCK DRIVER
3. CMOS 1-TO-5 CLOCK DRIVER 3. CMOS 1-TO-5 CLOCK DRIVER IDT74FCT38075 FEATURES: Advanced CMOS Technology Guaranteed low skew < 100ps (max.) Very low duty cycle distortion< 250ps (max.) High speed propagation
LY62L K X 16 BIT LOW POWER CMOS SRAM
REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 1.1 Revised Package Outline Dimension(TSOP-II) Apr.12.2007 Rev. 1.2 Added ISB1/IDR values when TA = 25 and TA = 40
ISSI IS23SC4418 IS23SC KBYTE EEPROM WITH WRITE PROTECT FUNCTION AND PROGRAMMABLE SECURITY CODE (PSC) IS23SC4418 IS23SC4428 FEATURES DESCRIPTION
1-KBYTE EEPROM WITH WRITE PROTECT FUNCTION AND PROGRAMMABLE SECURITY CODE (PSC) NOVEMBER 2001 FEATURES Standard CMOS process 1024 x 8 bits EEPROM organization Byte-wise addressing Byte-wise erase/write
IS62/65WVS5128GALL IS62/65WVS5128GBLL. 512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION
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A24C64. AiT Semiconductor Inc. ORDERING INFORMATION
DESCRIPTION provides 65536 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 8192 words of 8 bits each. The is optimized for use in many industrial and commercial
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
Integrated evice Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 124 X 9, 248 X 9 and 496 x 9 IT72421 IT7221 IT72211 IT72221 IT72231 IT72241 FEATURES: 64 x 9-bit organization (IT72421) 256 x 9-bit
MB85R K (32 K 8) Bit. Memory FRAM DS E CMOS DESCRIPTIONS FEATURES PACKAGES FUJITSU SEMICONDUCTOR DATA SHEET
FUJITSU SEMICONDUCTOR DATA SHEET DS05-13101-4E Memory FRAM CMOS 256 K (32 K 8) Bit MB85R256 DESCRIPTIONS The MB85R256 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words
PCMCIA / JEIDA SRAM Card
PCMCIA / JEIDA SRAM Card Product Specification June 2009 PRETEC/C-ONE Technology Corp. Corporate Headquarters 8F, NO5, Lane 345, Yang Guang St., Neihu, Taipei,Taiwan TEL: +886-2-2659-4380 Fax: +886-2-2659-4390
ATF16V8B. High Performance Flash PLD. Features. Block Diagram. Description. Pin Configurations
Features Industry Standard Architecture Emulates Many 20-Pin PALs Low Cost Easy-to-Use Software Tools High Speed Electrically Erasable Programmable Logic Devices 7.5 ns Maximum Pin-to-Pin Delay Several
ICE27C Megabit(128KX8) OTP EPROM
1- Megabit(128KX8) OTP EPROM Description The is a low-power, high-performance 1M(1,048,576) bit one-time programmable read only memory (OTP EPROM) organized as 128K by 8 bits. It is single 5V power supply
HX K x 8 STATIC RAM
32K x 8 STATIC RAM PRODUCTION - Release - 02 Sep 2014 12:28:58 MST - Printed on 03 Sep 2014 The monolithic 32K x 8 Radiation Hardened Static RAM is a high performance 32,768 word x 8-bit static random
25AA160A/B, 25LC160A/B
Device Selection Table 25AAA/B, 25LCA/B 16K SPI Bus Serial EEPROM Part Number VCC Range Page Size Temp. Ranges Packages 25LCA 2.5-5.5V 16 Byte I,E P, SN, ST, MS 25AAA 1.8-5.5V 16 Byte I P, SN, ST, MS 25LCB
IS62/65WVS1288FALL IS62/65WVS1288FBLL. 128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE DESCRIPTION
128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE JANUARY 2018 KEY FEATURES SPI-Compatible Bus Interface: - 16/20 MHz Clock rate - SPI/SDI/SQI mode Low-Power CMOS Technology: - Read Current:
LY62L205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM
Y62205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Sep.06.2012 Rev. 1.1 Add 25 & 40 spec for ISB1 & IDR on page 4 &
IDT54/74FCT244/A/C FAST CMOS OCTAL BUFFER/LINE DRIVER DESCRIPTION: FUNCTIONAL BLOCK DIAGRAM FEATURES: OEA OEB DA1 OA1 DB1 OB1 DA2 OA2 OB2 DB2 DA3 OA3
FAST CMOS OCTAL BUFFER/LINE DRIVER IDT/7FCT/A/C FEATURES: IDT/7FCTA equivalent to FAST speed and drive IDT/7FCTA % faster than FAST IDT/7FCTC up to % faster than FAST IOL = ma (commercial) and 8mA (military)