Prototyping Radiation Tolerant Microsemi FPGAs
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1 1 Prototyping Radiation Tolerant Microsemi FPGAs Takeshi Miyajima Technical Director Aldec Japan Rev. 1.0
2 Agenda 2 Today s Prototyping of RTAX-S/SL and RTSX-SU FPGAs Aldec/Microsemi Innovative Prototyping Solution Aldec RTAX-S/SL prototyping adaptor example Aldec RTSX-SU prototyping adaptor example Aldec RTAX2A3P EDIF Netlist and PDC File Conversion Summary
3 Today s Prototyping Solution 1 3 Socket + AX/SX-A Approach Good solution, but several design iterations could require several of the OTP (One Time Programmable) or Microsemi AX/SX-A commercial chips to complete the design. Weak Point The potential risk for using several of these OTP or AX/SX-A devices could add to the overall project cost and impact the budget.
4 Today s Prototyping Solution 2 4 Different Vendor Re-programmable Device Approach Expensive radiation tolerant device can be replaced with cheaper re-programmable device manufactured by some other vendor. Weak Points Different set of tools and libraries is needed. Dual footprint board increases costs.
5 What Solution Could Be Better? 5 Solutions from the two previous slides are not optimal. Probably there are no ideal solutions, but we can formulate two request that could make new solution much better than the others: 1. Solution should use reprogrammable devices (to minimize cost). 2. Solution should use devices with internal logic architecture as close as possible to the radiation tolerant device being prototyped (to minimize design file translations).
6 Aldec Re-programmable Solution 6 Ability to prototype RTAX-S/SL and RTSX-SU designs using reprogrammable Microsemi Flash ProASIC 3E FPGA family chips Adaptor board is footprint-compatible with the final RTAX-S/SL and RTSX-SU device Programming connector (JTAG) allows on-the-fly reprogramming of the device without detaching the adaptor from the target PCB EDIF netlist converter allows to migrate from RTAX-S/SL and RTSX- SU to ProASIC 3E FPGA easily Design efficiency is achieved, saving Development Time and Costs
7 Aldec Complementary Design Flow 1 7 Create and Verify Design Code Synthesize and Implement for ProASIC3 FPGA Test in Hardware: Results OK? Y Synthesize and Implement for flight FPGA Final Hardware Tests N Modify and Verify Design Code No throwaways! Preferred flow for PURE HDL Designs
8 Aldec Complementary Design Flow 2 8 Generate netlist for target technology No throwaways! Netlist Conversion Implement for ProASIC3 FPGA Test in Hardware: Results OK? Y Implement for flight FPGA Final Hardware Tests N Modify and Verify Design Code Flow for schematic and legacy designs
9 Sample RTAX-S/SL Adaptor Board 9 A3PE3000-FGG896 JTAG Connector ACT-H3K-CG624 Adaptor Adaptor size: 32.5mm x 34mm The following elements reside on the top part of the adaptor Microsemi ProASIC3E FPGA device, A3PE3000-FGG896 (or A3PE3000-2FGG896I) JTAG connector Capacitors, resistors Capacitors Ball grid array that mimics CG624 package The following elements reside on the bottom part of the adaptor Leads that mimic CG624 package
10 Sample RTSX-SU Adaptor 10 Mother Board of ACT-RTSX-CQ256 adaptor: Top side with visible Microsemi ProASIC3E device (A3PE600-FGG484 or A3PE600-2FGG484I) Bottom side with leads mimicking CQ256 package Mother board and daughter board of ACT-RTSX-CQ256 adaptor in stacked configuration
11 Available Adaptors 11 ALDEC is constantly extending the assortment of adaptors. RTAX-S/SL adaptor boards are available in the following footprint layouts: Commercial grade: CQ208, CQ256, CQ352, CG624, CG1272 Industrial grade: CQ208, CQ256, CQ352, CG624 RTSX-SU adaptors are available in the following footprints: Commercial grade: CQ208, CQ256, CG624 Industrial grade: CQ208, CQ256, CG624
12 RTAX2A3P EDIF Netlist Converter 12 RTAX2A3P EDIF Netlist Converter performs automatic conversion of the RTAX-S/SL and RTSX-SU EDIF netlist to ProASIC3E FPGA EDIF netlist. FEATURES: Conversion of combinatorial primitives Conversion of sequential primitives Conversion of I/O macros Memory conversion Replacement of sequential primitives to TMR primitives
13 EDIF Netlist Converter Flow 13 RTAX-S/SL RTSX-SU EDIF netlist RTAX and RTSX to ProASIC3E FPGA Converter ProASIC3E FPGA EDIF netlist RTAX-S/SL RTSX-SU PDC/PIN file ProASIC3E FPGA PDC file Primitives Library Pin Location Library Input RTAX-S/SL or RTSX-SU EDIF netlist RTAX-S/SL PDC file or RTSX-SU PIN file Output ProASIC3E FPGA EDIF netlist ProASIC3E FPGA PDC file for selected adaptor board Implementation for ProASIC3E FPGA in Microsemi Designer
14 Summary 14 Why should you consider this prototyping solution: Reduce chip costs Save Development Time Re-Programmability ProASIC 3 FPGA flash-based technology Wide Device & Package Support: CQ208, CQ256, CQ352 & CG624 packages Footprint compatible adaptors Automatic translation of netlist, memories and constraints Customer proven with over 300 units shipped worldwide
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