Packaging Innovation for our Application Driven World

Transcription

1 Packaging Innovation for our Application Driven World Rich Rice ASE Group March 14 th, 2018 MEPTEC / IMAPS Luncheon Series 1

2 What We ll Cover Semiconductor Roadmap Drivers Package Development Thrusts Collaboration Summary 2

3 What We ll Cover Semiconductor Roadmap Drivers Package Development Thrusts Collaboration Summary 3

4 Semiconductor Roadmap Drivers Moving from Moore s Law driven to system level integration driven technologies. Source: Yole 2.5D/3D Business Update

5 IC and Systems Drivers Converge IC Developer Driven Device Package SiP & SiM OSAT & EMS Integration & Miniaturization Value Up & Cost Down System OEM Driven System Module 5

6 Advanced Packaging Provides a Solution Package level homogenous and heterogeneous integration enables the next level of performance Source: Yole, 3D / 2.5D Business Update

7 What We ll Cover Semiconductor Roadmap Drivers Package Development Thrusts Collaboration Summary 7

8 FC BGA Technology Trends Performance Large PKg >60 / Thin & Coreless 2.5D / FO FCBGA Low Profile Fine Pitch FC BGA MCM & SIP N12, N10, N7 150um core / 130um CuP bump pitch ubump, BOT/BOL ~

9 Mobile - Fine Pitch Capability Advantage of ETS on fine pitch 28 nm a-fccsp I a-fccsp II 20/16/14 nm 10 nm/7nm 60 um ETS 100um 120um 90 um CuBoL ETS ETS 150um 110um 150um

10 Drivers for 2.5/3D Integration Source: Yole 2.5D/3D Business Update 2017 Higher performance Increased bandwidth Lower latency Reduced power consumption Integration of mixed nodes & functionality Yield / cost optimization 10 10

11 Addressing High End Integration 2.5D IC Package Positioning 100,000 s 2.5D IC D2D Interconnect 10,000 s FanOut FOCoS 1,000 s Flip Chip MCM 25/25 15/15 10/10 Line / Space (um) 5/5 2/2 1/1 0.5/0.5 11

12 Solder Bump & Microbump Roadmap Solder Bump mm Pitch C4 Bump Pitch (mm) mbump 130mm Pitch Cu Pillar 110mm Pitch Cu Pillar mm UBM 45mm Pitch Production 20mm UBM 40mm Pitch 15mm UBM 30mm Pitch

13 Molded 2.5D IC Test Vehicle Package Description Package: 55x55 ASIC + HBM x4 ASIC: 26x22 mm Interposer: 36x28 mm Package: 55x55 mm ASIC x2 ASIC: 29x18 mm (x2) Interposer: 38x31 mm Package: 47.5x47.5 ASIC + HBM x2 ASIC: 26x19 Interposer: 30x28 mm Production Ready 13

14 Competitive Solutions Flip Chip and Fan Out Platforms Chip Last- Build Carrier Before Die Bond High End 2.5D FC BGA CuBoL ETS a-fccsp Low End 1L (ETS/CIM) High End Low End a-wlp Chip First- Build Carrier Around Die 2.1D awlp-3d-2sided awlp2-2die awlp FoCOS Superior price / performance will win! 14

15 Eng/Qual In Production M-Series BB, RF, Codec, PMIC.. FOPoP AP & Memory Integration.. FOSiP AP & Memory, RF Module.. BB, RF, Codec, PMIC, Car Radar. ewlb BB, RF, Codec, PMIC.. FOCLP BB, RF, Codec, PMIC.. FOCoS Networking, Server.. 15

16 Wirebond Technology Is Still Advancing 1967 Mature Reliable Easy to use HUGE capacity Low Cost

17 Sensor & SiP Solutions Focus Industrial Wearable Medical Home Consumer Automotive 17

18 MEMS / Optical Sensors Environment Device Gas Sensor Temperature sensor Humidity sensor Ultrasound sensoranalogmicrophone DigitalMicrophone Radar FingerPrint Gesture RF Device MEMS Oscillator RF IC RF switch Pressure Sensors High Resolution Barometer Tire Pressure Sensor Force Sensor Low-gAccelerometer Medium-gAccelerometer Inertial Measurement Unit InertialSensors Medium-RateGyroscope High-RateGyroscope Optical Devices Electrostatic Mirror Proximity sensor Ambient light UV sensor TOF/CIS sensor Lidar Magnetic Sensors High Res.Compass Magnetometer Hall sensor Pulse sensor Oximetry sensor Thermopile IR sensor Spectrum meter Gesture sensor FingerPrint 18

19 MEMS/Sensor Tool Box Stealth laser dicing Plasma dicing Innovative Dicing Technology Stress Lab Thermal Lab Electrical Lab Optical lab Material Lab Simulation Package Design New materials Embedded Substrate Solution MEMS Various Molding Technology EMI Technology FAM : OCQFN, PMQFN Compression molding Transfer molding Active/passive component embedded Integrated IPD and MEMS solution SESUB solution Plastic lid metallization Metal lid w/ different coating technology 19 19

20 SiP Core Technologies Embedded Technology Shielding Antenna Mechanical Assy SMT Interconnection Die / Pkg Stacking Wafer Bumping / WLP Molding POG / IPD 20 20

21 What We ll Cover Semiconductor Roadmap Drivers Package Development Thrusts Collaboration Summary 21

22 Collaboration TDK and ASEEE JV SESUB (ASEEE) Module Design Test Assembly SMT Simulation Bumping 22

23 M-Series Low Density Chip First Die Up Chip First Die Up 23

24 SiP Intelligent Design The Next Generation of SiP Design Tool ASE Group collaborates with Cadence on SiP-id solution that addresses the design/verification challenges of complex layout of advanced packages, including ultra-complex SiP, Fan-Out and 2.5D packages 24

25 What We ll Cover Semiconductor Roadmap Drivers Package Development Thrusts Collaboration Summary 25

26 Key Messages Semi growth in 2017, growing but moderating in 2018 End applications drive very different packaging technologies Advancing and leveraging existing packaging platforms We must collaborate for success Foundries Customers Design Tools Suppliers OSAT Technology Alliances 26

27 Thank you Follow ASE on 27