Moore s Law: Alive and Well. Mark Bohr Intel Senior Fellow

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2 Moore s Law: Alive and Well Mark Bohr Intel Senior Fellow

3 Intel Scaling Trend Micron nm nm 14 nm 10 nm

4 Intel Scaling Trend Micron nm nm 14 nm 10 nm Dimensions scale to provide improved performance, lower power and lower cost per transistor

5 10 Inflection Points DRAM High Performance Processors 1000 Micron 0.1 Performance Low Power 100 nm nm 14 nm 10 nm Performance Low Power Dense SoC Product markets change, and thus the goals of scaling change

6 Transistor Evolution 90 nm 65 nm 45 nm 32 nm 22 nm SiGe Strained Silicon High-k Metal Gate Innovations in both device materials and device structures are now needed to continue scaling Tri-Gate

7 Lower Leakage Power The Value of Better Transistors 65 nm 45 nm 32 nm 22 nm 14 nm* 1x Server Computing 0.1x 0.01x 0.001x Higher Transistor Performance (switching speed) Source: Intel * Forecast

8 Lower Leakage Power The Value of Better Transistors 65 nm 45 nm 32 nm 22 nm 14 nm* 1x Server Computing 0.1x Client Computing 0.01x Mobile Computing 0.001x Mobile Always-On Circuits Higher Transistor Performance (switching speed) The same fundamental improvement benefits a wide range of products Source: Intel * Forecast

9 $ / Transistor (normalized) Active Power (normalized) Getting the Benefits of Moore s Law Lower Cost per Transistor Lower Active Power nm 45 nm 32 nm 22 nm 14 nm* 10 nm* nm 32 nm 22 nm 14 nm* Source: Intel * Forecast

10 Switching Energy Change (%) -65% Getting the Benefits of Moore s Law 160 Lower Power nm nm Gate Delay Change (%)

11 Switching Energy Change (%) Getting the Benefits of Moore s Law 160 Higher Performance nm 0-40% nm Gate Delay Change (%)

12 Benefits Across all Product Families Performance 2x 1x 10x Server Laptop Mobile Server Laptop Mobile Server Laptop Mobile 1x.25x 1x 45 nm 32 nm 22 nm 14 nm* Performance improved for all product families 45 nm 32 nm 22 nm 14 nm* 45 nm 32 nm 22 nm 14 nm* Source: Intel * Forecast

13 Benefits Across all Product Families Performance Active Power (Includes performance increase) 2x 1x 10x Server Laptop Mobile Server Laptop Mobile Server Laptop Mobile 1x.25x 1x 45 nm 32 nm 22 nm 14 nm* Performance improved for all product families 45 nm 32 nm 22 nm 14 nm* Active power reduced for all product families 45 nm 32 nm 22 nm 14 nm* Source: Intel * Forecast

14 Benefits Across all Product Families Performance Active Power (Includes performance increase) Performance per Watt 2x 1x 10x Server Laptop Mobile Server Laptop Mobile Server Laptop Mobile 1x.25x 1x 45 nm 32 nm 22 nm 14 nm* Performance improved for all product families 45 nm 32 nm 22 nm 14 nm* Active power reduced for all product families 45 nm 32 nm 22 nm 14 nm* Performance per watt improves >1.6x per generation Improved performance per watt is the critical enabler for all Source: Intel * Forecast

15 130 nm 90 nm 65 nm Density Improvements Offset Wafer Cost Trend 45 nm 32 nm 22 nm 14 nm* 10 nm* 100 $ / mm 2 (normalized) 10 1 Source: Intel * Forecast

16 130 nm 90 nm 65 nm Density Improvements Offset Wafer Cost Trend 45 nm 32 nm 22 nm 14 nm* 10 nm* 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm* 10 nm* 100 $ / mm 2 (normalized) 1 mm 2 / Transistor (normalized) 10 x Source: Intel * Forecast

17 130 nm 90 nm 65 nm Density Improvements Offset Wafer Cost Trend 45 nm 32 nm 22 nm 14 nm* 10 nm* 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm* 10 nm* 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm* 10 nm* 100 $ / mm 2 (normalized) 1 mm 2 / Transistor (normalized) 1 $ / Transistor (normalized) 10 x = Cost per Transistor reducing by better than 0.7x per generation Source: Intel * Forecast

18 Product Market Changes 65 nm CPU (2005) 22 nm SoC (2013) SoC products integrate a wider range of circuit and device types

19 Expanding the Technology Envelope Voltage Ceiling 1.2V CPU Density Low Digital Device 0.1x Leakage Floor

20 Expanding the Technology Envelope Voltage Ceiling 3.3V SoC 1.2V CPU Density Low Digital Device 0.1x Leakage Floor

21 Expanding the Technology Envelope Voltage Ceiling 3.3V SoC 1.2V CPU Density Low Digital Device 0.1x.001x Leakage Floor

22 Expanding the Technology Envelope Voltage Ceiling 3.3V SoC 1.2V CPU Density High Low Digital Device 0.1x.001x Leakage Floor

23 Expanding the Technology Envelope Voltage Ceiling 3.3V SoC 1.2V CPU Density High Low Digital Mixed Signal RF Device 0.1x.001x Leakage Floor

24 Intel Custom Foundry High Speed SerDes IP 22 nm 14 nm General Purpose 12G Productized 16G 1-12G 1-16G Test Silicon High Speed 28G Productized Coming Soon 19-28G 10-32G Taped-Out Industry leading power, performance, area Intel Tri-gate transistors + leading edge architecture

25 Interconnect Options Enable Product Optimization CPU CPU SoC SOC Gate Density Performance High Perf High Perf CPU CPU Standard Standard SoC SoC High Density High Density SoC SoC Ultra High Ultra High Density Density SoC SoC

26 Expanding the Breadth of Technology Options Intel Intel Custom Foundry Features Logic Transistor I/O Transistor Interconnect Embedded Memory Basic Analog/ Passives Library Adv. Mixed Signals/ RF Options Client/ Server Chipsets Tablets Embedded DRAM Wireless Products Smart Phones Entry Mobile FPGA/ HP - High Perf. SP Std. Perf/Pwr LP - Low Power 1.2V 1.8V 3.3V RC Performance High Density Low Cost COB e-sram High Performance e-sram Low Voltage e-sram Low Power e-sram Dual Port e-prom/otp e-dram Resistor - Linear Capacitor MOS, MFC Capacitor - MIMCAP Inductor - Standard High Performance General Purpose High Density Transistor PA Resistor - Precision Capacitor - Linear Inductor High Q Deep Nwell/Triple Well High Res Substrate ASIC

27 System Integration Modern microprocessors integrate many of the separate system components from past platforms

28 System Integration Cell Phone Platform Processor CPU Memory DRAM SRAM NAND Flash NOR Flash Sensors 3-Axis Accelerometer 3-Axis Gyroscope Compass Wireless Baseband Processor WiFi Bluetooth RF Transceiver RF Power Amp Tx/Rx Switch Misc Power Management Unit Audio CODEC Display Interface System integration opportunities in the mobile market

29 System Integration Discrete ICs 2-D Integration (SoC) SoC provides smaller footprint and improved performance/power

30 System Integration Discrete ICs 2-D Integration (SoC) 3-D Integration (SiP) Logic Memory Power Reg. Radio Sensors Photonics 3-D integration is useful for combining disparate technologies Unlike scaling, 3-D does not provide lower cost per transistor

31 Conclusion Scaling requires continued innovations in device materials and structures A highly coordinated research-development-manufacturing pipeline is needed to bring innovative technologies to volume manufacturing Intel s 14 nm generation provides a wide range of SoC features and delivers significant improvements in performance, power and cost per transistor The 10 nm generation is projected to continue to provide similar benefits

32 Conclusion Scaling requires continued innovations in device materials and structures A highly coordinated research-development-manufacturing pipeline is needed to bring innovative technologies to volume manufacturing Intel s 14 nm generation provides a wide range of SoC features and delivers significant improvements in performance, power and cost per transistor The 10 nm generation is projected to continue to provide similar benefits Moore s Law is indeed alive and well!