High Performance Embedded Applications. Raja Pillai Applications Engineering Specialist

Transcription

1 High Performance Embedded Applications Raja Pillai Applications Engineering Specialist

2 Agenda What is High Performance Embedded? NI s History in HPE FlexRIO Overview System architecture Adapter modules Peer-to-peer streaming New FlexRIO Module 1 st Demo Building a HPE system Case Studies 2 nd Demo Q&A and discussion

3 What is High Performance Embedded? Autonomous Vehicles Medical Imaging Signal Intelligence Software- Defined Radio Scientific Research Vision

4 High Performance Embedded Requirements Very high data rates Many channels or very fast stream A strong Real-time requirement Processing & determinism Flexible & Open As much about discovery as it is performance Must play nice with others Fast Host, sensor, actuator, other bus communication Not seconds, nanoseconds Robust & Secure Part of the solution, not the problem

5 NI s History in HPE

6 NI s History in HPE

7 FPGA Technology Programmable Interconnects Logic Blocks Field-Programmable Gate Array I/O Blocks

8 FPGA Logic Implementation E Implementing Logic on an FPGA: F = {(A+B)CD} E LabVIEW FPGA Code F A B C D

9 Why are FPGAs useful? High Reliability Designs implemented in hardware High Performance Computational abilities open new possibilities for measurement and data processing speed True Parallelism Enables parallel tasks and pipelining, reducing test times Low Latency Run algorithms at deterministic rates down to 5 ns Reconfigurable Create DUT / application-specific personalities

10 NI FlexRIO System Architecture PXIe NI FlexRIO Adapter Module Interchangeable I/O Analog or digital NI FlexRIO Adapter Module Development Kit (MDK) NI FlexRIO FPGA Module Kintex-7 FPGA 132 digital I/O lines Up to 2 GB of DRAM PXI Platform Synchronization Clocking/triggers Power/cooling Data streaming

11 NI FlexRIO System Architecture PXIe NI FlexRIO Adapter Module Interchangeable I/O Analog or digital NI FlexRIO Adapter Module Development Kit (MDK) NI FlexRIO FPGA Module Kintex-7 FPGA 132 digital I/O lines Up to 2 GB of DRAM PXI Platform Synchronization Clocking/triggers Power/cooling Data streaming

12 NI FlexRIO Adapter Modules Digital Analog 100 Mbps SE DIO 300 Mbps LVDS DIO 100MHz BW, 4.4 GHz RF I/O 200MHz BW, 4.4 GHz RF Rx 200MHz BW, 4.4 GHz RF Tx 2 ch. 3 GS/s, 8-bit AI 2 ch. 1.6 GS/s, 12-bit AI 300 Mbps SE/LVDS DIO 1 Gbps LVDS DIO 2 ch. 250 MS/s, 14-bit AI/16-bit AO 2 ch. 250 MS/s, 16-bit AI 4 ch. 250 MS/s, 14-bit AI 32 ch. 16 ch. 50 MS/s, 50 MS/s, 12-bit AI 14-bit AI 2 GS/s 14-bit AO Camera Link RS-485/422 2 ch. 100 MS/s, 14-bit AI/16-bit AO 2 ch. 40 MS/s, 12-bit AI 2 ch. 80 MS/s, 14- bit AI 2 ch. 120 MS/s, 16-bit AI 4 ch. 120 MS/s, 16-bit AI 2 ch GS/s, 14-bit AO

13 7 Series FPGA Module NI PXIe-7975R PXIe-7966R PXIe-7975R FPGA Xilinx Virtex-5 Xilinx Kintex-7 DRAM Size 512 MB 2 GB DRAM Theoretical Bandwidth 3.2 GB/s 10.6 GB/s PXI Express Bandwidth (bi-directional) 800 MB/s (700 MB/s) 1.75 GB/s (1.2 GB/s)

14 NI FlexRIO Adapter Module Development Kit (MDK) CAD files (for PCB outline and gold finger cell) Detailed drawings Hardware documentation Software documentation Metal adapter module enclosures

15 NI FlexRIO Peer-to-Peer Architecture > 1.6 GB/s one-way > 1.2 GB/s both ways ~10 us latency Up to 16 streams per FPGA

16 Case Study: Demo Video

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18 Processor 8135 FPGA RF out RF in FPGA Processor x 8 MIMO

19 The Dilemma: Build or Buy? Build Advantages Custom HW/SW solution Maximum flexibility Ability to get exactly what you want Disadvantages Long lead times for new product Significant resource requirements Higher life-cycle costs Buy Advantages Off-the-shelf hardware/software solution Use fewer resources because systems are pre-built Shorter time to market Lower life-cycle costs Disadvantages Often pay for much more than you need Limited flexibility Limited functionality

20 Challenges of Buying COTS Technology Predefined Functionality Limited Flexibility Generic Performance

21 Digital I/O ADC/DAC Interfaces (I/O Timing, FIFOs) DMA and Registers (I/O Timing, FIFOs) Typical Custom Design with I/O Clocking Clocking structure (MMCM s, constraints) ADC PCI Express DAC IP / Algorithms Front End Configuration DRAM Interface (I/O Timing, FIFOs) DRAM, SRAM, EEPROM

22 Digital I/O ADC/DAC Interfaces (I/O Timing, FIFOs) DMA and Registers (I/O Timing, FIFOs) LabVIEW FPGA and NI RIO Clocking Clocking structure (MMCM s, constraints) ADC PCI Express DAC LabVIEW LabVIEW FPGA FPGA Front End Configuration DRAM Interface (I/O Timing, FIFOs) DRAM, SRAM, EEPROM

23 What if you could delegate the integration of the latest technology? delegate the handling of EOL components? skip the repetitive parts of your designs? tackle more projects with smaller teams? get to first prototype faster? deploy on the same platform you used to prototype?

24 Graphical System Design A platform-based approach for measurement and control

25 Painful debugging & rework Design Flow in LabVIEW FPGA Design, implement, verify Hierarchy / Block diagram Coding Compilation Synthesis Simulation / Verification Fitting / place & route Timing verification Digital Design Principles and Practices John F. Wakerly Get to HW and I/O quickly and successfully Compile to verify performance and resources Minimize HW debugging, rework, and recompilation Simulate for quick, iterative development Simulate for functional verification Design Implement Compile Verify (HW) LabVIEW FPGA Simulate Lengthy process Limited visibility

26 Value of Graphical Programming for FPGAs How we think: How we program: Source: Wikipedia Enable a domain expert to program FPGAs

27 PXI System

28 4X Design Productivity: Half the Time with Half the Team NI UBM Size of core embedded team (average # of SW/HW/firmware engineers) Complete projects in (months) On/ahead of schedule 58% 42% Behind schedule/late 38% 55%

29 Implementing FPGA Control of a Single Atom Interested in testing interaction of single atoms with single photons Built NI FlexRIO-based feedback system to control the position of a single atom. Monitoring of specialized sensors and manipulation of control elements.

30 World s First Real-Time 3D OCT Imaging System Combining 320 simultaneous channels, 22 FPGAs, peer-to-peer streaming, and GPUs to achieve real-time 3D imaging LabVIEW, PXI, and FlexRIO for system design LabVIEW for system integration and control PXI for synchronization and data streaming FlexRIO for FPGA processing (>700,000 FFTs per second) We leveraged the flexibility and scalability of the PXI platform and NI FlexRIO to develop the world s first real-time 3D OCT imaging system. Rendered 3D fingerprint image

31 High Performance Embedded Requirements Very high data rates Many channels or very fast stream A strong Real-time requirement Processing & determinism Flexible As much about discovery as it is performance Must play nice with others Fast Host, sensor, actuator, other bus communication Not seconds, nanoseconds Robust Part of the solution, not the problem

32 Conclusions FPGAs can have a very powerful impact in our approach to test, by enabling new methodologies to address modern testing challenges. NI FlexRIO and LabVIEW FPGA bring the power of FPGAs to test engineers and domain experts, allowing you to concentrate on your actual application without having to worry about the hardware-specific details.