Optimizing HDL IP Development with Real-World I/O. William Baars National Instruments

Transcription

1 Optimizing HDL IP Development with Real-World I/O William Baars National Instruments

2 Agenda IP Development Process Traditional Algorithm Engineering Components required for HDL IP Algorithm Engineering Technology Demonstration

3 Traditional IP Development Specify/Model desired functionality Design IP Develop the HDL IP Simulate the design, debug and optimize Deploy IP Instantiate the IP in hardware

4 IO Related Challenges System Noise Harmonic Distortion Analog circuit non-linearity/ideality Channel impairments Protocol errors, collisions

5 Typical System Architecture Memory Processor FPGA IO Circuit IP

6 IP Evaluation Challenges Glue Logic Memory Processor FPGA IO Circuit Software IP Evaluation Software Development IP Integration

7 Inefficiencies with Traditional Approach HDL developers and domain experts spend time on infrastructure tasks rather than IP development Requires expertise in many areas beyond IP under development Testing of HDL IP happens late in development cycle

8 ALGORITHM ENGINEERING

9 A New Approach for IP Development = combination of theoretical algorithm design with real-world data

10 Architecture for Algorithm Engineering Memory CPU FPGA IO Circuit IO Circuit IP IO Input/Output Circuit Circuit

11 Architecture for Algorithm Engineering Memory Processor FPGA IO Circuit Software IP Employ a development platform that handles these pieces

12 Benefits of Algorithm Engineering Reduce development time Lowers time to functional prototype Improve IP quality Allows for more testing and optimization with realworld I/O Analog I/O Digital I/O FPGA VHDL IP Analog I/O Digital I/O

13 HDL IP PROTOTYPING PLATFORMS

14 Vendor Evaluation Boards JTAG access to FPGA for programming Variety of specialized and generic IO User must build communication logic and software Standards exist for modular IO circuits VITA 57.1 FMC, Avnet EXP CPU JTAG Memory FPGA Xilinx Video Starter Kit IO

15 Hardware Co-Simulation Platforms Facilitates programming and communication between CPU and FPGA Data rates may not match real-world performance CPU PCI, USB, FPGA Connectivity to memory and IO can be difficult

16 Programmable FPGA-based Measurement Products Ideal architecture for Algorithm Engineering approach Memory Variety of fixed and modular IO circuit options CPU PCI, PXI, FPGA FMC, IO Circuit Key differences lie in communication & integration software

17 Example Architecture IO Adapter Module DRAM FPGA DRAM PXI to CPU

18 HDL IP Algorithm Engineering CRITICAL COMPONENTS

19 Critical Component 1. IP Packaging for Reuse 2. Abstracting the Glue 3. High Level Communication Software

20 1. IP Packaging for Reuse Integrating IP into development hardware must be seamless Through packaging IP with metadata we can simplify this process Metadata ensures proper signal connections and adequate FPGA resources Example specs: SPIRIT IP- XACT and LabVIEW CLIP IP Component Definition Synthesis Files Simulation Files Metadata

21 2. Abstracting the Glue DRAM FPGA DRAM Controller FIFO Interface PCI DMA Controller FIFO Interface IP Under Test Sync. ADC Sample Interface ADC Interface State Machine ADC

22 DMA Abstraction = 66 Pages, ~4000 lines

23 3. High Level Communication Software Abstract and simplify required data movement and visualization Allow developer to focus on IP Load image Setup transfer from FPGA Receive data from FPGA Decode into RAW format Processing IP Format image for display Setup transfer to FPGA Receive data on FPGA Display or log results

24 Summary of Required Components IP Packaging for Reuse Abstracting the Glue High Level Communication Software

25 Example 1: Synthetic Aperture Radar Memory CPU Data Visualization FPGA Radar Signal Processing HDL IP Transducer Sampling Circuit

26 Example 2: Gigabit Ethernet Simulator Develop and test customized protocols Fault injection Channel simulation Image: Prevas AB, Sweden.

27 Summary & References Save time in the design by Using algorithm engineering when evaluating logic testing with real-world I/O early in the design Using high-level software platform Appling flexible COTS hardware architecture Xilinx Video Starter Kit Vita 57 FMC LabVIEW FPGA IP-XACT NI FlexRIO Visit our booth to learn more about connecting FPGA to real-world I/O