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THIS SPEC IS OBSOLETE Spec No: 40-00047 Spec Title: 7C270 / 7C276 PROM

1 THIS SPEC IS OBSOLETE Spec No: Spec Title: 7C270 / 7C276 PROM Programming Spec Sunset Owner: Dennis Samaniego (dsi) Replaced by: NONE

2 Title: 7C270 / 7C276 PROM Programming Spec 1. PURPOSE/SCOPE 1.1. Purpose: 1.2. Scope: This document specifies all information necessary to program the CY7C270/6 Processor Intelligent PROMs. This programming spec serves as complete documentation of the DC and AC programming characteristics of the devices and the required programming algorithms. 2. RESPONSIBILITIES 2.1. Design Engineering is responsible for defining this spec Product Engineering and Test Engineering are responsible for ensuring conformance of this spec. 3. REFERENCE DOCUMENTS C270/5/6 Design Feasibility and Objective Spec Quality Records Element 4. MATERIALS: N/A. 5. EQUIPMENT: N/A. 6. SAFETY: N/A 7. CRITICAL REQUIREMENTS SUMMARY: N/A 8. OPERATING PROCEDURES AND RESPONSIBILITIES 8.1. Functional Description Document No Rev. *D Page 1 of 18

3 The CY7C270/6 are high-speed, 16Kx16 PROMs, manufactured using 0.8 micron CMOS EPROM technology. The CY7C270, packaged in a 44 lead chip carrier, is a registered Processor Intelligent PROM with userprogrammable features that include an on-chip counter to support processor bursts, a programmable address latch, and polarity programmable chip selects and output enable. The CY7C276 is an asynchronous version of the CY7C270 that does not include the on-chip counter and address latches CY7C270 Description The CY7C270 is offered in 44 lead HC, LCC and PLCC packages. The device is intended to interface with a variety of microprocessors with as little "glue" logic as possible. For processors that burst, on-chip address advancement logic is included for faster access times. Three separate, linear, address advancement ranges are available for the user, 2-bit, 4-bit, and 8-bits wide, to support a variety of processors. The user can also program the part to support the Intel 80486, which bursts in a nonsequential pattern. Selection of the type of address generation required is accomplished with programmable fuses. Additional programmable features are included to assist in tailoring the PROM to particular microprocessors. There are two modes of operation in the CY7C270. In the first, "Registered Mode", the CY7C270 is a clocked device with an address register on the input that will capture an address, or advance the address counter, on the rising edge of clock (CLK). In the second, "Latched Mode", addresses are stored into an address latch controlled by the latch enable (LEB) input. As long as LEB is low, the output of the latch follows its input. The low to high transition of LEB closes the latch. Data from the PROM is available after the address is stabilized or after the latch is opened, whichever is later. A burst access is activated if the advance (ADVB) signal is sampled low at clock rise while LEB is high. The polarity of the three chip selects and the output enable are also user programmable. The on-chip decoding of the chip selects allows the user to select from as many as eight banks of PROMs without requiring external decoding circuitry. Document No Rev. *D Page 2 of 18

4 CY7C270 Block Diagram Document No Rev. *D Page 3 of 18

5 CY7C276 Description The CY7C276 is a straight asynchronous PROM that is offered in 44 lead HC, LCC and PLCC packages. The CY7C276 behaves like a typical PROM where data is available some time after the address is stabilized. Burst accesses are not supported, and the LEB, ADVB, and CLK inputs are eliminated. The polarity of the three chip selects and the output enable is programmable CY7C276 Block Diagram Document No Rev. *D Page 4 of 18

6 CY7C270/6 Pinout Diagrams VPP PGM VFY D13 D14 D15 CLK ADVB VSS VCC LEB CS2 CS1 CSO D A13 D A12 D A11 D A10 D A9 7C270 VSS VSS VCC VSS D A8 D A7 D A6 D A D3 D2 D1 D0 OE VSS A0 A1 A2 A3 A4 VPP PGM VFY D13 D14 D15 VSS VCC VSS VCC VSS CS2 CS1 CSO D A13 D A12 D A11 D A10 D A9 7C276 VSS VSS VCC VSS D A8 D A7 D A6 D A D3 D2 D1 D0 OE VSS A0 A1 A2 A3 A4 Document No Rev. *D Page 5 of 18

7 8.2. Programming Programming Overview Programming the CY7C270/6 changes the default "0" state of memory cells to a programmed "1" state through hot-electron (EPROM) programming. Both devices have a memory array of 16K words of 16-bits each. In addition, both include a variety of programmable configurations. The configurable options on the CY7C270 include selecting the type of burst address generation desired from a choice of 2-bit, 4-bit, or 8-bit linear bursts or 2-bit Intel burst (the default is no burst). The CY7C270 also allows the selection of registered or latched mode of address input. The CY7C270 and CY7C276 both allow the user to configure the polarity of the each of the three chip select inputs as well as the single output enable pin Programming Control Pins Mode Table Both devices use three pins to control programming. These pins include a VPP pin which sustains the high voltage necessary for programming, a PGMB pin that enables programming of the data on the I/O pins, and a VFYB pin that allows verification of the programmed word directly on the outputs. The devices always program and verify 16-bit words. There are three distinct modes of operation available while programming the device. The first, Program Inhibit, is entered when both PGMB and VFYB are high. Program Inhibit disables internal programming circuits, even though high voltage is present on the VPP pin. Program Enable, entered when PGMB is taken low while VFYB is held high, initiates programming of a word in the device. Program Verify, entered with VFYB low and PGMB high, allows direct verification of the word being programmed. Mode VPP PGMB VFYB D0-D15 Program Inhibit Vpp Vihp Vihp HI-Z Program Enable Vpp Vilp Vihp Vihp/Vilp Program Verify Vpp Vihp Vilp Vohp/Volp Illegal Mode Vpp Vilp Vilp To program the devices, the VPP pin is first taken to high voltage, with the PGMB and VFYB pins both held HIGH. This powers up the internal programming circuitry and converts both the input and output paths to fully Document No Rev. *D Page 6 of 18

8 asynchronous paths, meaning registered input and output paths are disabled until the VPP pin is returned low. While PGMB and VFYB are held high, data is applied to the I/O pins D0- D15. Taking PGMB low while holding VFYB high programs the data into the device, and taking VFYB low while holding PGMB high verifies the location being programmed Programming the Memory Array The memory array is programmed by directly addressing one of the words in the device. The address is applied to the address inputs A0-A13 and must be held steady while programming and verifying the location. The 16-bit word being programmed into the array is applied to the I/O pins D0-D15 and Program Enable mode is entered. The programmed location is verified on D0-D15 by entering Program Verify mode Programming the Configuration Fuses The architecture of the CY7C270/6 is set by programming one control word into the device. The bits in the control word correspond to specific configuration bits (programmable fuses) in the device. Programming the control word is accomplished in a manner similar to programming the memory array. The only difference is that address input A2 must be held at the same high voltage level as the VPP pin when programming the control word. Programming is accomplished identically to memory array programming, except the data applied and verified on the I/O pins is the control word Configuration Mode Table Mode VPP PGMB VFYB A2 D0-D15 Program Inhibit Vpp Vihp Vihp X HI-Z Program Control Word Vpp Vilp Vihp Vpp CWORD Verify Control Word Vpp Vihp Vilp Vpp CWORD Programmable Fuse Locations Each programmable element has a PROM bitmap location. For the memory array, which is organized as words of 16-bits each, there are programmable fuses. The fuses are addressable in sets of sixteen using address pins A0-A13 to address a specific 16-bit word, and I/O pins D0-D15 to access each bit in the word. The PROM bitmap locations are 0 to 3fff (hex), where location 0 is word 0, location 1 is word 1, and so on. Document No Rev. *D Page 7 of 18

9 If the bitmap is represented according to the Intel 16-bit hex format, then each word in the bitmap should be stored as LSB-MSB, where LSB is the Least Significant Byte and MSB is the Most Significant Byte. This results in the following organization in the buffer memory: 00000H: LSB0-MSB0 LSB1-MSB1 LSB2-MSB H: LSB8-MSB8 LSB9-MSB Within the LSB and MSB, the bits of the byte are organized from most significant BIT to least significant BIT: MSB: D15 D14 D13... D8 LSB: D7 D6 D5 D0 In the PROM bitmap, the configuration fuses are grouped into a control word (CWORD) which is stored at bitmap location 4000 (hex). Each bit in the control word corresponds to a specific fuse in the configuration. Again, each word should be stored as LSB-MSB, and the bits should be organized as most significant BIT to least significant BIT PROM Bitmap Locations Programmer Address Decimal Programmer Address Hex fff 4000 Programmer Memory CY7C270/6 DATA... DATA CWORD The CWORD is used to configure the burst address generation on the CY7C270 and the chip select and output enable polarity on the CY7C270/6. On the CY7C270/6, bit D0 of CWORD sets the output enable (OE) polarity, and bits D12-D14 correspond to chip select CS0-CS2 polarity. Setting these bits to "0" in the control word will set the corresponding pin polarity to active low (the default), while setting these bits to "1" sets the corresponding pin polarity to "active high". Document No Rev. *D Page 8 of 18

10 On the CY7C270, bit D15 of CWORD set to "1" enables burst mode address generation and bits D1 and D2 specify the type of address generation desired. If D1 and D2 are both "0", address generation will be according to Intel burst order (the default), while if D1 is "1" and D2 is "0", 2-bit linear count is enabled. If D1 is "0" and D2 is "1", 4-bit linear count is enabled, and finally, if both D1 and D2 are "1", 8-bit linear count is enabled. The final configuration bit on the CY7C270 is set by D3, which specifies registered or latched mode of operation. If D3 is set to "0", the device operates in registered mode (the default), while if D3 is set to "1", the device is programmed to operate in latched mode. The tables below illustrate the control words for the devices Control Words for the CY7C270/6 Note that bit D3 in the control word for the 7C276 MUST be set to "1". Failure to do this will result in the wrong configuration for this device. Document No Rev. *D Page 9 of 18

11 Bit Description of CWORD Control Option Bit Control Word Programmed Level Function OE 270/6 D 0 0 = Default 1 = Programmed OE Active LOW OE Active HIGH C 1 C only R/L 270 only D 2, D 1 D 3 00 = Default 01 = Programmed 10 = Programmed 11 = Programmed 0 = Default 1 = Programmed Intel bit Counter 2-Bit Linear Counter 4-Bit Linear Counter 8-Bit Linear Counter Registered Mode Latched Mode CS 0 270/6 D 12 0 = Default 1 = Programmed CS 0 Active Low CS 0 Active High CS 1 270/6 D 13 0 = Default 1 = Programmed CS 1 Active Low CS 1 Active High CS 2 270/6 D 14 0 = Default 1 = Programmed CS 2 Active Low CS 2 Active High BE 270 only D 15 0 = Default 1 = Programmed No Burst Burst (follow C 1 C 0 ) Signature Mode The 7C270 includes a signature mode that allows a programmer to identify the device being programmed. The signature code is organized as two words, the first word indicating the manufacturer as Cypress, and the second indicating the identity of the device. The signature code is accessed by taking A9 to high voltage, while holding all other input-only pins low (with the obvious exception of the VCC pins). The code 0034 (hex) will appear on the output pins. Toggling the A0 pin from low to high and subsequently holding A0 high, will cause the device ID to appear on the output pins Table of Signature Codes Device Mfg Code Device Code CY7C (hex) 0013 (hex) Document No Rev. *D Page 10 of 18

12 Waveforms for Accessing the Signature Codes Programming DC Parameters Parameter Description Unit Min Max Vpp Programming Voltage V Vccp Supply Voltage V Ipp Programming Supply Current ma 50 Icc Supply Current ma 200 Vihp Input HIGH V 3.0 Vilp Input LOW V 0.4 Vohp Output HIGH V 2.4 Volp Output LOW V 0.4 TA Ambient Temperature C Document No Rev. *D Page 11 of 18

13 Programming AC Parameters Parameter Description Unit Min Max tr tf Vpp rise time Vpp fall time us us tas tah Address setup to PGMB, VFYB Address hold from PGMB, VFYB us us tds tdh Data setup to PGMB Data hold time from PGMB us us tdv tdz VFYB to data valid VFYB to tristate us us tvps Vpp setup to PGMB, VFYB us 2.0 tvph Vpp hold from PGMB, VFYB us 2.0 tcs CEB setup to PGMB (273 only) us 2.0 tos Outputs setup to VFYB us 2.0 tpp(array) PGMB (program) pulse width us 200 tpp(config) PGMB (program) pulse width ms 10.0 tvp VFYB (verify) pulse width us 12.0 tps PGMB to VFYB us 2.0 tvs VFYB to PGMB us 2.0 tp Power Up/Down ms Document No Rev. *D Page 12 of 18

14 Memory Array Programming Waveforms Document No Rev. *D Page 13 of 18

15 Memory Array Programming Algorithm Flowchart Document No Rev. *D Page 14 of 18

16 Configuration Programming Waveforms Configuration Programming Algorithm 9. QUALITY REQUIREMENTS: N/A. 10. RECORDS Storage location and retention period for records is specified in the spec # , Quality Records Element. Document No Rev. *D Page 15 of 18

17 11. PREVENTIVE MAINTENANCE: N/A. 12. POSTING SHEETS/FORMS: N/A Document No Rev. *D Page 16 of 18

18 Appendix 1 (This page is not yet in use. Replace this text with your own content. Do not delete this page.) Document No Rev. *D Page 17 of 18

19 Document History Page Document Title: 7C270 / 7C276 PROM Programming Spec Document Number: Rev. ECN No. Issue Date Orig. of Description of Change Change ** /07/91 CSN New Release *A /26/93 CSN Delete 272, 273, 275 Make 276 (mark option) compatible with 270 *B /24/95 HVN Converted the spec to ISO format CY7C270/6 Pinout Diagrams, changed pin 3 of 7C276, VCC to VSS. Title: added CY to device names. *C /23/96 DCon Automated conversion from WordPerfect to Word for Windows 6.0c *D SEE ECN DSI Obsolete specification. Distribution: , OREGON, CTI Posting: None Document No Rev. *D Page 18 of 18

Rev. No. History Issue Date Remark

Preliminary 512K X 8 OTP CMOS EPROM Document Title 512K X 8 OTP CMOS EPROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 17, 1998 Preliminary 1.0 Change CE from VIL to VIH