8051 I/O and 8051 Interrupts

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1 8051 I/O and 8051 Interrupts Class 7 EE4380 Fall 2002 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas

2 Agenda 8051 I/O Interfacing Scanned LED displays LCD displays Keypads 8051 Interrupts IVT, ISR Interrupt enable and priority External interrupts 19-Sep-02 2

3 Scanned 7-seg LED display LED displays are power-hungry (10ma per LED) Pin-hungry (8 pins per 7- seg display) Scanned displays Only one 7-seg display is enabled at a given time Inputs a-h are connected together respectively Total Port pins needed 8 + # of digits for this figure a h D3 Vcc D2 D1 D0 19-Sep-02 3

4 Scanned 7-seg display Algorithm to display a 4 digit value. The scanning frequency should be high enough to be flicker-free At least 30HZ Time one digit is ON 1/30 seconds Higher values give better flicker reduction (60Hz) start: again: disable [D3:D0] enable D3 [a:h] pattern for Digit3 delay disable D3. Enable D2 [a:h] pattern for Digit2 delay disable D2. Enable D1 [a:h] pattern for Digit1 delay disable D1. Enable D0 [a:h] pattern for Digit0 delay disable D0 Goto again 19-Sep-02 4

5 Keypad Interfacing 16 Keys arranged as 4x4 Algorithm: Drive a 0 on a row Read all the columns If any key had been pressed, its column will be 0, else 1 Keep repeating in a loop for each successive row Example: Switch 4 is pressed R1 0, C1:C4 = 1111 R2 0, C1:C4 = 0111 Switch 2 is pressed R1 0, C1:C4 = 1101 Vcc R R2 8 9 A B R3 C D E F R4 C1 C2 C3 C4 R1 R2 R3 R4 C1 C2 C3 C4 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P Sep-02 5

6 LCD Interfacing LCDs are cheap and easy way to get text display for an embedded system Various configurations (1x20 to 8x80), starting from $5 Graphics LCDs are also available Intelligent LCDs have internal ASCII decoders, Character Generators and LCD control circuitry Some also have custom character generation capacity User defined character RAM Program this RAM with the character pattern Then use it like ordinary ASCII characters Usually MSB decides between std ASCII and custom characters 19-Sep-02 6

7 Alphanumeric LCD Interfacing Pinout 8 data pins D7:D0 RS: Data or Command Select RW: Read or Write E: Enable (Latch data) Vee : contrast control RS=0 Command, RS=1 Data RW=0 Write RW=1 Read E=1 Enable (H-L pulse) LCD Command Codes Mfrs. Data sheet Clear screen, move cursor, shift display 8051 P1.0 P1.7 P3.3 P3.5 D0 D7 RS LCD RW Vee E Vcc 19-Sep-02 7

8 Alphanumeric LCD - Algorithm Algorithm mov A, command call cmd delay mov A, another_cmd call cmd delay mov A, # A call data delay mov A, # B call data delay. Command and Data Write Routines cmd: mov P1, A ;A has the cmd word clr P3.3 ;RS=0 for cmd clr P3.4 ;RW=0 for write setb P3.5 ;H->L pulse on E clr P3.5 ret data: mov P1, A ;A is ascii data setb P3.3 ;RS=1 data clr P3.4 ;RW=0 for write setb P3.5 ;H->L pulse on E clr P3.5 ret 19-Sep-02 8

9 Alphanumeric LCD - Algorithm Busy checking: After a read from the LCD, the D7 will contain the busy flag. Check this before sending any new command to the LCD, or use a big delay. ready: setb P1.7 ;D7 as input clr P3.3 ;RS=0 cmd setb P3.4 ;RW=1 for read again: setb P3.5 ;H->L pulse on E clr P3.5 jb P1.7, again ret 19-Sep-02 9

10 8051 Interrupts What are interrupts? A way to stop the processor from whatever it was doing and make it do another task Why and where do we need them? Service multiple interfaced devices Multi-tasking systems Interrupts in external, two for the timers and one for the serial port 19-Sep-02 10

11 Polling Vs Interrupts Polling: CPU monitors all served devices continuously, looking for a service request flag Whenever it sees a request, it serves the device and then keeps polling CPU is always busy with polling doing the while any request loop Interrupts If and when a device is ready and needs attention, it informs the CPU CPU drops whatever it was doing and serves the device and then returns back to its original task CPU is always free, when not serving any interrupts 19-Sep-02 11

12 Interrupt Service Routine CPUs have fixed number of interrupts Every interrupt has to be associated with a piece of code called Interrupt Service Routine, or ISR. If interrupt-x is received by CPU, the ISR-x is executed CPU architecture defines a specific code address for each ISR, which is stored in the, Interrupt vector Table (IVT) ISRs are basically subroutines, but they end with the RETI, instruction instead of RET When an interrupt occurs, the CPU fetches its ISR code address from the IVT and executes it. 19-Sep-02 12

13 Interrupt Execution 1. CPU finishes the instruction it is currently executing and stores the PC on the stack 2. CPU saves the current status of all interrupts internally 3. Fetches the ISR address for the interrupt from IVT and jumps to that address 4. Executes the ISR until it reaches the RETI instruction 5. Upon RETI, the CPU pops back the old PC from the stack and continues with whatever it was doiing before the interrupt occurred 19-Sep-02 13

14 8051 Interrupts Vendors claim 6 hardware interrupts. One of them is the reset. So only 5 real interrupts in the Clones may differ. Two external interrupts INT0 and INT1, two timer interrupts TF0 and TF1 and one serial port interrupt S0 Interrupts can be individually enabled or disabled. This is done in the IE (Interrupt Enable Register) External interrupts (INT0 and INT1) can be configured to be either level or edge triggered. 19-Sep-02 14

15 IVT Each Interrupt has 8 bytes for its ISR. If ISR is too big to fit in 8bytes, then use a ljmp Interrupt ROM Location Pin rom_start: ORG 0 LJMP main_code ORG 13H Reset INT0 0000H 0003H 9 P3.2 int1_vec: main_code: ;. LJMP int1_isr ORG 30H ;bla bla TF0 INT1 TF1 000BH 0013H 001BH P3.3 int1_isr: ;bla bla S0 0023H 19-Sep-02 15

16 IE Register EA = 0, disable all interrupts EA -- ET2 ES ET1 EX1 ET0 EX0 Other bits if set to 1, enable the corresponding interrupt, if set to 0, disable it. EX0 = enable INT0 ET0 = enable Timer0 EX1 = enable INT1 ET1 = enable Timer1 ES = enable serial port interrupt ET2 = (for 8052 clones only) enable Timer2 19-Sep-02 16

17 Simple Example INT1 pin is connected to a switch that is normally high. Whenever it goes low, an LED should be turned on. LED is connected to port pin P1.3 and is normally OFF org 0H ljmp MAIN org 13H ;INT1 ISR INT1_ISR: setb P1.3 ;turn on LED mov r3, #255 BACK: djnz r3, BACK ;keep the led ON for a while clr P1.3 ;turn OFF the LED RETI ;use RETI, ***NOT RET*** org 30H MAIN: mov IE, # B ;enable INT1, EA=1, EX1=1 HERE: sjmp HERE ;stay here until interrupted end 19-Sep-02 17

18 External Interrupts INT0 and INT1 Level triggered : a low level on the pin causes interrupt Default mode Edge triggered : a high-to-low transition on the pin causes interrupt Configuration in TCON register (IT1) TCON.2 = 1 INT1 is edge triggered (IT0) TCON.0 = 1 INT0 is edge triggered IE0 (TCON.1) and IE1 (TCON.3) In edge triggered mode, if interrupt INTx occurs, the CPU sets the IEx bit, which is cleared only after a RETI is executed Prevents interrupt within interrupt Setup and Hold times for Edge triggered external interrupts One machine cycle each 19-Sep-02 18

19 Interrupt Priority Default Priority INT0 > TF0 > INT1 > TF1 > S0 The ISR of an interrupt can be interrupted by a higher priority interrupt. The Default Priority can be changed by programming the IP register PT2 PS PT1 PX1 PT0 PX0 To set higher priority to an interrupt, set its bit in IP to 1 If more than one 1 in IP, the default priority is used for all the interrupts that have 1 in IP 19-Sep-02 19

20 Next Class 8051 Timers Timers and Interrupts Applications 19-Sep-02 20

Interrupts. EE4380 Fall 2001 Class 9. Pari vallal Kannan. Center for Integrated Circuits and Systems University of Texas at Dallas

Interrupts. EE4380 Fall 2001 Class 9. Pari vallal Kannan. Center for Integrated Circuits and Systems University of Texas at Dallas 8051 - Interrupts EE4380 Fall 2001 Class 9 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas Polling Vs Interrupts Polling: MCU monitors all served devices continuously,