Comparing Constraint Behavior to Determine Equivalency TAU Sonia Singhal Loa Mize Subramanyam Sripada Szu-Tsung Cheng Cho Moon

Transcription

1 Comparing Constraint Behavior to Determine Equivalency TAU 2011 Sonia Singhal Loa Mize Subramanyam Sripada Szu-Tsung Cheng Cho Moon 1

2 Constraints Communicate design requirements and intent to implementation and analysis tools set_input_delay clock CLK1 -setup [get_ports in1] create_clock name CLKA period 10 edges {0 5 10} [get_port clka] create_clock name CLKB period 50 edges { } [get_port clkb] MCP 2 set_output_delay 1.5 clock CLK1 setup [get_ports out1] set_multicycle_path 2 -from [get_pins ff1/cp - to [get_pins ff2/d] set_false_path -from CLKA to CLKB set_false_path -from CLKB to CLKA Constraint file size can be more than a few gigabytes 2

3 Motivation Pair-wise comparison not enough Constraints in different forms can have the same effect compressed vs. non-compressed constraints set_false_path from A to Z set_false_path from B to Z vs. set_false_path from {A B} to Z - set_false_path, set_case_analysis, set_disable_timing, set_clock_group - Different syntax and representation - Different propagation effects on the netlist - Similar effect (disable) on the design Constraints change form during the flow Implementation and Analysis tools Experts know which form has potential benefits in runtime and faster timing closure 3

4 Motivation Constraints overlap and override inv ra rx and rb ry set_multicyle_path 3 \ through [get_pins inv/z] set_multicycle_path 2 \ -through [get_pins and/z] Behavior Not Equivalent set_multicycle_path 3 \ from [get_pins ra/cp] set_multicycle_path 2 \ through [get_pins and/z] Partially overridden, partially invalid constraints along with constraint precedence cannot be matched simply by comparing the netlist objects of the constraints 4

5 Motivation Netlist optimizations 2 netlists, same constraint-set ra u1 rx ra u1 rx u2 u3 rb ry rb ry set_false_path from rb through u1/z? set_false_path from rb through u1/z Netlist optimizations have led to bad chips despite no changes in logical functionality and constraints There is a strong need to compare constraint behaviors (effects of constraints on designs) 5

6 Timing relationships Constraint representation for a set of paths ra rb and rx ry create_clock period 10 name [get_ports } set_multicyle_path 2 through [get_pins inv/z] set_false_path -through [get_pins and/b] Timing start-point Timing end-point Launch clock Capture clock Min/ Max/ Rise/ Fall State * rx/d (r) (r) All MCP(2) ra ry/d (r) (r) All MCP(2) rb ry/d (r) (r) All FP We create a minimal set of Timing Relationships necessary to describe the design and its constraints. 6

7 Constraint Comparison Algorithm Three Pass Approach Compares the timing relationships of a set of paths across 2 netlist-constraint sets using a multi-pass gradual refinement method: Pass 1: Fast method to detect mismatches of all paths reaching an endpoint. Pass 2: Main method to detect matches/mismatches for all paths between a startpoint-endpoint pair. Pass 3: Detailed method to remove remaining potential mismatches involving reconvergence points 7

8 Pass 1 Compare the effect of constraints on timing path endpoints between 2 netlist/constraint pairs Check same state for each endpoint timing relationship Value Exception state - None - False - Cycle relationship - set_min_delay/set_max_delay value Key - Launch clock and clock edge - Timing Endpoint - Capture clock and clock edge - Endpoint data rise/fall - Min and Max path Fast - Single bread-first traversal on netlist. Only endpoints with multiple matching timing relationships need further analysis 8

9 Pass 1 Example inv1 First constraint set ra inv2 rx set_false_path from [get_pins ra/cp] set_false_path from [get_pins rb/cp] set_multicycle_path 2 from [get_pins rc/cp] rb ry Second constraint set rc and rz set_false_path from [get_pins ra/cp] set_multicyle_path 2 from [get_pins rb/cp] set_false_path from [get_pins rc/cp] Timing start-point Timing endpoint Launch Clock Capture Clock Min/Max/ Rise/ Fall 1 st set s state 2 nd set s state Pass1 Result * rx/d (r) (r) All FP FP Match * ry/d (r) (r) All FP MCP Mis-match * rz/d (r) (r) All FP, MCP (2) FP, MCP (2) Needs further analysis 9

10 Pass2 Compare the effect of constraints on timing path between startpoint-endpoint pairs across 2 netlist/constraint pairs Check same state for each startpoint-endpoint pair s timing relationship Value Exception state - None - False - Cycle relationship - set_min_delay/set_max_delay value Key -Timing Startpoint - Launch clock and clock edge - Startpoint data rise/fall - Timing Endpoint - Capture clock and clock edge - Endpoint data rise/fall - min and max path Each inconclusive endpoint left over from Pass1 is analyzed Data gathered for all startpoints to the endpoint to be analyzed and cleared before proceeding to next endpoint Highly parallelizable 10

11 Pass 2 Example rb rc inv2 and ry rz First constraint set set_false_path from [get_pins rb/cp] set_multicycle_path 2 from [get_pins rc/cp] Second constraint set set_multicyle_path 2 from [get_pins rb/cp] set_false_path from [get_pins rc/cp] Timing startpoint Timing endpoint Launch clock Capture clock Min/ Max/ Rise/ Fall 1 st set s state 2 nd set s state Result rb/cp rz/d (r) (r) All FP MCP Mismatch (2) rc/cp rz/d (r) (r) All MCP (2) FP Mismatch 11

12 Pass 3 Compare multiple timing relationships due to reconvergent points ra mux rb First constraint set set_multicycle_path 2 through mux/a Second constraint set set_multicycle_path 2 -through mux/b Timing startpoint Timing endpoint Reconvergent Points 1 st Set State 2 nd Set State Result ra/cp rb/d mux/a MCP(2) Cycle (1) Mismatch ra/cp rb/d mux/b Cycle(1) MCP(2) Mismatch 12

13 Block constraints vs Top Constraints Bottom-up or Top-down design flow validation Chip_Top set_input_delay 2.75 Input -clock CLK1 -setup [get_ports in1] Signal? create_clock name CLKA period 10 edges Clock {0 5 10} [get_port clka] Signals? create_clock name CLKB period 50 edges { } [get_port clkb] USB core False clock relationship? MCP? MCP 2 Output Signal? set_output_delay 1.5 clock CLK1 setup [get_ports out1] set_multicycle_path 2 -from [get_pins ff1/cp - to [get_pins ff2/d] set_false_path -from CLKA to CLKB set_false_path -from CLKB to CLKA Bottom-up flow: Constraints Block-level are constraints propagated are created up to top level User Block wants is optimized to ensure alone that then top-level integrated constraints with chip are complete 13

14 Results Single netlist and 2 constraints Design #instances (M) Single Core (sec) 4 cores (sec) X factor Single Core (GB) 4 cores (GB) D D D D D D D D

15 Results Block Constraints vs top Constraints Design #instances in Top (M) #instances in Block (M) Runtime (CPU Sec) Top1/Block Top1/Block Top2/Block Top2/Block Top3/Block Top3/Block

16 Summary Advantages of our approach Efficient solution that compares two constraint behaviors Compare compressed vs. non-compressed exceptions Compares different constraints with similar affects (false paths vs. set_case_analysis) Accounts for precedence rules Easily parallelizable Timing relationships help report mismatches in form of original user constraints Many applications 16

17 Thank You Questions 17