My Second FPGA for Altera DE2-115 Board
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1 My Second FPGA for Altera DE2-115 Board 數位電路實驗 TA: 吳柏辰 Author: Trumen
2 Outline DE2-115 System Builder ModelSim-Altera 2
3 DE2-115 System Builder 3
4 Introduction to DE2-115 System Builder (1/2) This section describes how users can create a custom design project on the DE2-115 board by using DE2-115 Software Tool DE2-115 System Builder. The DE2-115 System Builder is a Windows based software utility, designed to assist users to create a Quartus II project for the DE2-115 board withim minutes. 4
5 Introduction to DE2-115 System Builder (2/2) The generated Quartus II projects files include: Quartus II Project File (.qpf) Quartus II Setting File (.qsf) Top-Level Design File (.v) Synopsis Design Constraints file (.sdc) Pin Assignment Document (.htm) 5
6 General Design Flow Start Launch DE2-115 System Builder Create New DE2-115 System Builder Project Generate Quartus II Project and Document Add User Design/Logic Launch Quartus II and Open Project.qpf.qsf.v.sdc.htm Compile to generate.sof Configure FPGA End 6
7 Launch DE2-115 System Builder DE2_115_tools\DE2_115_system_builder.exe 7
8 Input Project Name 1 8
9 System Configuration 1 9
10 GPIO Expansion 1 10
11 HSMC Expansion 1 11
12 Project Setting Management Users can save the current board configuration information into a.cfg file and load it to the DE2-115 System Builder
13 Project Generation When users press the Generation buttion, the DE2-115 System Builder will generate the corresponding Quartus II files and documents. No. Filename Description 1 exp2_rsa.v Top level verilog HDL file for Quartus II 2 exp2_rsa.qpf Quartus II Project File 3 exp2_rsa.qsf Quartus II Setting File 4 exp2_rsa.sdc Synopsis Design Constraints file for Quartus II 5 exp2_rsa.htm Pin Assignment Document 13
14 THDB-HTG Board This figure illustrates how the THDB-HTG board is connected to the DE2-115 board. Be sure to turn off the power whenever you connect or disconnect the THDB-HTG board!! 14
15 exp2_rsa.htm (1/2) DE2_115_User_manual.pdf 4.8 Usiing the Expansiion Header 15
16 exp2_rsa.htm (2/2) THDB-HTG_V1.0.3.pdf 1-6 Expansion Prototype Connectors 16
17 exp2_rsa.sdc Remember to modify the.sdc file. clock, i/o delay, etc. create_clock -period 1000 [get_ports clk] derive_clock_uncertainty set_input_delay 0 -clock clk [all_inputs] set_output_delay 0 -clock clk [all_outputs] 17
18 Can't place multiple pins? If you try to assign pins by yourself, this error message may occur. How to fix it? 18
19 1 2 19
20 1 20
21
22 1 22
23 ModelSim-Altera 23
24 Introduction to ModelSim (1/5) ModelSim is a simulation and verification tool for VHDL, Verilog, SystemVerilog, and mixed language designs. The following diagram shows the basic steps for simulating a design in ModelSim. Create a working library Compile design files Load and Run simulation Debug results 24
25 Introduction to ModelSim (2/5) Creating the Working Library In ModelSim, all designs are compiled into a library. You typically start a new simulation in ModelSim by creating a working library called "work," which is the default library name used by the compiler as the default destination for compiled design units. 25
26 Introduction to ModelSim (3/5) Compiling Your Design After creating the working library, you compile your design units into it. The ModelSim library format is compatible across all supported platforms. You can simulate your design on any platform without having to recompile your design. 26
27 Introduction to ModelSim (4/5) Loading the Simulator with Your Design and Running the Simulation With the design compiled, you load the simulator with your design by invoking the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). 27
28 Introduction to ModelSim (5/5) Debugging Your Results If you don t get the results you expect, you can use ModelSim s robust debugging environment to track down the cause of the problem. 28
29 ModelSim-Altera Altera Quartus II software allows the user to launch Modelsim-Altera simulator from within the software using the Quartus II feature called NativeLink. It facilitates the process of simulation by providing an easy to use mechanism and precompiled libraries for simulation. 29
30 Setting up EDA Tool Options
31
32 Setting Up the Simulation
33
34
35 1 35
36 Before Simulation We should compile our design before simulation to generate a simulation snapshot. "Start Analysis & Elaboration" is enough, and it takes much less time than "Start Compilation". And then we can run the simulation. 36
37 Issues of Working Directory The working directory of ModelSim-Altera is under "(project directory)/simulation/modelsim", so be careful of setting the directory of input data in the testbench. 37
38
39
40 Congratulation! Be sure ModelSim-Altera has found the input data!! 40
41 If There are Something Wrong Your simulation takes a long time and seems it will not stop. The calculated result is incorrect. 41
42 If the Input Date are not Found It is a fake "PASS" 42
43 Change the Time Unit of the Timeline
44 Check the Waveform (1/2)
45 Check the Waveform (2/2) Zoom full Zoom Mode How to see the signals in the design? Just try it! 45
46 The End. Any question?
47 Reference 1. "DE2-115 User manual" by Terasic. 2. "THDB-HTG User Manual" by Terasic. 3. ModelSim Tutorial by Mentor Graphics Corporation. 4. "Getting Started with Quartus II Simulation Using the ModelSim-Altera Software User Guide" by Altera. 47
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