Equivalence Checking for Timing Constraints Subramanyam Sripada March 6, 2014
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1 Equivalence Checking for Constraints Subramanyam Sripada March 6, Synopsys. All rights reserved. 1
2 Agenda Motivation Existing Solutions Multi-pass approach Results Conclusion 2014 Synopsys. All rights reserved. 2
3 Motivation Today s timing constraints (SDC) are quite complex 10M lines of SDC for a 25M instance design Constraint management is a big issue: Different constraints through different stages of the design flow Constraint modifications and optimizations Hierarchical methodology with multiple teams ECOs Large number of modes 2014 Synopsys. All rights reserved. 3
4 Terminology Equivalence of constraints is defined as identical timing characteristics (s, exceptions etc) for each and every path of the design 1-design/2-SDC: Same netlist, two sets of SDC 2-design/2-SDC: Logically equivalent designs can have different timing constraint behavior Block vs top: Constraint correlation between blocks and chip-level Verification of Merged Modes: Verifying correctness of automated or manually merged constraints 2014 Synopsys. All rights reserved. 4
5 Existing Solutions 1. Manual Checking: Manually inspect the constraint/ design changes 2. Structural Checking: Iterative approach based on pairwise comparison of set_case_analysis, s, input/output delays, exceptions, latency, uncertainty, input transition, output load, etc 3. STA: Compare timing slacks 2014 Synopsys. All rights reserved. 5
6 Motivation inv SDC1: set_multicyle_path 3 from [get_pins ra/cp] ra rx Equivalent and SDC2: set_multicycle_path 3 through [get_pins inv/z] rb ry SDC3: set_multicyle_path 3 from [get_pins ra/cp] set_multicycle_path 2 -through [get_pins and/z] Not Equivalent SDC4: set_multicycle_path 3 through [get_pins inv/z] set_multicycle_path 2 through [get_pins and/z] 2014 Synopsys. All rights reserved. 6
7 Multi-Pass Approach Intention to compare timing behavior on each and every path of the design Adaptive multi-pass approach to achieve good performance Gradual refinement to move to higher pass only if ambiguous in previous pass 2014 Synopsys. All rights reserved. 7
8 1-design/2-SDC inv Clk ra Clk rx and rb ry Clk Clk SDC1: set_multicyle_path 2 through [get_pins ra/cp] set_false_path -through [get_pins and/b] SDC2: set_multicyle_path 2 through [get_pins ra/cp] set_false_path -through [get_pins rb/cp] SP Launch EP Capture SDC1 SDC2 Result * Clk (r) rx/d Clk(r) MCP (2) MCP (2) Match * Clk (r) ry/d Clk(r) FP, MCP (2) FP, MCP (2) Ambiguo us ra/cp Clk (r) ry/d Clk(r) MCP (2) MCP (2) Match rb/cp Clk (r) ry/d Clk(r) FP FP Match Pass 1 characteristics: Endpoint matches/ mismatches Pass 2 characteristics: Startpoint matches/ mismatches for given endpoint Path set 2014 Synopsys. All rights reserved. 8 Exception State
9 1-design/2-SDC Re-convergence example SDC1: set_multicycle_path 2 through mux/a ra mux rb SDC2: set_multicycle_path 2 through mux/b SP Launch EP Reconv ergence point Captur e * Clk (r) rb/d * Clk(r) Valid, MCP (2) SDC1 SDC2 Result Valid, MCP (2) Ambiguou s Pass 1 characteristics ra/cp Clk (r) rb/d * Clk(r) Valid, MCP (2) Valid, MCP (2) Ambiguou s Pass 2 characteristics ra/cp Clk (r) rb/d mux/a Clk(r) MCP (2) Valid Mismatch ra/cp Clk (r) rb/d mux/b Clk(r) Valid MCP (2) Mismatch Path set Exception State Pass 3 characteristics Re-convergent points within one {startpoint, endpoint} pair 2014 Synopsys. All rights reserved. 9
10 2-design/2-SDC Object matching done by names custom mapping ra u1 rx ra u1 rx rb u2 ry rb u3 ry set_false_path from rb through u1/z set_false_path from rb through u1/z SP Launch EP Capture SDC1 SDC2 Result * Clk (r) rx/d Clk(r) Valid, FP Valid, FP Ambiguous * Clk (r) ry/d Clk(r) Valid Valid, FP Mismatch ra/cp Clk (r) rx/d Clk(r) Valid Valid Match rb/cp Clk (r) rx/d Clk(r) FP FP Match Pass 1 characteristics Pass 2 characteristics Path set 2014 Synopsys. All rights reserved. 10 Exception State
11 2-design/2-SDC Difficult to handle netlist changes that change the timing paths: Different registers: The extra/missing startpoints (pass 2) and endpoints (pass 1) will be reported as inconclusive or mismatch Different re-convergence points: The set of paths between the startpoint and endpoint can be reported as inconclusive or mismatch Might be alleviated with additional inputs 2014 Synopsys. All rights reserved. 11
12 Block vs Top - Netlist object matching done by names - Clock matching is done by waveform checks ra inv P rx Top SDC: create_ p 10 waveform {0 5} clk set_multicyle_path 2 through [get_pins ra/cp] clk rb inv2 Q ry block Block SDC: create_ p 10 waveform {5 0} clk create_ p 10 waveform {0 5} name clk_virtual set_input_delay 2 - clk_virtual [get_ports {P Q}] set_multicycle_path 2 from [get_ports P] SP Launch EP Capture Top SDC Block SDC Result * clk/ clk_virtua l (r) 2014 Synopsys. All rights reserved. 12 rx/d clk(f), clk MCP (2) MCP (2) Match * clk/ clk_virtua ry/d clk(f) Valid Valid Match l (r) Path set Exception State Pass 1 characteristics
13 Verification of Merged Modes Union of timing characteristics of individual modes vs characteristics of merged mode clka clkb sel 0 1 FF1 FF2 Mode 1 SDC: set_case_analysis 0[get_port SE] Mode 2 SDC: set_case_analysis 1[get_port SE] User Merged SDC: set_false_path from [get_s clkb] to [get_s clka] SP Launch EP Capture SDC1 SDC2 Merged SDC Result * clka (r) FF2/D clka(r) Valid Not present Valid Match * clkb (r) FF2/D clka(r) FP FP FP Match * clka (r) FF2/D clkb(r) Not present Not present Valid Mismatch Pass 1 characteristics * clkb (r) FF2/D clkb(r) Not present Path set 2014 Synopsys. All rights reserved. 13 Valid Valid Match Exception state
14 Comparison to Existing Solutions Manual Checking STA Category Coverage Runtime Memory Required Limited Expensive Not applicable Only critical paths/ endpoints Requires delay calculation Loads one constraint set at a time but keeps timing numbers like arrival times Structural Checking All timing paths, but limited SDC changes No calculation, no enumeration, quite fast Loads multiple designs/ constraint sets at the same time Muti-Pass Approach All timing paths Path enumeration might be needed for a very small portion of the design Loads multiple designs/ constraint sets at the same time 2014 Synopsys. All rights reserved. 14
15 Conclusions Efficient, non-iterative solution that compares two constraint behaviors for either one or two netlists Compare compressed vs. non-compressed exceptions Compare false paths vs. {case analysis, disable timing, groups} Honor exception precedence Compared to STA: Covers full design Runs faster Consumes more memory Is nicely extensible for all constraint equivalence problems Compact set of user-friendly reports based on mismatched constraints and corresponding paths 2014 Synopsys. All rights reserved. 15
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