Verilog Code File Normally this will not have delay information, but it will have fanout (loading) information. Cell Model File

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1 Delay Modeling Verilog Code File Normally this will not have delay information, but it will have fanout (loading) information. Cell Model File Delay Modeling This has delay information but not loading information. It may also attempt to tell the delay calculator the proper method to use. There are many formats; some of them are:- Verilog is shown. However the loading parameters are not standard. Synopsys and Cadence each have proprietary formats which include specialized timing model information. VHDL Initiative Toward ASIC Libraries (VITAL) is an IEEE standard. The Advanced Library format (ALF) is a standard proposed by the Open Verilog International group. Wire Delays Before layout an estimate of the wire delays may be made from a crude layout, or by adding short delays inside a module and longer delays between modules. After layout some quite complex wire delays can be inserted. Delay Calculator This takes the cell delay, wire delay and loading information and converts them to a numerical delay. It usually gives different delays for rising and falling signals. It may give a min and max delay corresponding to a hightemperature and a slow process, or a low-temperature and a fast process. The delay calculator may be part of some simulators. It must be part of a synthesizer. SDF file This saves the output of the delay calculator. The Annotator This merges the SDF delays with the logic from the Verilog and cell-library files. It is often part of the simulator. Comment on Slide 21 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 41 Timing Model Uses Path Searching It is much faster (minutes to months) to check for the excessively long paths by adding up the delays, than to check that the paths long paths can actually be sensitized. trying to find setup-time violations by simulation led to the expression death by simulation. Synthesis For synthesis the SDF files will contain timing assertions. for example: The clock period should be 10 ns. The minimum output pulse width is 5 ns. Adding these assertions is called forward annotation. The synthesizer will try to construct a circuit which will meet the constraints. Verification Timing Model Uses After layout the lead resistance and capacitance may be calculated from their lengths and dimensions. The delay calculator can then calculate delays and add them to the SDF file. This is called back annotation. False paths If certain paths are known to be false, most verifiers will let one remove them from consideration: set_false_path -from Areg -to Breg Comment on Slide 22 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 42

2 Delay Modelling Cell Model File... specify specparam Outcap=8, Incap=6, R_Ramp$a$g=0.2; (a=>g)=(4,3); endspecify g not (g, a);... a tr=# Optional Wire Delays 6 g c b 6 h k Verilog Code File... not1 noty(g,a); nand2 nany(h,b,g); nand2... pany(k,c,g); Delay Calculator Calc for: noty, a g, rising. t = R(Cout+Cload)+tr = 0.2(8+(6+6)) + 4 = 8 Annotator $sdf_annotate Simulator or Synthesizer Standard Delay Format File (CELLTYPE not1 ) (INSTANCE mod1.submod3.noty) (DELAY (ABSOLUTE (IOPATH a g (8) (7)) ) ) Annotated Netlist Propriatory format. Has both logic and delay info. Slide 20 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 43 Timing-Verification and Synthesis vs Timing Model Uses Timing-Verification and Synthesis vs Simulation Timing verification only checks for timing violations, not logic. Usually of setup and hold times. Verification looks only for longest (shortest) paths It assumes the long paths found can be sensitized (propagate a signal change). The longest path Add the register-toregister delays. (=12) This is a setup violation if T clk <12 False paths Suppose c,d,e can never be 1,1,1. Then the path is a false path. If the longest circuit path is false: the synthesizer will prescribe a slower T clk than necessary. the verifier will accuse it of having a setup violations. The Simulator: will not be able to sensitize false paths. will not flag them as setup violations x 1D C1 0 A sensitized path for x. c=1 x #4 #3 x 0 x #2 #2 d=1 But is it really false, or was the simulator just not fed the right input vector? x e=1 #3 x 1D C1 Slide 21 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 44

3 Delay Models Specification by Connection Verilog models For all models one can use either: #(single_delay) i.e #(5) or #5 #(min: typical: max) i.e #(4:5:6) #(rising_delay, falling_delay) i.e #(3, 6) #(rise_min: rise_typ: rise_max, fall_min: fall_typ: fall_max) i.e. #(2:3:4, 4:5;6) One also has #(rising_dly, falling_dly, turn_off_dly) for coming out of tri-state. ;Lumped and distributed delays are put on the line where the module is invoked. Placing something like #5 before each instance is nuisance for modules that are standard cells. Such cells would probably be encapsulated as shown on the right. module not_cell (out, in); input in; output out; not #(0.15, 0.2) (out,in); endmodule Delay Models Path or pin-to-pin delay is done using specify blocks. Specify blocks show timing between module pins. The specify block is put inside the module, but its timing is between the modules input and output pins. This is a useful way to specify timing for standard-cell models. Comment on Slide 23 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 45 Delay Models Specify Blocks The are a separate block inside the module, They are not placed inside an always or initial block. They are for wire signals, not reg. However one can cheat by assigning regx to wirex Parallel connection The signals must be declared the same size on both sides of the delay. input [10:0] a; output [10:0] b; Full connections *> Groups of signals are equated to other groups. The signals groups do not have to be the same size. However do not give timing for some signals of a vector and omit others. You may propagate a Z. Conditional delays specifications may be made conditional. The condition can be almost any logical construct. One can use if but not else. specify if (b & c) ( b => out) = 3; if (~(b & c)) ( b => out) = 4; if ({e,f,g} == 3b 101 ) (e,f,g *> out) = 12; if (out1 out2) (a *> out1, out2) = 3.3; endspecify module cheat(xout, a) input a; output xout; reg xreg; wire a, xout; assign xout=xreg; specify (a => xout)=30; endspecify Full Connection module add(cout,s, a,b,cin); input [4:0] a, b; input cin; output [4:0] s; output cout; specify (a,b *> s[2:0]) =1.2; (a,b *> s[4:3]) =1.5; (cin => cout) = 1.7; endspecify a[7:0] b[7:0] s[4:3] s[2:0] Comment on Slide 24 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 46

4 Delay Model Types Delay Models Delay Model Types 1. Delay by connection 2. Delay by rise/fall min/max 3. Delay by model, RC, Elmore delay 1. Delay Classified by Connection Lumped delay All the delay lumped at the output Distributed delays (gate delay) Delays distributed to each gate. Path delay (Pin-to-pin delay) For pin-to-pin delay in modules Module andor(g, A, B, C, D) input...etc... specify (A => G ) = 7; (B => G ) = 8; (C => G ) = 8; (D => G ) = 9; endspecify A B C D #4 E #5 #6 #2 #3 #7 F G A B C D A B C D Lumped E #5 #6 F and and5(e, A, B); and and6(f, C, D); or #9 or3(g, E, F); Distributed E F #3 and #5 and5(e, A, B); and #6 and6(f, C, D); or #3 or3(g, E, F); assign #5 E = A & B; assign #3 G = E F; assign #6 F = C & D; #9 G G Slide 22 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 47 Module pin-to-pin delay in Verilog Module pin-to-pin delay in Verilog Specify Blocks Uses a specify...endspecify block. It is a separate block inside the module. Circuitry is defined outside that block. Delays are for module:- input pins => output pins. Types Scalar delays Here (min: typical: max) delays were used. Parallel connection Use for arrays Size of output must equal size of input. Full connection *> specifies delays between multiple inputs and multiple outputs. Conditional delays if (a (~b)&c) (a,b,c *> out)=2; There is no else Scalar delays Module andor(g, A, B, C, D) input A,B,C,D; output G; // Module pin-to-pin timing specify (A => G) = (5:7:9); (B => G) = (6:8:10); (C => G) = (6:8:10); (D => G) = (7:9:11); endspecify A B C D // Now define the gates assign G = E (C & D); assign E = A & B; Parallel delay specify (Q => P) = (3:5:7); endspecify Q[0] Q[1] Q[2] Q[3] Q[4] Q[5] Full connection specify (A,B *> G) = 9; A #5 B #5 (C,D *> G,H) = 7; endspecify C #4 D #4 3:4:5 4:5:6 2:3:4 G 5:6:7 1:2:3 6:7:8 E #4 #3 #3 P[0] P[1] P[2] P[3] P[4] P[5] G H Slide 23 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 48

5 Specparam Specparam Specparam are officially defined and used inside the same specify block. However real circuits have cells whose delay is proportional to load and Verilog only allows a fixed delay. That means the delays of every cell instance must be changed according to load. External delay calculations An external program will reach into the Verilog, extract the specparam and send back the load corrected delays. Timing model This delay calculator may use a prop-ramp delay model in which:- Delay = R(C out + C load ) + t fixed Rise time = R_Ramp$i$z(OutCap$z + Cload) + (30:50:70) Fall time = F_Ramp$i$z(OutCap$z + Cload) + (25:45:63) Cload is taken from the InCap specparam of the next stage(s) Min, typ, or max numbers will be selected for the final calculation. Interacting with the Verilog circuit The extraction is probably done using the Programming Language Interface (PLI) which is a part of the Verilog language. PLI contains a number of routines that can access the internal Verilog data-structures after compilation. It can also pass data back and forth between the simulator and external c programs. Since the access functions are part of the Verilog standard, their calls are always the same independent of how the Verilog data-structures are organized. At least 3000 ps clk $Setup, $Hold and $Width More checks exist like $period and $skew At least At least 120 ps 200 ps and $setuphold. D Comment on Slide 25 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p Delay Classified by Max/Min Rise/Fall Verilog format triads (min: typ: max) assign #(1:2:3) g= a & b; value-changes (rising, falling, turn_off) assign #(2, 5, 7) g= a & b; value-changes may be triads assign #(1:2:3, 4:5:6, 6:7:8) g= a & b; 2. Delay Classified by Max/Min Rise/Fall In addition specify blocks can do (rising, falling, 0 z, z 1, 1 z, z 0) which can be triads. specify (a =>g) = (1:2:3, 4:5:6, 6:7:8, 3:4:5, 6:7:8, 3:4:5); Selecting min, typ, or max. Verilog will simulate with only one of the triad at a time. Choose one on the command line. > verilog your_file_name.v +maxdelays //or use +mindelays or +typdelays Interpretation of rise/fall Interpretation I Nonunate delay AND and OR gates are called positive unate. A rising input means the verifier will chose the rising delay. Similarly NAND and NOR are negative unate. XOR is nonunate, the verifier cannot tell if the output inverts, and must use the maximum delay. Negative delay In Out In Out t RISE start of Input change to end of output change Interpretation II common usage t RISE Input =1/2 or (0.37) to output =1/2 or (0.63) c=1 x x/x x/x x #(2,3) #(4,5)? #(4,2) 1 Delay 1 = 3 + 5(max) + 2 = 10 Delay 2 = 2 + 5(max) + 2 = 9 Watch out; the verifier did not get the worst case! Many simulators/verifiers interpret negative delays as 0.0. This may give an over-conservative clock-period. Comment on Slide 26 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 50

6 Specparam and Timing Checks Specparam and Timing Checks Specparam Define aliases for delays Easy to change delays by a text search. Helps avoid errors. Parameters are defined and used in the same block, except:-. Specparam for delay calculations Synthesizers and timing verifiers need to know load (fanout) related delays. Verilog cells store delay for one load only. Some cell models use specparam to store extra parameters used by a delay calculator to compute load related delays. Specify blocks for Verilog timing checks. $hold $setup $width Put these in a flip-flop model for automatic checking during simulation. $setuphold checks both, and allows negative limits. Specparam Module and(g, A, B) input A,B; output G; specify specparam AtoG_rise =3; specparam BtoG_rise =5; specparam fall =4; (A => G) = (AtoG_rise,fall); (D => G) = (BtoG_rise,fall); endspecify A B Specparam for external delay calculator specify specparam InCap$a=60, OutCap$z=40, R_Ramp$a$z=0.95:1.0:1.2; F_Ramp$a$z=0.80;0.95:1.0; (a => z)= (30:50:70, 25:45:63); endspecify a z Timing check functions specify specparam hold_lim = 120; $hold(posedge clk, D, hold_lim); $setup(d, posedge clk, 200); $width(posedge clk, 2000); endspecify 3, 4 G 5, 4 D clk 1D C1 Slide 24 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p Delay Classified by Max/Min Rise/Fall 2. Delay Classified by Max/Min Rise/Fall Verilog Notation triads (min: typ: max) assign #(1:2:3) g= a & b; value-changes (rising, falling, turn_off) assign #(2, 5, 7) g= a & b; value-changes may be triads assign #(1:2:3, 4:5:6, 6:7:8) g= a & b; Wire delays Can put delay on a wire Rise/Fall definition wire #(5:6:7) SlowLead; Rise/fall is usually defined input =1/2 to output =1/2. Verifiers must follow inversions They can ignore logic but they must keep track of rising/ falling delays. 0 x Delay 1 = Delay 2 = #(4,5) x 0 c=1 x x x #(4,3) x #(2,3) #(2,3) 1 #(4,3) = = 21 Negative Delays Happens if a very fast buffer squares up a very slow one. Verifiers may not handle negative delays. slow fast t RISE Input =1/2 to output =1/2 t RISE (neg) Slide 25 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 52

7 3. Delay models Delays For Cells 3. Delay models These models describe the internal cell delay and its interaction with its I/O signals. The interconnect delay between cells is not considered. Input slope delay The value of S is a function of the slope. For fast slopes S may be small. For slow slopes S may be 1, that is a slow input adds directly to the total propagation delay. 1 Propagation delay in practice 1. Verilog lumps all three into one number. Cells require an sdf file to change delays to account for loading. 2. Most data books ignore input slope and combine (T i +RCout) as one constant T pd = (T i + RCout) + RCload 3. Nonlinear effects: S is a function of input slope R is the channel resistance of a MOSFET which is nonlinear, as is much of the gate capacitance. Many delay calculators use tables to include these nonlinear function. 1. See Michael Smith, Application Specific Integrated Circuits, Addison Wesley, 1998, pp Comment on Slide 27 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p Delay models (cont) Interconnect Delay Two Models 1. The RC or L model which is simple. Many delay calculators add two time-constants: RdriverCdriver + Rnet(Cload+ Cload) 2. The Π model which is more complex. Placing half the capacitance on both sides means this model will give a faster delay. Two Types Of Tree 3. Delay models (cont) 1. Dividing each of the total lead resistance and total lead capacitance by the fanout N, and distributing it will predict shorter than actual delays. It is the default in some systems but is likely to give poor results for highresistance deep submicron leads. 2. Placing all of R N and C N in each lead will give worst case as a lower bound. This is a safer method. Comment on Slide 28 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 54

8 3. Delay models 3. Delay models Delays For Cells Input Slope delay Related to output delay for previous stage. T S = T T (prev)*s Intrinsic delay Fixed delay Output transition delay Usually the 63% charge time. T T = R(Cout + Cload) Total propagation delay T T = R(Cout + Cload) Input Slope Delay Caused by slow input transitions T S Cout T I Intrinsic Delay Fixed internal delay T T Output Transition Delay Depends on load T pd = T T (prev)*s + T I + T T Two-dimensional nonlinear delay models NLDM tables are often used because S and R are really nonlinear functions. Both T T and T pd must be calculated. input T T output load T pd input TT output load T T Slide 26 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p Delay models (cont) 3. Delay models (cont) Interconnect Delay R-C Model C only tree Use for wide leads where R is negligible. Balanced tree Divide total net R and C equally between all outputs. Worst-Case tree Put total R N and C N in series with all loads. Π Model Gives slightly faster and more accurate delay calculations Worst-Case tree Balanced tree R N 0 C out 1R 2 N R N C N 1 R 2 N 1C 2 N 1 C 2 N R N 1 C 2 N 1C 2 N C N 1R 2 N 1 R 2 N C load 1C 2 N 1C 4 N 1C 4 N Network lead has total resistance R N and capacitance C N The R-C model 1C 2 N R N The Π model R N C N 1CN 2 Slide 27 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 56

9 3. Delay models (cont) Elmore delay It is the first term (moment) in the series expansion for the exact delay. It is the dominant time-constant in the exact expression. One method for deriving the model is shown below. 1 It is as on the slide except node 4 was dropped. The current generators represent i = CdV/dt at each node. R1 =0 1 i1 R2 R3 2 i2 3 i3 V 1 = (R 1 C 1 + R 1 C 2 + R 1 C 3 )dv 1 /dt V 2 =(R 1 C 1 + (R 1 +R 2 )C 2 + R 1 C 3 )dv 2 /dt V 3 =(R 1 C 1 + R 1 C 2 + (R 1 +R 3 )C 3 )dv 3 /dt 3. Delay models (cont) Use i=cdv/dt. Then to find V j at node j, assume dv i /dt at all other nodes equals dv j /dt at node j. Use superposition to find each node voltage. V 1 =R 1 i 1 + R 1 i 2 + R 1 i 3 V 2 =R 1 i 1 + (R 1 +R 2 )i 2 + R 1 i 3 V 3 =R 1 i 1 + R 1 i 2 + (R 1 +R 3 )i 3 Solve the differential equations:- V i = V i (t=0) exp(-t/τ i ) τ 1 = R 1 C 1 + R 1 C 2 + R 1 C 3 ) τ 2 = R 1 C 1 + (R 1 +R 2 )C 2 + R 1 C 3 τ 3 = R 1 C 1 + R 1 C 2 + (R 1 +R 3 )C 3 1. See Michael Smith, Application Specific Integrated Circuits, Addison Wesley, 1998, pp Comment on Slide 29 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p Delay models (cont) Comment on Slide 30 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 58

10 3. Delay models (cont) 3. Delay models (cont) Elmore delay An fairly accurate, easy to calculate model. It puts the right R N and C N in the paths. Combines a good model and a good tree. Elmore calculation τ Delay between node 0 (source) and node i (sink) is: i = C n R k n k n sums over all capacitances. k sums over all R common to the path between: (1) nodes i and 0, and (2) nodes n and 0. 0 R1 1 C1 R2 R3 2 C2 C3 R4 4 C4 τ 1 = R 1 C 1 + R 1 C 2 + R 1 C 3 + R 1 C 4 ) τ 2 = R 1 C 1 + (R 1 +R 2 )C 2 + R 1 C 3 + R 1 C 4 τ 3 = R 1 C 1 + R 1 C 2 + (R 1 +R 3 )C 3 + (R 1 +R 3 )C 4 τ 4 = R 1 C 1 + R 1 C 2 + (R 1 +R 3 )C 3 + (R 1 +R 3 +R 4 )C 4 τ 1 τ 2 τ 3 τ 4 Slide 28 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 59 Models Models If timing is critical Summary Elmore delay is the best commonly avaliable and should not slow simulation. With it you have the best tree and a good delay model. Try to get input slew incorporated. Watch out for treatment of negative delays. Slide 29 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 60

11 Comment on Slide 31 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 61 Comment on Slide 32 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 62

12 Models Slide 30 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 63 Models Slide 31 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 64

13 Comment on Slide 33 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 65 Comment on Slide 34 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 66

14 Models Slide 32 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 67 Models Slide 33 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 68

15 Comment on Slide 35 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 69 Comment on Slide 36 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 70

16 Models Slide 34 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 71 Models Slide 35 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 72

17 Comment on Slide 37 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 73 Comment on Slide 38 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 74

18 Models Slide 36 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 75 Models Slide 37 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 76

19 Comment on Slide 39 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 77 Comment on Slide 40 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 78

20 Models Slide 38 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 79 Models Slide 39 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 80

21 Comment on Slide 41 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 81 Comment on Slide 42 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 82

22 Models Slide 40 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 83 Models Slide 41 Modified; March 22, 2000 Strategic Microelectronics Consortium Digital Circuits p. 84

Post-Synthesis Simulation. VITAL Models, SDF Files, Timing Simulation

Post-Synthesis Simulation. VITAL Models, SDF Files, Timing Simulation Post-Synthesis Simulation VITAL Models, SDF Files, Timing Simulation Post-synthesis simulation Purpose: Verify correctness of synthesized circuit Verify synthesis tool delay/timing estimates Synthesis