Asynchronous Transmission. Asynchronous Serial Communications & UARTS

Transcription

1 Asynchronous Transmission Asynchronous Serial Communications & UARTS 55:036 Embedded Systems and Systems Software asynchronous: transmitter and receiver do not share a common clock or explicitly coordinate the exchange of data Transmitter can wait arbitrarily long between transmissions Receiver must figure out how to properly extract data from the received waveform when a new character starts the individual bits of the character Used, for example, when transmitter such as a keyboard may not always have data ready to send Possible Signaling Schemes Transmission Timing Issues Encoding scheme leaves several questions unanswered: How long will each bit last? How will the transmitter and receiver agree on timing? Standards specify operation of communication systems Devices from different vendors that adhere to the standard can interoperate Example organizations: International Telecommunications Union (ITU) Electronic Industries Association (EIA) Institute for Electrical and Electronics Engineers (IEEE) International Standards Organization (ISO) RS232/422 is the prevailing standard for asynchronous serial communications 1

2 RS-232 Standard for serial transfer of characters across copper wire Produced by EIA Full name is RS-232-C RS-232 defines serial, asynchronous communication Serial - bits are encoded and transmitted one at a time (as opposed to parallel transmission) Asynchronous - characters can be sent at any time and bits are not individually synchronized There is also a differential (twisted pair) version of RS-232 intended to operate over longer distances (RS-422) Logical 0 (space) between +3 v and +15 v. (nominally +12 V) Logical 0 (space) between +3 v and +15 v. (nominally +12 V) Logical 1 (Mark) between -3 v and -15 v. (nominally -12 V) 2

3 Idle line is in mark state Character transmission begins with a start-bit Followed by data bits (7 or 8), LSB first Followed by (optional) parity bit 3

4 Followed by one or more stop bits. Line will stay in mark state until start of next character transmission A Logical View of the Previous Diagram LSB Stop bit(s) MSB Start Bit Seven data bits Even parity Converting between RS-232 and TTL Logic levels Converting between RS-232 and TTL Logic levels Note: The QwikFlash Board uses a simple two line (plus GND) RS-232 connection i.e. no RTS/CTS flow control 4

5 RS-232 Bit-level Synchronization Low-speed: RS-232 Bit-level Synchronization Low-speed: High speed; Note: Rx sampling clock runs at 16x baud rate When Rx detects leading edge of start bit, it counts 8 ticks of sampling clock to locate middle of start bit. Then strobes remaining bit values as 16-tick intervals Doing RS-232 on a Microcontroller Two ways: In software bit-banging via a Universal Asynchronous Receiver/Transmitter (UART) Using the PIC UART Once the UART is configured, it does all the work To transmit a byte, simply write it to the UART s TXREG To receive a byte, simply read it from the UART s RXREG 5

6 Using the PIC UART Once the UART is configured, it does all the work To transmit a byte, simply write it to the UART s TXREG To receive a byte, simply read it from the UART s RXREG Using the PIC UART Once the UART is configured, it does all the work To transmit a byte, simply write it to the UART s TXREG To receive a byte, simply read it from the UART s RXREG The transmitter interrupt flag (TXIF) is cleared by a write to TXREG and set when transmission of the byte is complete The receiver interrupt Flag (RXIF) is set when an incoming data byte is available in the RXREG. Automatically cleared when the data is read from the RXREG Using the PIC UART Once the UART is configured, it does all the work To transmit a byte, simply write it to the UART s TXREG To receive a byte, simply read it from the UART s RXREG The UART has a small (2 byte) internal RX queue (FIFO) in case the PIC runs behind in reading incoming bytes from the RXREG Using the PIC UART, continued The UART can be configured to generate interrupts from: The RXIF bit (Rx data ready) The ISR should read RXREG to receive the new incoming byte The TXIF bit (Tx ready) The ISR should send the next outgoing byte to the TXREG or disable further TXIF interrupts if no more bytes to send 6

7 The UART Clock Generator The UART Clock Generator Eight bit counter, clocked at f osc The UART Clock Generator The UART Clock Generator Determined by BRGH Eight bit counter, clocked at f osc fosc /(SPBRG+1) Eight bit counter, clocked at f osc fosc /(SPBRG+1) Baud Rate: f osc /(SPBRG+1)16 or f osc /(SPBRG+1)64 7

8 Setting the Baud Rate Achievable Baud rates (BRGH=1) Baud Rate = BRGH=1 (High rate) BRGH=0 (Low Rate) Achievable Baud Rates (BRGH=0) Additional UART Configuration Details Consult: PIC Data Sheet Chapter 18 in the text 8