Active-HDL. Getting Started
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- Leslie Anthony
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1 Active-HDL Getting Started Active-HDL is an integrated environment designed for development of VHDL designs. The core of the system is a VHDL simulator. Along with debugging and design entry tools, it makes up a complete system that allows you to write, debug and simulate VHDL code. Based on the concept of a design, Active-HDL allows you to organize your VHDL resources into a convenient and clear structure. Students can use Active-HDL to perform following tasks: development of the VHDL based designs, functional simulation of their code, functional simulation of the synthesized code, timing simulation of the hardware implementation. From this tutorial you can learn how to: 1. Create a new design page 2, 2. Compile and debug your design page 6, 3. Perform simulation page 9. 1
2 1. Creating a new design After starting Active-HDL a Getting Started window will pop up. Choose Create new design. The design wizard will give you a chance to type the name of your design and its location. Name of your design Location of the design folder 2
3 Next you can choose the way to create your design resources. If you wish to create your source files now using wizard s help, choose Create new source files now. If you have your source files already created and you want to simply add them to the design, choose Add existing resource files. Choose Create an empty design if you wish to do so. If you have chosen Create new source files now option, the wizard will let you to create all entities you want to have in your design. You can create/delete entities by clicking on the New/Delete button. Each entity is characterized by name and source type: VHDL, state diagram, or block diagram. 3
4 You can also specify all inputs and outputs to every entity by clicking on the Ports button. For every port you can specify: name direction in for inputs, out for outputs, inout for bi-directional signals type use std_logic or std_logic_vector only array index to create vectors. When you are done with creating your entities, the wizard will show you current design specification. After you click Finish your design is finally created. Your source files are listed in the Design Browser window under Files Tab. Notice that every entity has 4
5 already its port part created, but architecture is empty. Your task is to supplement missing code. source files ports are already created architecture is empty 5
6 2. Compiling designs Compilation of the VHDL code is necessary to create simulation model of the described circuit. The compiler checks all the syntax and writes all the necessary information in the internal binary format. It should be clearly noted that the compiler s ability to find errors is limited to syntax errors only. Many other errors and mistakes can be found only when performing thorough simulation. It is also important to understand that the compilation does not produce any synthesized code for implementation purposes. This task is performed in Foundation Series exclusively. 2.1 Compiling selected files Select the file you want to compile and press button the keyboard. This will start compilation. or press F11 on 6
7 If everything went right during the compilation, you should see check mark near your file. You can also expand the branch headed by the library icon to see that all compiled entities and architectures have been added to the project library. check mark compiled entities messages from compiler If the compilation process did not end with success, the compiler will produce meaningful descriptions of errors. All places in your code where errors were found will be highlighted. architecture has not been compiled to the library errors found in this entity located errors 7
8 2.2 Compiling all files The entire design can be compiled at once by pressing buttons: or. If all the entities in the design are organized in the clear hierarchical structure, the compiler will automatically recognize the top-level entity. However, if distinct hierarchies of entities exist, the compiler will leave the choice of the top-level entity for you. More than one top-level entities detected 8
9 3. Simulating the design Simulation can be performed when the entire design has been successfully compiled. It means that the simulation model of all elements has been created. Simulator can be configured to stimulate all inputs to the circuit, however students should learn to write test benches top-level testers described behaviorally. The task of test bench is to produce all the stimulation to the tested circuit to verify its correctness. Once the test bench is created, performing simulation becomes an easy task. Simulation is performed in a graphical way simulator plots waveforms of all signals being of designer s interest. To create an empty waveform click on the button. Next add desired signals by clicking on the button. signals can be selected from any level in hierarchy select desired signals 9
10 When you are done with adding signals, you can attempt to perform simulation. There are three slightly different ways to run it: by pressing button - the simulation will run until you will stop it by pressing. by pressing button - the simulation will run until specified point of time will be reached. by pressing button - the simulation will run for specified amount of time. The result of simulation is represented in the form of waveforms. You can always restart simulation by pressing button. 10
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