VHDL introduction Notes

Transcription

1 UH Hawaii Manoa 475 Electronics for physicists VHDL introduction Notes Author: Andrej Seljak Date: Fall 2016 update 1

2 Ver: 1.0 Table of Contents 1. FPGA description3 2. USB EVALUATION board 4 3. ISE Xilinx programming tools Introduction ISE environment presentation 6 4. Basics of VHDL coding 9 5. ISim simulator 9 Associate the file with the file you want to simulate. 10 The software generates a new file for you. Note that the file does not appear in the left top window. However if you switch from Implementation to Simulation you will see it. This is convenient to separate the design with the test benches. 10 You can now setup the stimulus signals. Test bench files are written in VHDL code as well. 10 Selecting Simulation in the menu, selecting your test file containing your file under test and double clicking on Simulate Behavioral Model will start Isim. This is what you expect to see. Your code behaving as you expect. 11 This concludes the basic step by step tutorial USB evaluation board example FPGA description Contemporary field-programmable gate arrays (FPGAs) have large resources of logic gates and RAM blocks to implement complex digital computations. Some FPGAs have analog features in addition to digital functions. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring or couple unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slowly [1]. 2

3 Figure 1. Left a picture of an FPGA on a printed circuit board. Right, a simplified basic cell. Programming an FPGA requiers the use of description languages. The most commonly used are Verilog and VHDL (VHSIC Hardware Description Language). VHDL language is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as fieldprogrammable gate arrays and integrated circuits. VHDL can also be used as a 3

4 general purpose parallel programming language[1]. Once the description of the circuit has being made, the compiler will take over and generate a programming file. This file is introduced into the FPGA via a JTAG controller and sets the basic cells to behave as described in the program. Worth mentioning, that FPGAs come in different sizes and clocking speed options. Fpga vendors provide also a programming environment for their products. We will use Xilinx tools for the demonstration. 2. USB EVALUATION board An evaluation board is commonly used during the development process of a project. It allows to advance quickly with the proof of concept for a particular project. Figure 2. A picture of the USB evaluation board developed in the ID laboratory. 4

5 The evaluation board you are about to use holds an Xilinx Spartan3AN FPGA, a JTAG connector, power supply connector, a reset button, push buttons, a 16 bit configurable IO connected also to LEDs and an expansion connector. The expansion connector allows to extend the number of I/O ports with another board which will be described later. The schematic drawings of the board are available within the folder provided by your instructor. 3. ISE Xilinx programming tools 3.1 Introduction In order to program an FPGA we need an environment which allows as to write the code, compile it, simulate the code and download it on the target device. The following steps are a rudimentary path explanation on how to successfully make a custom circuit: - For programming the board we use ISE in the Xilinx. - Once the code is written, it can be synthesized and simulated using Isim. - Satisfied with the code working as expected, we can now generate the bitfile. Before doing so, we need to include the so called UCF file. This file links the signals from our code to the physical pins of the device. The generation of the bitfile is made in ISE program. - Using Impact software we download the code on the FPGA. As soon as the file is written in the chip the operation starts. By pressing the hard reset button, a new download will be needed. - The Spartan3AN has also a PROM memory inside, which allows do store a bit file indefinitely. This file will automatically load at every power up of the device. We will see later how to proceed in order to achieve so. 3.2 ISE environment presentation Go to start menu, find the Xilinx folder and start ISE. 5

6 Invoke File new project, choose a directory and the name of your project. Define the device you want to use. For our case, copy the settings from the picture below. Finish the process by clicking next. 6

7 In order to make a file you can write in, click marked icon and choose VHDL module. Give it a name and click next. and define your inputs and outputs. In the next window you can name 7

8 Click next to finish the process. A window like this will appear. Inverter code Module definition 8

9 Libraries included The left top window shows the files which are present in the project. Under the window which allows you to run commands. The entire right window is typically used to display the code. The bottom window is a console window, where compiler warnings and errors will appear. Double click on View RTL schematic will show the block diagram. 4. Basics of VHDL coding Internet is a good staring point. There are a number of VHDL tutorials. For convenience, here are a few useful web pages: A good starting point is to understand the definition for signals followed by logical operators. The next step would be to instantiate modules inside other modules and proceed with the understanding how to build state machines. Its a lot to digest, so make sure, you understand thing well before proceeding. Keep in mind you are building your own digital chip! 9

10 5. ISim simulator The next thing we need is to simulate the code. Coming back to our model of inverter. We want to see if the code behaves accordingly. In order to do so, add a new file. This time choose VHDL Test Bench 10

11 Associate the file with the file you want to simulate. The software generates a new file for you. Note that the file does not appear in the left top window. However if you switch from Implementation to Simulation you will see it. This is convenient to separate the design with the test benches. 11

12 You can now setup the stimulus signals. Test bench files are written in VHDL code as well. Selecting Simulation in the menu, selecting your test file containing your file 12

13 under test and double clicking on Simulate Behavioral Model will start Isim. This is what you expect to see. Your code behaving as you expect. This concludes the basic step by step tutorial. 6. USB evaluation board example Folder content: - Documentation containing USB_eval board schematic and chips data sheets. - Original_files contains separate of files for running ADC, DAC... - USB_eval, The start point for your project containing code for ADC and DAC where you can start from. - Isim simulator 13

14 Figure x. Picture of the extension board. USB eval board example. A firmware which reads the ADC and writes to DAC the value. 14

15 Install ISE and open the USB_eval.xise in the USB_eval directory. 15

16 Left top window shows the files in the project. The left bottom window shows the commands starting from code synthesize to file bit file generation. 16