LINECARD SOLUTIONS WITH THE IDT8216X1 AND IDT821054A. Microprocessor. MPI Interface. Level Metering. LH SLIC 3 # (IDT8216x1) DSP.
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1 LINECARD SOLUTIONS WITH THE IDT8216X1 AND IDT824A Application Note IDT ADVANTAGE V (CODEC & SLIC) and Battery Power Supply DSP-Based: Single LineCard Design Meets Different Standards Worldwide Internal Polarity Reversal On-Chip Thermal Management Less External Components High Reliability and Robust (ESD > V, Latch-up > ma) Cost-Effective OTHER FEATURES OF THE SLIC: Slic operating states: Active, Reverse Active, Ringing, Standby and Disconnect Low Standby power consumption ( mw) -19 V to -8 V Battery Supply On-Hook Transmission Two-Wire impedance set by single external impedance Programmable constant-current feed Programmable loop-detect threshold and ring-trip detect threshold Three on-chip relay drivers and relay snubbers Programmable digital filters adapting to different requirements: AC impedance matching Transhybrid balance Frequency response correction Gain adjustment Programmable A/u-law compressed or linear code conversion Supports two programmable PCM buses and MPI interface 7 SLIC signaling pins per channel Two programmable dual tone generators per channel Two programmable chopper clocks Advanced test capability (level metering and programmable loopbacks) TOTAL SOLUTION BLOCK DIAGRAM Microprocessor MPI Interface Telephone LH SLIC 1 # (IDT8216x1) Level Metering Dual Tone DSP LH SLIC 3 # (IDT8216x1) Telephone Quad CODEC (IDT824A) Telephone LH SLIC 2 # (IDT8216x1) Digital filters Chopper Clocks Test Loopbacks Hardware Ringtrip LH SLIC 4 # (IDT8216x1) Telephone PCM Interface PCM Highway 6429 drw1 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 SEPTEMBER 29, 4 4 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-6429/1
2 SLIC FUNCTIONAL BLOCK DIAGRAM TMG Relay Driver RYOUT2 Relay Driver RYOUT1 A (TIP) Ring Relay Driver RINGOUT HPA Two-Wire Interface Digital Interface D1 D2 C1 C2 C3 DET HPB B (RING) Signal Transmission Off-hook Detector Power Feed Controller VTX RSN RD RDC CAS DA DB VBAT BGND Ring-trip Detector VCC VBREF AGND 6429 drw2 2
3 CODEC FUNCTIONAL BLOCK PROGRAM CH1 CH3 VIN1 Filter and A/D Filter and A/D VIN3 VOUT1 D/A and Filter DSP D/A and Filter VOUT3 2 Inputs 3 I/Os 2 Outputs SLIC Signaling Core SLIC Signaling 2 Inputs 3 I/Os 2 Outputs CH2 CH4 MCLK CHCLK1 CHCLK2 PLL and Clock Generation General Control Logic MPI Interface PCM Interface DR1 DR2 DX1 DX2 RESET INT12 INT34 CCLK CS CI CO FS BCLK TSX1 TSX drw3 3
4 CODEC SIGNAL FLOW DIAGRAM LREG1: CS[3] CS[3] = 1: enable (normal) CS[3] = : disable (bypass) Transmit KHz TS PCM Highway MHz Level Meter LPF/AA D1 GTX D2 LPF FRX HPF CMP TSA DX1/DX2 DLB-DI ALB-DI DLB-PCM DLB-8K ALB-8K IMF ECF GIS DLB_1BIT ALB-1BIT DLB-ANA DR1/DR2 VIN VOUT EXP TSA LPF/SC U1 UF GRX U2 LPF FRR Dual Tone Receive Path CUT-OFF-PCM LREG1: CS[1] CS[1] = 1: enable (normal) CS[1] = : disable (cut) LREG1: CS[] CS[] = 1: enable (normal) CS[] = : disable (cut) LREG1: CS[2] CS[2] = 1: enable (normal) CS[2] = : disable (cut) Bold Black Framed: Programmable Filters Fine Black Framed: Fixed Filters 6429 drw4 4
5 6429 drw24b
6 c 6429 drw23b 6
7 COMPONENTS LIST: Designator Description Part Type Precision Maximum Power/Voltage Other CAS Capacitor.1uF % V CNF Capacitor.1uF % 16V CRC Capacitor 2.2nF % V CTC Capacitor 2.2nF % V CTX Capacitor.1uF % 16V CRX Capacitor.1uF % 16V CD Capacitor.1uF % 16V CVCC Capacitor.1uF % 16V CBAT Capacitor.1uF % V CHP Capacitor.27uF % V CDC Capacitor.27uF % 16V CRT1 Capacitor 33nF % V CRT2 Capacitor 33nF % V RR2 Resister 4M % 1/4W RR3 Resister 3.4M % 1/4W RTMG Resister 2K % 1W RR Resister 3.4M % 1/4W RDC2 Resister 27K 1 % 1/4W RDC1 Resister 27K 1 % 1/4W RD Resister 36K 1 % 1/4W RRX Resister 1K 1 % 1/4W RT Resister 1K 1 % 1/4W RR1 Resister 8 % 1W RR4 Reisister 4M % 1/4W RF1 Fuse 1% 1W RF2 Fuse 1% 1W D1 DIODE V, ma U1 IDT824A U2 IDT8216x1 J1 Relay 7
8 COEFFICIENTS IN DSP RAM 6Ω The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: db Coefficients in the DSP Ram From low address to high address: IMF Ram: C6 FD 6B 4 ECF Ram: 42 F4 A4 4 4 CE E GIS + Dual Tone Ram: 8 FC FRX + GTX Ram: 7 37 F F F 7 FRR + GRX Ram: B 3E B 3E CE 84 1D 1. Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to 6 db by setting the GAD bit in LREG9 to "1"; 3. Set the analog gain of D/A to db by setting the GDA bit in LREG9 to "". 8
9 Total Distortion - A (A2D) (For 6Ω impedance, system target gain of A2D: db; system target gain of D2A: db) Level(dBm) A(A2D) drw 9
10 Total Distortion - A (D2A) (For 6Ω impedance, system target gain of A2D: db; system target gain of D2A: db) Level(dBm) A(D2A) drw6
11 COEFFICIENTS IN DSP RAM 6Ω The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: -3. db Coefficients in the DSP Ram From low address to high address: IMF Ram: C6 FD 6B 4 ECF Ram: 42 F4 A4 4 4 CE E GIS + Dual Tone Ram: 8 FC FRX + GTX Ram: 7 37 F F F 7 FRX + GRX Ram: B 3E B 3E CE 84 9A Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to 6 db by setting the GAD bit in LREG9 to "1"; 3. Set the analog gain of D/A to db by setting the GDA bit in LREG9 to "". 11
12 Total Distortion - A (A2D) (For 6W impedance, system target gain of A2D: db; system target gain of D2A: -3.dB) Level (dbm) A(D2A) drw7 12
13 Total Distortion - A (D2A) (For 6Ω impedance, system target gain of A2D: db; system target gain of D2A: -.3.dB) Level (dbm) A(D2A) drw8 13
14 COEFFICIENTS IN DSP RAM 6Ω The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: -7 db Coefficients in the DSP Ram From low address to high address: IMF Ram: F 1 C1 3 ECF Ram: 1 FA A B 6 3 4C E1 GIS + Dual Tone Ram: 18 F4 FRX + GTX Ram: 6E 19 F F3 6E E2 7 FRR + GRX Ram: 1C E 28 3E 4 1C 1 CE A 1. Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to 6 db by setting the GAD bit in LREG9 to "1"; 3. Set the analog gain of D/A to -6 db by setting the GDA bit in LREG9 to "1". 14
15 Total Distortion - A (A2D) (For 6Ω impedance, system target gain of A2D: db; system target gain of D2A: -7dB) Level (dbm) A(D2A) drw9
16 Total Distortion - A (D2A) (For 6Ω impedance, system target gain of A2D: db; system target gain of D2A: -.7dB) Level (dbm) A(D2A) drw 16
17 COEFFICIENTS IN DSP RAM 9Ω The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: db Coefficients in the DSP Ram From low address to high address: IMF Ram: F 26 F EE ECF Ram: CE F CC F7 E GIS + Dual Tone Ram: B8 A4 FRX + GTX Ram: 3E FF 42 F2 4 1F 4 1F 42 F2 3E FF 66 3E 9 C FRR + GRX Ram: CD 1 33 F3 F 22 F F3 CD 1 CD 24 E Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to db by setting the GAD bit in LREG9 to ""; 3. Set the analog gain of D/A to db by setting the GDA bit in LREG9 to "". 17
18 Total Distortion - A (A2D) (For 9Ω impedance, system target gain of A2D: db; system target gain of D2A: db) Level (dbm) A(A2D) drw11 18
19 Total Distortion - A (D2A) (For 9Ω impedance, system target gain of A2D: db; system target gain of D2A: db) Level (dbm) A(D2A) drw12 19
20 COEFFICIENTS IN DSP RAM 9Ω The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: -3. db Coefficients in the DSP Ram From low address to high address: IMF Ram: F 26 F EE ECF Ram: CE F CC F7 E GIS + Dual Tone Ram: B8 A4 FRX + GTX Ram: 3E FF 42 F2 4 1F 4 1F 42 F2 3E FF 66 3E 9 C FRR + GRX Ram: CD 1 33 F3 F 22 F F3 CD 1 CD 24 4E F 1. Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to db by setting the GAD bit in LREG9 to ""; 3. Set the analog gain of D/A to db by setting the GDA bit in LREG9 to "".
21 Total Distortion - A (A2D) (For 9Ω impedance, system target gain of A2D: db; system target gain of D2A: -3.dB) Level (dbm) A(A2D) drw13 21
22 Total Distortion - A (D2A) (For 9Ω impedance, system target gain of A2D: db; system target gain of D2A: -3.dB) Level (dbm) A(D2A) drw14 22
23 COEFFICIENTS IN DSP RAM 9Ω The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: -7 db Coefficients in the DSP Ram From low address to high address: IMF Ram: F 26 F EE ECF Ram: CE F CC F7 E GIS + Dual Tone Ram: B8 A4 FRX + GTX Ram: 3E FF 42 F2 4 1F 4 1F 42 F2 3E FF 66 3E 7 6 FRR + GRX Ram: CD 1 33 F3 F 22 F F3 CD 1 CD 24 2D Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to 6 db by setting the GAD bit in LREG9 to "1"; 3. Set the analog gain of D/A to -6 db by setting the GDA bit in LREG9 to "1". 23
24 Total Distortion - A (A2D) (For 9Ω impedance, system target gain of A2D: db; system target gain of D2A: -7dB) Level (dbm) A(A2D) drw 24
25 Total Distortion - A (D2A) (For 9Ω impedance, system target gain of A2D: db; system target gain of D2A: -7dB) Level (dbm) A(D2A) drw16
26 COEFFICIENTS IN DSP RAM (Ω & 68 Ω.1µF) The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: db Coefficients in the DSP Ram From low address to high address: IMF Ram: B8 DC AF D ECF Ram: DC F6 94 3A B BC DF GIS + Dual Tone Ram: F4 7 FRX + GTX Ram: 1 1 9D ED D ED F4 FRR + GRX Ram: 3C 19 D D7 3C Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to 6 db by setting the GAD bit in LREG9 to "1"' 3. Set the analog gain of D/A to db by setting the GDA bit in LREG9 to "". 26
27 Total Distortion - A (A2D) (For China complex impedance, system target: gain of A2D is db; gain of D2A is db) Level (dbm) A(A2D) drw17 27
28 Total Distortion - A (D2A) (For China complex impedance, system target: gain of A2D is db; gain of D2A is db) Level (dbm) A(A2D) drw18 28
29 COEFFICIENTS IN DSP RAM (Ω &68Ω.1µF) The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: -3. db Coefficients in the DSP Ram From low address to high address: IMF Ram: B8 DC AF D ECF Ram: DC F6 94 3A B BC DF GIS + Dual Tone Ram: F4 7 FRX + GTX Ram: 1 1 9D ED D ED F4 FRR + GRX Ram: 3C 19 D D7 3C E 1. Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to 6 db by setting the GAD bit in LREG9 to "1"; 3. Set the analog gain of D/A to db by setting the GDA bit in LREG9 to "". 29
30 Total Distortion - A (A2D) (For China complex impedance, system target: gain of A2D is db; gain of D2A is -3.dB) Level (dbm) A(A2D) drw19
31 Total Distortion - A (D2A) (For China complex impedance, system target: gain of A2D is db; gain of D2A is -3.dB) Level (dbm) A(D2A) drw 31
32 COEFFICIENTS IN DSP RAM (Ω & 68Ω.1µF) The system target gain from tip / ring to digital port: db The system target gain from digital port to tip / ring: -7 db Coefficients in the DSP Ram From low address to high address: IMF Ram: B8 DC AF D ECF Ram: DC F6 94 3A B BC DF GIS + Dual Tone Ram: F4 7 FRX + GTX Ram: 1 1 9D ED D ED F4 FRR + GRX Ram: 3C 19 D D7 3C Select filter coefficients in the Coe-RAM by setting LREG1 to FFH; 2. Set the analog gain of A/D to 6 db by setting the GAD bit in LREG9 to "1"; 3. Set the analog gain of D/A to db by setting the GDA bit in LREG9 to "". 32
33 Total Distortion - A (A2D) (For China complex impedance, system target: gain of A2D is db; gain of D2A is -7dB) Level (dbm) A(A2D) drw21 33
34 Total Distortion - A (D2A) (For China complex impedance, system target: gain of A2D is db; gain of D2A is -7dB) Level (dbm) A(D2A) drw22 34
35 Document History 9/27/4 pgs. 8, 11, 14, 17,, 26, 29, 32 CORPORATE HEADQUARTERS for SALES: for Tech Support: 297 Stender Way or Santa Clara, CA 94 fax:
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